936 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES.VOL.57.NO.4.APRIL 2009 VI.CONCLUSION [9]D.Hauspie,E.-C.Park,and J.Craninckx,"Wideband VCO with simul- taneous switching of frequency band,active core,and varactor size," Having a constant bandwidth is essential for phase-noise op- IEEE J.Solid-State Circuits,vol.42.no.7.pp.1472-1480.Jul.2007. timization and ensuring loop stability for wideband frequency [10]T.Nakamura,T.Masuda,N.Shiramizu,K.Washio,T.Kitamura,and synthesizers.This paper reports a fully integrated 1.175-2-GHz N.Hayashi,"A wide-tuning-range VCO with small VCO-gain fluctu- ation for multi-band W-CDMA RFIC,"in Proc.Eur.Solid-State Cir- frequency synthesizer with a constant loop bandwidth for cuits Conf..Sep.2006.pp.448-451. DVB-T applications.Techniques for achieving a constant syn- [11]T.Y.Lin,T.Y.Yu,L.W.Ke,and G.K.Dehng."A low-noise VCO with a constant Fvco for GSM/GPRS/EDGE applications,"in Proc. thesizer loop bandwidth are proposed.To overcome the VCO IEEE Radio Freq.Integr.Circuits Symp.,Jun.208.pp.387-390. gain Kvco and the band step fres variations,a technique by [12]H.Lee,J.-K.Cho,K.-S.Lee.I-C.Hwang.T.-W.Ahn,K.-S.Nah, and B.-H.Park,"A C-L fractional-V frequency synthesizer using a simultaneously adjusting both the sizes of switched capacitors wide-band integrated VCO and a fast AFC technique for GSM/GPRS/ and varactors is developed.The procedure for calculating WCDMA applications,"IEEE J.Solid-State Circuits,vol.39,no.7,pp the switching capacitor and varactor sizes at each frequency 1164-1169,jul.2004. [13]K.-S.Lee,E.-Y.Sung,I.-C.Hwang,and B.-H.Park,"Fast AFC tech- band is also described.Furthermore,the CP current Icp is nique using a code estimation and binary search algorithm for wide- programmed to compensate the variation of division ratio N.In band frequency synthesis,"in Proc.Eur.Solid-State Circuits Conf., addition,an impedance transformation method is employed to Sep.2005,pp.448-451. [14]Z.Tang,J.He,and H.Min,"A low-phase-noise 1-GHz LC VCO dif- reduce the die area of the LPF allowing its on-chip integration. ferentially tuned by switched step capacitors,"in IEEE Asian Solid. The synthesizer was fabricated and validated in a 0.18-um State Circuits Conf..Nov.2005.pp.409-412. CMOS process.It achieved a normalized tuning range of 52% [15]E.Hegazi.H.Sjoland,and A.A.Abidi,"A filtering technique to lower LC oscillator phase noise,"IEEE J.Solid-State Circuits,vol.36,no using a single LC VCO,and a less than 12.5%VCO gain 12,Pp.1921-1930.Dec.2001」 Kvco variation,as well as a less than 4.5%band step fres [16]P.Andreani and S.Mattisson,"On the use of MOS varactors in RF VCO's,"IEEE J.Solid-State Circuits.vol.35,no.6,pp.905-910,Jun variation.The in-band phase noise at a 10-kHz offset is below 20D00 -97 dBc/Hz and the integrated phase error from 100 Hz to [17]R.L.Bunch and S.Raman,"Large-signal analysis of MOS varactors 10 MHz is0.63mIt has a nearly constant 3-dB closed-loop in CMOS-G LC VCOs."IEEE J.Solid-State Circuits.vol.38.no. 8.Pp.1325-1332,Aug.2003. bandwidth and a flat phase-noise characteristic across the entire [18]S.Cheng,H.Tong,J.Silva-Martinez,and A.I.Karsilayan,"Design wide frequency tuning range.The synthesizer consumes only and analysis of an ultrahigh-speed glitch-free fully differential charge 18 mW with a 1.8-V supply. pump with minimum output current variation and accurate matching," IEEE Trans.Circuits Syst.II,Exp.Briefs,vol.53.no.9.pp.843-847. Sep.2006. [19]M.Terrovitis,M.Mack,K.Singh,and M.Zargari,"A 3.2 to 4 GHz ACKNOWLEDGMENT 0.25 Ni CMOS frequency synthesizer for IEEE 802.11a/b/g WLAN." in IEEE Int.Solid-State Circuits Conf.Tech.Dig..Feb.2004.pp.95-96. The authors would like to thank L.Yang and X.Duo,both [20]K.Shu,E.Sanchez-Sinencio,J.Silva-Martinez,and S.Embabi,"A with the Semiconductor Manufacturing International Corpora- 2.4-GHz monolithic fractional-V frequency synthesizer with robust phase switching prescaler and loop capacitance multiplier,"IEEE J. tion (SMIC),Shanghai,China,for providing chip fabrication Solid-State Circuits,vol.38,no.6,pp.866-874,Jun.2003. and testing support.The authors would also like to thank the [21]C.S.Vaucher,I.Ferencic,M.Locher,S.Sedvallson.U.Voegeli,andZ. reviewers for the comments and suggestions,which help to im- Wang,"A family of low-power truly modular programmable dividers in standard 0.35-Ni CMOS technology."IEEE /Solid-State Circuits. prove the quality of this paper. vol.35,no.7,pp.1039-1045,Jul.2000. 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To overcome the VCO gain and the band step variations, a technique by simultaneously adjusting both the sizes of switched capacitors and varactors is developed. The procedure for calculating the switching capacitor and varactor sizes at each frequency band is also described. Furthermore, the CP current is programmed to compensate the variation of division ratio . In addition, an impedance transformation method is employed to reduce the die area of the LPF allowing its on-chip integration. The synthesizer was fabricated and validated in a 0.18- m CMOS process. It achieved a normalized tuning range of 52% using a single VCO, and a less than 12.5% VCO gain variation, as well as a less than 4.5% band step variation. The in-band phase noise at a 10-kHz offset is below 97 dBc Hz and the integrated phase error from 100 Hz to 10 MHz is 0.63 . It has a nearly constant 3-dB closed-loop bandwidth and a flat phase-noise characteristic across the entire wide frequency tuning range. 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Wang, “A family of low-power truly modular programmable dividers in standard 0.35- ￾m CMOS technology,” IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 1039–1045, Jul. 2000. [22] A. Maxim, R. Poorfard, and J. Kao, “A sub-1.5 phase-noise ring-os￾cillator-based frequency synthesizer for low-IF single-chip DBS satel￾lite tuner-demodulator SoC,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2006, pp. 618–619. [23] M. Marutani, H. Anbutsu, M. Kondo, N. Shirai, H. Yamazaki, and Y. Watanabe, “An 18 mW 90 to 770 MHz synthesizer with agile auto￾tuning for digital TV-tuners,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2006, pp. 192–193. [24] I. Vassiliou, K. Vavelidis, S. Bouras, S. Kavadias, Y. Kokolakis, G. Kamoulakos, A. Kyranas, C. Kapnlstls, and N. Haralabldls, “A 0.18 ￾m CMOS dual-band direct-conversion DVB-H receiver,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2006, pp. 606–607. [25] M. Gupta, S. Lerstaveesin, D. Kang, and B.-S. Song, “A 48-to-860 MHz CMOS direct-conversion TV tuner,” in IEEE Int. Solid-State Cir￾cuits Conf. Tech. Dig., Feb. 2007, pp. 206–207. Lei Lu (S’07) was born in Bengbu, Anhui, China, in 1982. He received the B.S. degree in electronics in￾formation engineering from the Shanghai University of Electric Power (SUEP), Shanghai, China, in 2004 and is currently working toward the Ph.D. degree in microelectronics at Fudan University, Shanghai, China. Since September 2007, he has been with Shanghai Ratio Microelectronics Technology Company Ltd., Shanghai, China, where he designed wideband fractional- frequency synthesizers for DTV ap￾plications as an Intern. His current research interests include modeling and parameter extraction of on-chip inductors, quadrature and wideband VCOs, as well as wideband fractional- and all-digital frequency synthesizers.