复旦大学：微电子工程教学资源（参考论文）An 18-mW 1.175–2-GHz Frequency Synthesizer With Constant Bandwidth for DVB-T Tuners

928 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES.VOL.57.NO.4.APRIL 2009 An 18-mW 1.175-2-GHz Frequency Synthesizer With Constant Bandwidth for DVB-T Tuners Lei Lu,Student Member,IEEE,Jinghong Chen,Senior Member,IEEE, Lu Yuan,Hao Min,and Zhangwen Tang,Member;IEEE Abstract-A fully integrated 1.175-2-GHz differentially tuned-87 dBc/Hz at a 10-kHz offset [2].In addition,because of the frequency synthesizer aimed for digital video broadcasting-ter- very wide frequency range,the synthesizer loop bandwidth, restrial tuners is implemented in a 0.18-um CMOS process. which affects the phase-noise optimization and loop stability. To maintain phase-noise optimization and loop stability over the entire output frequency range,techniques of constant loop may vary quite significantly due to two reasons.Firstly,to bandwidth are proposed.The voltage-controlled oscillator gain cover such a wideband frequency range and achieve a rela- Kvco and band step fr are both maintained by simultaneously tively low voltage-controlled oscillator (VCO)gain (Kvco),a adjusting the sizes of switched capacitors and varactors.Charge switched capacitor array is usually employed in the LC VCO. pump current Icp is programmed to compensate the variation of the division ratio N.The measured results show an in-band phase However,even with a switched capacitor bank,the VCO gain noise of-97.6 dBc/Hz at a 10-kHz offset and an integrated phase variation is still huge.The phase noise is degraded as the VCO error of 0.630 from 100 Hz to 10 MHz.The measured variations of gain increases [3].Secondly,a large range of division ratio Kvco and fres are less than 12.5%and 4.5%,respectively.The N is required to obtain the wide tuning range of nearly one variations of the measured phase noise at 10-kHz and 1-MHz fre- octave.The N variation also changes the loop bandwidth,thus quency offsets are less than 1 dB.The measured 3-dB closed-loop bandwidth is 110 kHz and the variation is less than 9%.The chip impacting the phase noise and loop stability. draws 10-mA current from a 1.8-V supply while occupying a To achieve a constant loop bandwidth,several methods have 2.2-mm2 die area. been previously proposed [4],[5].In [4],natural frequency wn Index Terms-Frequency synthesizer,loop bandwidth,loop gain, is used as a definition of the loop bandwidth.To handle the large phase noise,voltage-controlled oscillator(VCO)gain,wideband. division ratio range,a sampled loop filter (LPF)network is con- structed and an inverse-linear charge pump(CP)is used to keep the natural frequency over reference frequency (wn/wref)and I.INTRODUCTION the damping factor constant.Though the natural frequency HE DIGITAL video broadcasting-terrestrial (DVB-T)and damping factor are widely used in the analysis of synthe- standard has ushered in a new era in TV entertainment. sizer loop dynamic,strictly speaking,they are applicable only Often the DVB-T tuners employ a double-conversion zero-IF to second-order loops.The inverse-linear CP also adds design (DZIF)architecture,which demands the use of a wideband complexity.Reference [5]uses open-loop crossover frequency frequency synthesizer as the first local oscillator (LO)(LO)We as the loop bandwidth and adjusts only the CP current(ICp) to cover the 48-862-MHz-wide frequency range and a frac- to compensate the Kvco and N variations.Although the open- tional-N frequency synthesizer as the second LO (LO2)to loop crossover frequency is often used to define a loop band- support several channel bandwidths(6/7/8 MHz)[1],[2]. width,it cannot accurately capture the low-pass corner charac- There are many challenges in designing a wideband fre-teristics of the closed-loop transfer function.In addition,though quency synthesizer LO1.It must achieve a wide frequency adjusting Icp alone can achieve a constant loop bandwidth,a tuning range,while providing low phase noise and low in-multiband VCO with constant and smaller gains is still desired tegrated phase error.The wideband synthesizer LO needs in order to improve the phase-noise performance. to meet a stringent phase-noise requirement over the entire In this paper,the concept of loop gain is used as the loop frequency range,which should be larger than the input range bandwidth to accurately model the low-pass characteristics of of 814 MHz.An adequate target for the overall phase noise is the closed-loop transfer function.Techniques achieving a con- stant and smaller VCO gain Kvco while obtaining a constant Manuscript received July 31,2008:revised December 19,2008.First loop bandwidth are proposed [6].Both a constant Kvco and published March 10,2009:current version published April 08.2009.This an equal band step fres are obtained in a multiband VCO.Au- work was supported in part by the National 863 Program of China under Grant 2007AA01Z282 and the National Science Funding of China under Grant tomatic frequency control (AFC)is used to ensure the opera- 60876019. tion of VCO in the linear region of the tuning range.The VCO L.Lu,L.Yuan,H.Min,and Z.Tang are with the Application Specific In- tegrated Circuit (ASIC)and System State Key Laboratory.Fudan University, with equal band steps greatly helps to simplify the AFC loop de- Shanghai 201203,China (e-mail:zwtang@fudan.edu.cn). sign.Programmable CP current is also adopted to compensate J.Chen is with Analog Devices Inc.,Somerset,NJ 08873 USA (e-mail: the variation of the division ratio N. jinghong@ieee.org). Color versions of one or more of the figures in this paper are available online The remainder of this paper is organized as follows.In at http://ieeexplore.ieee.org. Section II,design issues of the frequency synthesizer are con- Digital Object Identifier 10.1109/TMTT.2009.2014449 sidered and the loop gain is derived.The KVCo variation in a 0018-9480/s25.00©2009EEE

928 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 4, APRIL 2009 An 18-mW 1.175–2-GHz Frequency Synthesizer With Constant Bandwidth for DVB-T Tuners Lei Lu, Student Member, IEEE, Jinghong Chen, Senior Member, IEEE, Lu Yuan, Hao Min, and Zhangwen Tang, Member, IEEE Abstract—A fully integrated 1.175–2-GHz differentially tuned frequency synthesizer aimed for digital video broadcasting-ter￾restrial tuners is implemented in a 0.18- m CMOS process. To maintain phase-noise optimization and loop stability over the entire output frequency range, techniques of constant loop bandwidth are proposed. The voltage-controlled oscillator gain ￾ and band step  are both maintained by simultaneously adjusting the sizes of switched capacitors and varactors. Charge pump current  is programmed to compensate the variation of the division ratio . The measured results show an in-band phase noise of 97.6 dBc Hz at a 10-kHz offset and an integrated phase error of 0.63 from 100 Hz to 10 MHz. The measured variations of ￾ and  are less than 12.5% and 4.5%, respectively. The variations of the measured phase noise at 10-kHz and 1-MHz fre￾quency offsets are less than 1 dB. The measured 3-dB closed-loop bandwidth is 110 kHz and the variation is less than 9%. The chip draws 10-mA current from a 1.8-V supply while occupying a 2.2-mm die area. Index Terms—Frequency synthesizer, loop bandwidth, loop gain, phase noise, voltage-controlled oscillator (VCO) gain, wideband. I. INTRODUCTION T HE DIGITAL video broadcasting-terrestrial (DVB-T) standard has ushered in a new era in TV entertainment. Often the DVB-T tuners employ a double-conversion zero-IF (DZIF) architecture, which demands the use of a wideband frequency synthesizer as the first local oscillator (LO) to cover the 48–862-MHz-wide frequency range and a frac￾tional- frequency synthesizer as the second LO to support several channel bandwidths (6/7/8 MHz) [1], [2]. There are many challenges in designing a wideband fre￾quency synthesizer . It must achieve a wide frequency tuning range, while providing low phase noise and low in￾tegrated phase error. The wideband synthesizer needs to meet a stringent phase-noise requirement over the entire frequency range, which should be larger than the input range of 814 MHz. An adequate target for the overall phase noise is Manuscript received July 31, 2008; revised December 19, 2008. First published March 10, 2009; current version published April 08, 2009. This work was supported in part by the National 863 Program of China under Grant 2007AA01Z282 and the National Science Funding of China under Grant 60876019. L. Lu, L. Yuan, H. Min, and Z. Tang are with the Application Specific In￾tegrated Circuit (ASIC) and System State Key Laboratory, Fudan University, Shanghai 201203, China (e-mail: zwtang@fudan.edu.cn). J. Chen is with Analog Devices Inc., Somerset, NJ 08873 USA (e-mail: jinghong@ieee.org). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2009.2014449 87 dBc Hz at a 10-kHz offset [2]. In addition, because of the very wide frequency range, the synthesizer loop bandwidth, which affects the phase-noise optimization and loop stability, may vary quite significantly due to two reasons. Firstly, to cover such a wideband frequency range and achieve a rela￾tively low voltage-controlled oscillator (VCO) gain , a switched capacitor array is usually employed in the VCO. However, even with a switched capacitor bank, the VCO gain variation is still huge. The phase noise is degraded as the VCO gain increases [3]. Secondly, a large range of division ratio is required to obtain the wide tuning range of nearly one octave. The variation also changes the loop bandwidth, thus impacting the phase noise and loop stability. To achieve a constant loop bandwidth, several methods have been previously proposed [4], [5]. In [4], natural frequency is used as a definition of the loop bandwidth. To handle the large division ratio range, a sampled loop filter (LPF) network is con￾structed and an inverse-linear charge pump (CP) is used to keep the natural frequency over reference frequency and the damping factor constant. Though the natural frequency and damping factor are widely used in the analysis of synthe￾sizer loop dynamic, strictly speaking, they are applicable only to second-order loops. The inverse-linear CP also adds design complexity. Reference [5] uses open-loop crossover frequency as the loop bandwidth and adjusts only the CP current to compensate the and variations. Although the open￾loop crossover frequency is often used to define a loop band￾width, it cannot accurately capture the low-pass corner charac￾teristics of the closed-loop transfer function. In addition, though adjusting alone can achieve a constant loop bandwidth, a multiband VCO with constant and smaller gains is still desired in order to improve the phase-noise performance. In this paper, the concept of loop gain is used as the loop bandwidth to accurately model the low-pass characteristics of the closed-loop transfer function. Techniques achieving a con￾stant and smaller VCO gain while obtaining a constant loop bandwidth are proposed [6]. Both a constant and an equal band step are obtained in a multiband VCO. Au￾tomatic frequency control (AFC) is used to ensure the opera￾tion of VCO in the linear region of the tuning range. The VCO with equal band steps greatly helps to simplify the AFC loop de￾sign. Programmable CP current is also adopted to compensate the variation of the division ratio . The remainder of this paper is organized as follows. In Section II, design issues of the frequency synthesizer are con￾sidered and the loop gain is derived. The variation in a 0018-9480/$25.00 © 2009 IEEE

LU et al:18-mW 1.175-2-GHz FREQUENCY SYNTHESIZER 929 LPF fout=N-fre Binary weighted CP apa r array ÷N Fig.1.Block diagram of an integer-N frequency synthesizer with a typical passive LPF. (a) wideband PLL design is also investigated.Section III proposes techniques to achieve a constant Kyco and loop bandwidth. 2.2×10 Kvco_max=320MHz/V F-V curve The circuit implementation is described in Section IV.The ex- perimental results are given in Section V,and finally,Section VI concludes this study. 1,8 II.DESIGN CONSIDERATIONS 16 Kvco_max=8 Kyco min A.Loop Gain The phase-locked loop(PLL)loop bandwidth is an impor- fres min= tant design parameter for minimizing phase-noise variation and Kkv_in=40MHz/ 26MHz guaranteeing loop stability.As mentioned earlier,it is often de- 0.4 0.6 0.8 1.2 14 sired to have a constant loop bandwidth over the entire fre- Tuning Voltage (V) quency range. (b) The block diagram of an integer-N third-order type-II PLL is shown in Fig.1,which includes a phase-frequency detector Fig.2.Conventional topology.(a)Switching capacitor array and one varactor unit.(b)F-Vcurve with large variations of VCO tuning gain and band step. (PFD),a CP,a second-order passive LPF,an LC VCO,and a di- vider.Often the natural frequency wn or the open-loop crossover frequency wc is used as the loop bandwidth;however,the former For a typical third-order PLL,the transfer function of the LPF is not applicable in third or higher order loops and strongly de- is obtained as pends on the damping factor C,while the latter cannot capture 1 1 the low-pass corner characteristics of the closed-loop transfer (3) function.In this paper,the loop gain K is used to model the FLPF()=RIC (1+RC]s)RCCas+C+C low-pass corner of the closed-loop transfer function [7].[8].where K1 is equal to RiC and Fhf(0)is equal to 1/(C+ The open-loop transfer function of a PLL with a general LPF C2).Therefore,the loop gain K of the third-order PLL can be FLPF(s)is expressed as rewritten as G(s)= ICPKVCO FLPF(s)= K=ICPKvcoR b 2TN b+1 (4) 2INs IcpKvcO F+i(s)Fit(s) 2nNs ICPKvco where b is the ratio of Cl over C2.It can be observed that to 2nNs K1+ K2+…Ff() achieve a constant loop gain without changing the pole and zero positions is to maintain a constant VCO gain KVco and to make ICpKvcoK1Fhf(0) K2 Fir(s) 1+ (1) the CP current ICp match N. 2nNs K1s 十· Fir(O B.VCO Gain where ICp is the sink or source current of the CP.The Fpi(s) Frequency synthesizers for RF receivers usually employ an represents the proportional and integral components of the LPF, LC-based VCO due to its superior phase-noise performance. and Fif(s)represents the high-frequency components of the For the DVB-T frequency synthesizer,the targeted 814-MHz LPF.Note that Ff(0)is a finite and nonzero number.Thus. frequency range requires a VCO gain of more than 500 MHz/V the loop gain K is given by [7] assuming a 1.6-V tuning range for the CP output voltage.Such a high Kvco may significantly degrade the phase-noise per- K=IcpKvcoKi Ft(0) formance.To cover a wideband frequency range with a smaller rad/s (2) 2nN KvCo,a switched capacitor array is usually adopted,as shown in Fig.2(a).A fixed varactor Cu is tuned by the analog control Note that K has a unit of radians/second. voltage Vetri to achieve a continuous VCO frequency tuning

LU et al.: 18-mW 1.175–2-GHz FREQUENCY SYNTHESIZER 929 Fig. 1. Block diagram of an integer-￾ frequency synthesizer with a typical passive LPF. wideband PLL design is also investigated. Section III proposes techniques to achieve a constant and loop bandwidth. The circuit implementation is described in Section IV. The ex￾perimental results are given in Section V, and finally, Section VI concludes this study. II. DESIGN CONSIDERATIONS A. Loop Gain The phase-locked loop (PLL) loop bandwidth is an impor￾tant design parameter for minimizing phase-noise variation and guaranteeing loop stability. As mentioned earlier, it is often de￾sired to have a constant loop bandwidth over the entire fre￾quency range. The block diagram of an integer- third-order type-II PLL is shown in Fig. 1, which includes a phase-frequency detector (PFD), a CP, a second-order passive LPF, an VCO, and a di￾vider. Often the natural frequency or the open-loop crossover frequency is used as the loop bandwidth; however, the former is not applicable in third or higher order loops and strongly de￾pends on the damping factor , while the latter cannot capture the low-pass corner characteristics of the closed-loop transfer function. In this paper, the loop gain is used to model the low-pass corner of the closed-loop transfer function [7], [8]. The open-loop transfer function of a PLL with a general LPF is expressed as (1) where is the sink or source current of the CP. The represents the proportional and integral components of the LPF, and represents the high-frequency components of the LPF. Note that is a finite and nonzero number. Thus, the loop gain is given by [7] rad/s (2) Note that has a unit of radians/second. Fig. 2. Conventional topology. (a) Switching capacitor array and one varactor unit. (b) – curve with large variations of VCO tuning gain and band step. For a typical third-order PLL, the transfer function of the LPF is obtained as (3) where is equal to and is equal to . Therefore, the loop gain of the third-order PLL can be rewritten as (4) where is the ratio of over . It can be observed that to achieve a constant loop gain without changing the pole and zero positions is to maintain a constant VCO gain and to make the CP current match . B. VCO Gain Frequency synthesizers for RF receivers usually employ an -based VCO due to its superior phase-noise performance. For the DVB-T frequency synthesizer, the targeted 814-MHz frequency range requires a VCO gain of more than 500 MHz/V assuming a 1.6-V tuning range for the CP output voltage. Such a high may significantly degrade the phase-noise per￾formance. To cover a wideband frequency range with a smaller , a switched capacitor array is usually adopted, as shown in Fig. 2(a). A fixed varactor is tuned by the analog control voltage to achieve a continuous VCO frequency tuning,

930 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES.VOL.57.NO.4.APRIL 2009 while a binary weighted capacitor array is controlled digitally Size changeable to discretely change the frequency band. capacitor array Although the switched capacitor array can extend the VCO Cr tuning range while maintaining a smaller KvCo,it has two dis- en a1Cf advantages.Firstly,equal capacitor is switched in or out of the capacitor bank whenever a lower or higher adjacent tuning band a1sC is required.Due to the nonlinear characteristic of frequency versus capacitance,the Kvco will vary by a factor of 8 when the output frequency doubles by reducing the tank capacitance to a quarter [9].Simulated tuning curves of a wideband VCO from 1 to 2 GHz are shown in Fig.2(b),where a tank induc- tance of 4 nH is used.The highest and lowest Kvco is 320 and 40 MHz/V,respectively.Such a large VCO gain variation sig- nificantly changes the loop bandwidth.As a result,the phase noise is deteriorated and the PLL loop becomes unstable.Sec- ondly,the highest and lowest band step fres is 174 and 26 MHz, Size changeable varactor array respectively.Such a large band-step difference with a ratio of (a) 6.7 greatly increases the complexity of the AFC loop design. 2.2*109 -F-V curve fres=67MHz Kvco=100MHz/V III.DESIGN TECHNIQUES A.Wideband VCO With Constant VCO Gain and Band Step 1.8 The Kvco variation is a severe problem in designing wide- band VCOs.Several techniques have been previously reported to reduce Kvco fluctuation [10].[11].In [10],an additional anba serial LC-tank with a variable inductor configuration is used to offset the VCO gain variation;however,such a method requires extra inductors and consumes more die area.A switched var- actor array in combination with a multibias scheme is used to compensate the Kvco variation in [11].However,this method requires extra complicated biasing networks.In addition,both 0.4 0.6 0.8 1 1.2 1.4 Tuning Voltage (V) techniques cannot solve the variation problem of the band step fres.To minimize variations of both the VCO gain Kyco and (b) the band step fres,a proposed architecture is shown in Fig.3(a). Fig.3.Proposed LC-tank topology.(a)DCCA with a DCVA.(b)F-V curve The idea behind the proposed architecture is to make both with constant VCO tuning gain and band step. the sizes of switched capacitors and the varactors changeable. Instead of using a fixed analog varactor and a binary-weighted across the tank at the center frequency of the nth sub-band can capacitor array,a number of capacitor and varactor units with be expressed as follows: different sizes are adopted.At lower frequency bands,not only more switched capacitor units are connected into the LC-tank, Cp+Cf+(3+…+35)Cw,min+C,0.9, but also more varactor units are connected to the analog control m=1 voltage;the remaining varactor units are connected to a fixed Cp+(1+1+…+anm-1)Cf+(3n+…+35) voltage VB to have a minimum fixed capacitance and the re- Cu,mim+(1++…+3n-1)C,(0.9y maining switched capacitor units are disconnected.On the other Ctot,n n=2,3,,15 hand,at higher frequency bands,less switched capacitor units, Cp+(1+a1+…+15) as well as less varactor units are switched into the LC-tank. .Cf+(1+31+…+315)Cu,0.9): Doing so allows a small and a constant Kvco,as well as a m=16. constant fres to be achieved over the entire frequency range (5) without adding extra design complexity,die area,or power where Cp is the parasitic capacitance,Cf is the capacitance of consumption. the basic switched capacitor unit.Cv,min is the minimum capac- In the synthesizer,a digitally controlled capacitor array itance of the varactor C,and C,(0)is the capacitance of C (DCCA)divides the whole tuning range into 16 sub-bands to at the center of the control voltage(VDD=1.8 V).Note that keep a relatively low analog tuning gain,while an extra digitally n=1 is the highest frequency band.The oscillation frequency controlled varactor array (DCVA)is inserted to equalize the fvco,n at the center of nth sub-band is expressed as tuning sensitivity.Assuming ai(=1,2,...,15)being the capacitor ratio of DCCA units and Bi(=1,2,...,15)being 1 (6) the varactor ratio of DCVA units,the total capacitance Ctot,n fco,n=2m√Ctot,n n=1,2,.…,16

930 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 4, APRIL 2009 while a binary weighted capacitor array is controlled digitally to discretely change the frequency band. Although the switched capacitor array can extend the VCO tuning range while maintaining a smaller , it has two dis￾advantages. Firstly, equal capacitor is switched in or out of the capacitor bank whenever a lower or higher adjacent tuning band is required. Due to the nonlinear characteristic of frequency versus capacitance, the will vary by a factor of 8 when the output frequency doubles by reducing the tank capacitance to a quarter [9]. Simulated tuning curves of a wideband VCO from 1 to 2 GHz are shown in Fig. 2(b), where a tank induc￾tance of 4 nH is used. The highest and lowest is 320 and 40 MHz/V, respectively. Such a large VCO gain variation sig￾nificantly changes the loop bandwidth. As a result, the phase noise is deteriorated and the PLL loop becomes unstable. Sec￾ondly, the highest and lowest band step is 174 and 26 MHz, respectively. Such a large band-step difference with a ratio of 6.7 greatly increases the complexity of the AFC loop design. III. DESIGN TECHNIQUES A. Wideband VCO With Constant VCO Gain and Band Step The variation is a severe problem in designing wide￾band VCOs. Several techniques have been previously reported to reduce fluctuation [10], [11]. In [10], an additional serial -tank with a variable inductor configuration is used to offset the VCO gain variation; however, such a method requires extra inductors and consumes more die area. A switched var￾actor array in combination with a multibias scheme is used to compensate the variation in [11]. However, this method requires extra complicated biasing networks. In addition, both techniques cannot solve the variation problem of the band step . To minimize variations of both the VCO gain and the band step , a proposed architecture is shown in Fig. 3(a). The idea behind the proposed architecture is to make both the sizes of switched capacitors and the varactors changeable. Instead of using a fixed analog varactor and a binary-weighted capacitor array, a number of capacitor and varactor units with different sizes are adopted. At lower frequency bands, not only more switched capacitor units are connected into the -tank, but also more varactor units are connected to the analog control voltage; the remaining varactor units are connected to a fixed voltage to have a minimum fixed capacitance and the re￾maining switched capacitor units are disconnected. On the other hand, at higher frequency bands, less switched capacitor units, as well as less varactor units are switched into the -tank. Doing so allows a small and a constant , as well as a constant to be achieved over the entire frequency range without adding extra design complexity, die area, or power consumption. In the synthesizer, a digitally controlled capacitor array (DCCA) divides the whole tuning range into 16 sub-bands to keep a relatively low analog tuning gain, while an extra digitally controlled varactor array (DCVA) is inserted to equalize the tuning sensitivity. Assuming being the capacitor ratio of DCCA units and being the varactor ratio of DCVA units, the total capacitance Fig. 3. Proposed ￾-tank topology. (a) DCCA with a DCVA. (b) – curve with constant VCO tuning gain and band step. across the tank at the center frequency of the th sub-band can be expressed as follows: (5) where is the parasitic capacitance, is the capacitance of the basic switched capacitor unit, is the minimum capac￾itance of the varactor , and is the capacitance of at the center of the control voltage V . Note that is the highest frequency band. The oscillation frequency at the center of th sub-band is expressed as (6)

LU et al:18-mW 1.175-2-GHz FREQUENCY SYNTHESIZER 931 where L is half the inductance value of the differential tank in- TABLE I ductor.Furthermore,the VCO gain Kvco.n at the center of the VALUES OF COEFFICIENTS L:AND C nth sub-band,which is derived from the partial derivative of Qi Q i control voltage,can be calculated as 西 1.47 0.11 2.56 0.23 11 5.03 0.56 Kyco,n 2 1.63 0.12 2.90 0.27 12 5.88 0.69 vco.n 1.82 0.14 3.29 0.32 13 6.93 0.87 2.03 0.38 8.24 aVerl 0.16 3.77 1✉ 1.10 2.27 0.19 10 4.34 0.46 15 9.91 1.41 1 aC. m=1 4红√LCgt,n OVetrl V=0.9 1+3+…3m-1. OC 4红V/LCoun OVetrl IVetH=0.9 n=2,3,.,16 (7) where oCu/ovatri(Vetrl =0.9V)is the slope of the C-V curve PFD of the varactor C,at the center of control voltage.Note that OC/Ovtr is negative,hence,Kvco.n is a positive number. For a given constant Kvco and fres,as well as the entire fre- VCO quency range,the procedure to calculate oi and is as follows. Programmable Divider Firstly,the highest frequency band fH,the lowest frequency sda+ ◆N=94-160 band fr,the number of frequency bands n,and the inductance value L are selected,then the center frequency KVco.n at each reset- frequency band can be determined according to the frequency Fig.4.Block-level diagram of a wideband 1.175-2-GHz frequency synthesizer range and the number of bands.Substituting Kvco,n into with differential tuning. (6),Ctot,n can be obtained.Secondly,with the predetermined Kvcon,Ctot,n is substituted into (7)to obtain the coefficients Bi.Thirdly,the inherent capacitance of the cross-coupled MOS senses the VCO output center frequency of each band and com- transistors and the layout parasitic capacitance are estimated pares it with the target value,which is determined by the division to determine the value of Cp.In addition,a varactor unit is ratio N.The AFC loop selects the band whose center frequency simulated to obtain C,min and C,(0.).Finally,by substituting is the closest to the target value [12].[13].As long as the over- Cto,n.Cp,Cf,Cv,min,and Cu,(0.9).as well as the coefficient lapping ratio between any two adjacent bands exceeds 50%,all into(⑤)，the coefficients a;can be obtained. output frequency points can fall near the middle of the tuning Therefore,by choosing oi and Bi properly,the Kvco and curve thus having linear tuning gains.By doing so,the VCO the band step fres can be arbitrary and constant.Nevertheless,it gain variation is further suppressed. should be noted that if MOS transistors are used as the switched C.CP capacitors or the varactors,the minimum channel length of the The frequency synthesizer varies its output frequency by technology may limit the minimum value of the capacitor and varactor sizes and this restricts the Kvco and the band step fres changing the division ratio N.As can be seen from(4),when that can be achieved.An example of the coefficients ai and B is N changes,the loop gain is affected.To compensate the N summarized in Table I when Cp is 1.4 pF.Cf is 73 fF.Cv,(0.9)is variation,the CP current Icp is programmed to match the 40 fF,and C,min is 10 fF.These coefficients should be rounded division ratio N.A number of current mirrors are paralleled with a reference current source and sink to calibrate the total to the nearest values that the technology permits.It should also output charging and discharging current.By adjusting Icp,the be noted that since these coefficients are only ratios,they are insensitive to the process,voltage,and temperature(PVT)vari- term ICr/N can be made unchanged.With a constant IcP/N ations.The simulated tuning curves of the proposed architecture and Kvco,a constant loop gain K can be achieved across the are shown in Fig.3(b).Across the entire frequency range from entire frequency tuning range. 1 to 2 GHz,fres is 67 MHz uniformly and Kyco is 100 MHz/V IV.CIRCUIT IMPLEMENTATION for every switching band. A.System Architecture B.AFC A block-level diagram of the wideband 1.175-2-GHz fre- Due to the nonlinearity of the C-V curve of the varactor,the quency synthesizer is shown in Fig.4.The synthesizer is fully KyCo of each frequency band can only be made equal in the integrated including a PFD,a rail-to-rail differential CP,a dif- middle of the tuning curve.For each tuning curve,the slope ferential passive LPF,a wideband LC VCO,a programmable around the middle is linear and maximal.The AFC algorithm divider,a low drop-out(LDO)regulator,an AFC block,and an

LU et al.: 18-mW 1.175–2-GHz FREQUENCY SYNTHESIZER 931 where is half the inductance value of the differential tank in￾ductor. Furthermore, the VCO gain at the center of the th sub-band, which is derived from the partial derivative of control voltage, can be calculated as (7) where V is the slope of the – curve of the varactor at the center of control voltage. Note that is negative, hence, is a positive number. For a given constant and , as well as the entire fre￾quency range, the procedure to calculate and is as follows. Firstly, the highest frequency band , the lowest frequency band , the number of frequency bands , and the inductance value are selected, then the center frequency at each frequency band can be determined according to the frequency range and the number of bands. Substituting into (6), can be obtained. Secondly, with the predetermined , is substituted into (7) to obtain the coefficients . Thirdly, the inherent capacitance of the cross-coupled MOS transistors and the layout parasitic capacitance are estimated to determine the value of . In addition, a varactor unit is simulated to obtain and . Finally, by substituting , and , as well as the coefficient into (5), the coefficients can be obtained. Therefore, by choosing and properly, the and the band step can be arbitrary and constant. Nevertheless, it should be noted that if MOS transistors are used as the switched capacitors or the varactors, the minimum channel length of the technology may limit the minimum value of the capacitor and varactor sizes and this restricts the and the band step that can be achieved. An example of the coefficients and is summarized in Table I when is 1.4 pF, is 73 fF, is 40 fF, and is 10 fF. These coefficients should be rounded to the nearest values that the technology permits. It should also be noted that since these coefficients are only ratios, they are insensitive to the process, voltage, and temperature (PVT) vari￾ations. The simulated tuning curves of the proposed architecture are shown in Fig. 3(b). Across the entire frequency range from 1 to 2 GHz, is 67 MHz uniformly and is 100 MHz/V for every switching band. B. AFC Due to the nonlinearity of the – curve of the varactor, the of each frequency band can only be made equal in the middle of the tuning curve. For each tuning curve, the slope around the middle is linear and maximal. The AFC algorithm TABLE I VALUES OF COEFFICIENTS ￾ AND Fig. 4. Block-level diagram of a wideband 1.175–2-GHz frequency synthesizer with differential tuning. senses the VCO output center frequency of each band and com￾pares it with the target value, which is determined by the division ratio . The AFC loop selects the band whose center frequency is the closest to the target value [12], [13]. As long as the over￾lapping ratio between any two adjacent bands exceeds 50%, all output frequency points can fall near the middle of the tuning curve thus having linear tuning gains. By doing so, the VCO gain variation is further suppressed. C. CP The frequency synthesizer varies its output frequency by changing the division ratio . As can be seen from (4), when changes, the loop gain is affected. To compensate the variation, the CP current is programmed to match the division ratio . A number of current mirrors are paralleled with a reference current source and sink to calibrate the total output charging and discharging current. By adjusting , the term can be made unchanged. With a constant and , a constant loop gain can be achieved across the entire frequency tuning range. IV. CIRCUIT IMPLEMENTATION A. System Architecture A block-level diagram of the wideband 1.175–2-GHz fre￾quency synthesizer is shown in Fig. 4. The synthesizer is fully integrated including a PFD, a rail-to-rail differential CP, a dif￾ferential passive LPF, a wideband VCO, a programmable divider, a low drop-out (LDO) regulator, an AFC block, and an

932 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES.VOL.57.NO.4.APRIL 2009 1.5V,from LDO B15C -0000 an鸠 区en b[3:0]-Encode 015 h 感4丽 Fig.5.Circuit diagram of the proposed wideband LC VCO. 12C controller.In order to suppress common-mode noise from total of 16 sub-bands are achieved.An encoder is used to trans- control lines,power supply,and the substrate,a differentially form binary codes into thermometer codes to control the dig- tuned LC VCO was implemented [14].Accordingly,the CP ital bits.A basic varactor unit of only I-MOS is used at the of the synthesizer was also implemented as a fully differential highest frequency band.The DCCA using I-NMOS transistors structure.When switch S is closed,the differential control volt- performs coarse tuning.When eni(=1,...,15)is high,the ages Vtrlp and Vetrin are connected to a reference voltage Vief, NMOS transistor operates in the strong inversion region and and the AFC loop counts the clock divided by eight from the maximum capacitance is realized.To meet the wideband fre- VCO output and performs the coarse tuning.After AFC oper- quency resonating characteristics,switched capacitor arrays are ation,switch S2 is closed and S is open,and the differential also added at the tail nodes to compensate the tail capacitance control voltages are connected to the CP output to carry out the and allow the tail nodes to oscillate at twice the resonant fre- analog fine tuning.Internal digital registers are configured by an quency over the entire tuning range. T2C controller. The detail realization of DCVA is also depicted.When en is high,Ma and Ms are off,M2-M3 and M6-M7 are on to B.Wideband VCO conduct the control voltage Vetrlp and Vetrin to the drain-source of M and M5,then Mi and M5 are analog controlled and act as The schematic of an LC VCO is illustrated in Fig.5.To varactors.On the other hand,when en is low,the drain-source reduce supply noise coupling,the VCO core is biased by a of M is connected to ground and the drain-source of M is 1.5-V power supply from an on-chip LDO.Two complementary connected to Vpp,thus the capacitances of the varactor Mi and cross-coupled NMOS and PMOS transistors are adopted to form Ms are fixed and set at the minimal value. the negative transconductance.The LC tank uses a differential The quality factor Q of the resonator tank is mainly limited by inductor to achieve a higher O factor compared to single-ended the tank inductor.The differential inductor in the tank is mod- inductors.The tail current source has been removed to improve eled using the Agilent full-wave EM simulator Momentum,and the phase noise in the 1/f3 region.Removing the tail current the inductor Q factor is between 6-10 from 1 to 2 GHz.All the source also maximizes the oscillation amplitude to nearly full capacitors and varactors are made using inversion-mode MOS swing.A tail LC-tank is used to increase the impedance of the transistors,and their factors are optimized between 20-30 tail nodes at the second harmonic,thus eliminating the thermal across the entire tuning range so as to obtain larger values than noise at twice the oscillation frequency.It also enhances the av-that of the inductor. erage loaded Q factor of the resonant LC-tank over one period improving the VCO phase-noise performance [15]. C.Differential CP Inversion-mode MOS(I-MOS)varactors are used to perform A differential CP is used to achieve a better immunity to analog fine tuning [16],[17].To cover the wide frequency range common-mode,power supply,and substrate noises.The con- of more than 814 MHz,four digital control bits are used and a ventional differential CP topology,despite the use of common-

932 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 4, APRIL 2009 Fig. 5. Circuit diagram of the proposed wideband ￾ VCO. controller. In order to suppress common-mode noise from control lines, power supply, and the substrate, a differentially tuned VCO was implemented [14]. Accordingly, the CP of the synthesizer was also implemented as a fully differential structure. When switch is closed, the differential control volt￾ages and are connected to a reference voltage , and the AFC loop counts the clock divided by eight from the VCO output and performs the coarse tuning. After AFC oper￾ation, switch is closed and is open, and the differential control voltages are connected to the CP output to carry out the analog fine tuning. Internal digital registers are configured by an controller. B. Wideband VCO The schematic of an VCO is illustrated in Fig. 5. To reduce supply noise coupling, the VCO core is biased by a 1.5-V power supply from an on-chip LDO. Two complementary cross-coupled NMOS and PMOS transistors are adopted to form the negative transconductance. The tank uses a differential inductor to achieve a higher factor compared to single-ended inductors. The tail current source has been removed to improve the phase noise in the region. Removing the tail current source also maximizes the oscillation amplitude to nearly full swing. A tail -tank is used to increase the impedance of the tail nodes at the second harmonic, thus eliminating the thermal noise at twice the oscillation frequency. It also enhances the av￾erage loaded factor of the resonant -tank over one period improving the VCO phase-noise performance [15]. Inversion-mode MOS ( -MOS) varactors are used to perform analog fine tuning [16], [17]. To cover the wide frequency range of more than 814 MHz, four digital control bits are used and a total of 16 sub-bands are achieved. An encoder is used to trans￾form binary codes into thermometer codes to control the dig￾ital bits. A basic varactor unit of only -MOS is used at the highest frequency band. The DCCA using -NMOS transistors performs coarse tuning. When is high, the NMOS transistor operates in the strong inversion region and maximum capacitance is realized. To meet the wideband fre￾quency resonating characteristics, switched capacitor arrays are also added at the tail nodes to compensate the tail capacitance and allow the tail nodes to oscillate at twice the resonant fre￾quency over the entire tuning range. The detail realization of DCVA is also depicted. When is high, and are off, – and – are on to conduct the control voltage and to the drain–source of and , then and are analog controlled and act as varactors. On the other hand, when is low, the drain–source of is connected to ground and the drain–source of is connected to , thus the capacitances of the varactor and are fixed and set at the minimal value. The quality factor of the resonator tank is mainly limited by the tank inductor. The differential inductor in the tank is mod￾eled using the Agilent full-wave EM simulator Momentum, and the inductor factor is between 6–10 from 1 to 2 GHz. All the capacitors and varactors are made using inversion-mode MOS transistors, and their factors are optimized between 20–30 across the entire tuning range so as to obtain larger values than that of the inductor. C. Differential CP A differential CP is used to achieve a better immunity to common-mode, power supply, and substrate noises. The con￾ventional differential CP topology, despite the use of common-

LU et al:18-mW 1.175-2-GHz FREQUENCY SYNTHESIZER 933 VDD T9 h Fig.6.Circuit diagram of the differential CP. mode feedback(CMFB)circuitry,can still have mismatch be- tween the differential output currents due to the channel-length modulation effect [18].In this paper,a differential CP with ex- cellent single-ended current matching is adopted,as shown in up dn Fig.6.It uses a replica bias circuit to provide good matching be- tween the up and down current sources [19].Owing to the local dnb/ upb feedback opamp A1,the CP can have near rail-to-rail operation. Capacitors Cp and Cn are large bypass capacitors,which act as voltage sources with low impedance during the onset of the up and down pulses and ensure fast turn-on of the current sources. C2/2 During the charging period,current is sourced out to the LPF W connected to Vetrlp and sinks from the LPF on Vetrin,causing -M C1/2 R1 the differential voltage to increase.Similarly discharging cur- rent will cause the differential output voltage to decrease. Fig.7.Circuit diagram of the differential-mode LPF Programmable current banks are added to compensate the N variation from 80 to 160.The CP current is programmed from CML CMOS 62.5 to 125 uA with a step of 1.95 uA and a 5-bit digital con- F02 Fos trol.A CMFB loop is used to ensure the stability of the de- 2/3 231 23 23 23 23 213 ell sired common-mode voltage of Vetrlp and Vetrl.Two unit-gain cell mod:cell modacell buffers A2 are inserted to isolate the control voltages and the common-mode sensing point.Rail-to-rail opamps are used to Pa ensure a near VDD swing for Vetrlp and Vetrin. D.On-Chip LPF Fig.8.Circuit diagram of the programmable cascaded divider. The large area of the LPF capacitor makes it difficult to be integrated on chip.Moreover,two LPFs with the same loop an impedance transformation method is employed.The LPF bandwidth are required for differential tuning,and this may re- schematic is shown in Fig.7,which illustrates the principle.The quire twice the area.Although the capacitance multiplier tech-capacitor Cl that is the largest capacitor generates the first pole nique can be used,it suffers from the degradation of phase-noise for the type-II synthesizer.Ci and R are used to generate a zero performance [20].To ensure on-chip integration of the LPF, for loop stability,and C2 is used to generate the second pole and

LU et al.: 18-mW 1.175–2-GHz FREQUENCY SYNTHESIZER 933 Fig. 6. Circuit diagram of the differential CP. mode feedback (CMFB) circuitry, can still have mismatch be￾tween the differential output currents due to the channel-length modulation effect [18]. In this paper, a differential CP with ex￾cellent single-ended current matching is adopted, as shown in Fig. 6. It uses a replica bias circuit to provide good matching be￾tween the up and down current sources [19]. Owing to the local feedback opamp , the CP can have near rail-to-rail operation. Capacitors and are large bypass capacitors, which act as voltage sources with low impedance during the onset of the up and down pulses and ensure fast turn-on of the current sources. During the charging period, current is sourced out to the LPF connected to and sinks from the LPF on , causing the differential voltage to increase. Similarly discharging cur￾rent will cause the differential output voltage to decrease. Programmable current banks are added to compensate the variation from 80 to 160. The CP current is programmed from 62.5 to 125 A with a step of 1.95 A and a 5-bit digital con￾trol. A CMFB loop is used to ensure the stability of the de￾sired common-mode voltage of and . Two unit-gain buffers are inserted to isolate the control voltages and the common-mode sensing point. Rail-to-rail opamps are used to ensure a near swing for and . D. On-Chip LPF The large area of the LPF capacitor makes it difficult to be integrated on chip. Moreover, two LPFs with the same loop bandwidth are required for differential tuning, and this may re￾quire twice the area. Although the capacitance multiplier tech￾nique can be used, it suffers from the degradation of phase-noise performance [20]. To ensure on-chip integration of the LPF, Fig. 7. Circuit diagram of the differential-mode LPF. Fig. 8. Circuit diagram of the programmable cascaded divider. an impedance transformation method is employed. The LPF schematic is shown in Fig. 7, which illustrates the principle. The capacitor that is the largest capacitor generates the first pole for the type-II synthesizer. and are used to generate a zero for loop stability, and is used to generate the second pole and

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES.VOL.57.NO.4.APRIL 2009 -60 70 80 Simulation -90 Measured -100 -110 VCO CP -120 Divider -130 Technology 0.18-um CMOS Reference 12.5 MHz Frequency -140 Power Supply 1.8V Output 1.175-2GHz Reference Frequency (52%) .150 Phase Nolse -97.6@10kHz Loop Bandwidth 90 kHz 103 o 10￥ 105 106 101 (dBc/Hz) -124.201MHz Chip Area 2.6mm Frequency Offset(Hz) RMS Phase Eror 0.63 Power Fig.12.Comparisons of simulation and measured phase noise at the oscillation 100H2-10MHz Consumption 18 mW 20 frequency of 1.6 GHz. Fig.9.Die micrograph and performance summary. -90 150 -95 140 2.1 band +Closed-loop output freq. -100 130 2 89 @10kHz offset -105 120 1.9 -110 110 1.8 -115 100 1.7 8i9 -1.6GHz二 1000 120 @1MHz offset 90 1.6 1001 1010 .125★0 80 1.5 1011 1100 -130 1101 1.2 1.41.61.8 d 14 Output Frequency (Hz) 1110 ×10 1.3 1111 Fig.13. Measured phase noise and 3-dB closed-loop bandwidth. 1.21 AFC operation region 0.8-0.6-0.4-020 0.20.4 0.60.8 1 1.9 Differential Control Voltage (V) Fig.10.Measured tuning curves of 16 sub-bands. 1.8 a Mkr1 -12.50 MHz Ref 8 dBm Atten 10 dB -55.437dB Samp -3 bit 1.6 2nd bit 10 dB/ ,1数b 1.5 1.4 AFC PLL Marker△ -12.500000MHz stat0102030 405060708090100 LgAv -55.437dB Time(μs) 100 Fig.14.Measured total locking time FS AA ered as virtually grounds.The two capacitors C and C2 can Swp thus be connected in series directly.As a result,only a quarter Center 1.600 00 GHz Span 30 MHz of the area is needed as compared to the conventional imple- Res BW 270 kHz VBH 270 kHz meep1.6m3(691pts】 mentation.The LPF parameters are as follows:Cl is 971 pF, Fig.11.Measured PSD of the oscillation amplitude at 1.6 GHz. C2 is 97.1 pF,and Ri is 5.66 k2. E.Other Blocks smooth ripples of the control voltage.Since the VCO is driven The schematic of the programmable divider is shown in by differential control voltages,nodes A and B can be consid- Fig.8.It uses a cascade of seven 2/3 divider cells [21].A

934 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 4, APRIL 2009 Fig. 9. Die micrograph and performance summary. Fig. 10. Measured tuning curves of 16 sub-bands. Fig. 11. Measured PSD of the oscillation amplitude at 1.6 GHz. smooth ripples of the control voltage. Since the VCO is driven by differential control voltages, nodes A and B can be consid￾Fig. 12. Comparisons of simulation and measured phase noise at the oscillation frequency of 1.6 GHz. Fig. 13. Measured phase noise and 3-dB closed-loop bandwidth. Fig. 14. Measured total locking time. ered as virtually grounds. The two capacitors and can thus be connected in series directly. As a result, only a quarter of the area is needed as compared to the conventional imple￾mentation. The LPF parameters are as follows: is 971 pF, is 97.1 pF, and is 5.66 k . E. Other Blocks The schematic of the programmable divider is shown in Fig. 8. It uses a cascade of seven 2/3 divider cells [21]. A

LU et al:18-mW 1.175-2-GHz FREQUENCY SYNTHESIZER 935 TABLE II PERFORMANCE SUMMARY AND COMPARISON WITH PRIOR ARTS Ref. [221 23] [24 25] This Work Application DVB-S ISDB-T DVB-H DVB-T DVB-T Integration Fully-Integrated Fully-Integrated Fully-Integrated Off-Chip LPF Fully-Integrated Loop Bandwidtha 1 MHz 100 kHz 60 kHz 100 kHzb 110 kHz Output Frequency (Normalized Tuning 2.24-4.48GH2 1.5-3.78GH 1.2-1.8GHz 1.1-2.2GHz 1.175-2GHz Range) (66.7%) (43.2%) (20%) (22.2%) (52%) VCo Core Ring Two LCs Two LCs Three LC's Single LC Tuning Type Single-Ended Single-Ended Single-Ended Single-Ended Differential Phase Noise -98@100kHz -88@10kHz -94@10kHz -90@10kHz -97.6@10kH2 (dBc/Hz) -100@1MHz 118@1MHz -127@1MHz -124.2@1MHz RMS Phase Error 0.8° N.A. 0.5° 1.5o 0.630 Power Consumption 132mW 20 mW N.A. N.A. 18 mW Die Area 0.3mm2 1.9mm2 2.45mm2 1.2mm2 2.2mm2 (Exclude PADs) (Exclude I2C) Technology (CMOS) 0.13-μm,3.3V 0.11-um,1.2V 0.18-μm,1.8V 0.18-um,1.8V 0.18-um1.8V a 3-dB Closed-Loop. b Does not indicate which kind of bandwidth is used The whole tuning range divided by the number of LC-VCOs. few logic gates are added to extend the division range so the and simulated curves agree very well from 100 Hz to 10 MHz. resulting division range is from 32 to 255.To save the power The simulated phase-noise contributions of all the blocks are consumption,only the first two stages use the current mode also depicted.At below 1-kHz offset,the noise from reference logic (CML),and the following stages adopt CMOS circuits. clock dominates;the CP contributes most at the in-band fre- The AFC loop uses a binary-search algorithm.Each unit com- quency offset;the LPF contributes most from 30 to 500 kHz;and parison time of AFC is 4 us and a total of 16 us is used for per-the VCO dominates at the far out-of-band frequency offset be- forming the AFC operation yond 500 kHz.Phase-noise plots at frequency offsets of 10 kHz and 1 MHz with the oscillation frequency ranging from 1.2 to V.EXPERIMENTAL RESULTS 2 GHz are shown in Fig.13.The phase-noise curves have a flat The wideband frequency synthesizer was implemented in a characteristic across the entire frequency range.The variation is 0.18-um CMOS process.The die micrograph is shown in Fig.9 less than 1 dB.It is also shown that the closed loop has an av- and a summary of the measured chip performance is also in-erage 3-dB bandwidth of 110 kHz and the bandwidth variation cluded.The die area is 2.2 mm2,excluding PADs.electronic is less than 9%. discharge (ESD)protection circuits,and I2C controller.The The measured locking process is shown in Fig.14.The AFC power supply is 1.8 V. operation consumes 16 us,with 4 us for each unit comparison The measured closed-loop output frequency is shown in time.The remaining time for PLL operation is 84 us,and the Fig.10,which includes a total of 71 points with a division ratio total locking time is less than 100 us. from 93 to 163.The tuning gain varies from 70 to 90 MHz/V. Table II presents a performance comparison with recently re- The tuning gain variation is less than 12.5%across the entire ported frequency synthesizers designed for DVB applications. wideband frequency range of 825 MHz.One possible reason for This work used a single LC VCO,while the others used mul- this small tuning gain variation is that the oscillation amplitude tiple(either two or three)LC VCOs.For the synthesizers using is not constant across the entire frequency range,as a result,the LC VCOs,this work achieved the highest normalized tuning calculated average capacitance over an oscillation period varies range of 52%.The normalized tuning range is defined as the slightly.The measured band step fres is from 50 to 60 MHz.whole tuning range divided by the number of LC VCOs used. The variation of the band step is less than 4.5%.Due to the Even with a single LC VCO,the wideband frequency synthe- adoption of the AFC loop,the differential control voltages sizer described in this paper still achieved an excellent phase- fall between +0.4 V over the entire frequency range,and this noise performance.It consumed the smallest power with a com- ensures the operation of the VCO in the linear tuning region. parable die area(compared with the synthesizers having a fully Fig.11 shows the oscillation amplitude power spectral den-integrated LPF).In addition.the synthesizer adopted differential sity (PSD)at 1.6 GHz.The reference spur at a 12.5-MHz fre-tuning modes to suppress the common-mode noise from control quency offset is below-55 dBc/Hz.The measured phase noise lines,power supply,and the substrate.A unique feature of the at 1.6 GHz is plotted in Fig.12 and is compared with the simula-synthesizer is that it achieved a constant 3-dB closed-loop band- tion result.The spot phase noise is-97.6 dBc/Hz at a 10-kHz width.The VCO is designed to achieve a constant band step fres. offset and-124.2 dBc/Hz at a 1-MHz offset.The integrated as well as a small and constant VCO gain Kvco.The CP cur- phase error from 100 Hz to 10 MHz is 0.63s.The measured rent is adjusted to match the division ratio N

LU et al.: 18-mW 1.175–2-GHz FREQUENCY SYNTHESIZER 935 TABLE II PERFORMANCE SUMMARY AND COMPARISON WITH PRIOR ARTS few logic gates are added to extend the division range so the resulting division range is from 32 to 255. To save the power consumption, only the first two stages use the current mode logic (CML), and the following stages adopt CMOS circuits. The AFC loop uses a binary-search algorithm. Each unit com￾parison time of AFC is 4 s and a total of 16 s is used for per￾forming the AFC operation. V. EXPERIMENTAL RESULTS The wideband frequency synthesizer was implemented in a 0.18- m CMOS process. The die micrograph is shown in Fig. 9 and a summary of the measured chip performance is also in￾cluded. The die area is 2.2 mm , excluding PADs, electronic discharge (ESD) protection circuits, and controller. The power supply is 1.8 V. The measured closed-loop output frequency is shown in Fig. 10, which includes a total of 71 points with a division ratio from 93 to 163. The tuning gain varies from 70 to 90 MHz/V. The tuning gain variation is less than 12.5% across the entire wideband frequency range of 825 MHz. One possible reason for this small tuning gain variation is that the oscillation amplitude is not constant across the entire frequency range, as a result, the calculated average capacitance over an oscillation period varies slightly. The measured band step is from 50 to 60 MHz. The variation of the band step is less than 4.5%. Due to the adoption of the AFC loop, the differential control voltages fall between 0.4 V over the entire frequency range, and this ensures the operation of the VCO in the linear tuning region. Fig. 11 shows the oscillation amplitude power spectral den￾sity (PSD) at 1.6 GHz. The reference spur at a 12.5-MHz fre￾quency offset is below 55 dBc Hz. The measured phase noise at 1.6 GHz is plotted in Fig. 12 and is compared with the simula￾tion result. The spot phase noise is dBc Hz at a 10-kHz offset and 124.2 dBc Hz at a 1-MHz offset. The integrated phase error from 100 Hz to 10 MHz is 0.63 . The measured and simulated curves agree very well from 100 Hz to 10 MHz. The simulated phase-noise contributions of all the blocks are also depicted. At below 1-kHz offset, the noise from reference clock dominates; the CP contributes most at the in-band fre￾quency offset; the LPF contributes most from 30 to 500 kHz; and the VCO dominates at the far out-of-band frequency offset be￾yond 500 kHz. Phase-noise plots at frequency offsets of 10 kHz and 1 MHz with the oscillation frequency ranging from 1.2 to 2 GHz are shown in Fig. 13. The phase-noise curves have a flat characteristic across the entire frequency range. The variation is less than 1 dB. It is also shown that the closed loop has an av￾erage 3-dB bandwidth of 110 kHz and the bandwidth variation is less than 9%. The measured locking process is shown in Fig. 14. The AFC operation consumes 16 s, with 4 s for each unit comparison time. The remaining time for PLL operation is 84 s, and the total locking time is less than 100 s. Table II presents a performance comparison with recently re￾ported frequency synthesizers designed for DVB applications. This work used a single VCO, while the others used mul￾tiple (either two or three) VCOs. For the synthesizers using VCOs, this work achieved the highest normalized tuning range of 52%. The normalized tuning range is defined as the whole tuning range divided by the number of VCOs used. Even with a single VCO, the wideband frequency synthe￾sizer described in this paper still achieved an excellent phase￾noise performance. It consumed the smallest power with a com￾parable die area (compared with the synthesizers having a fully integrated LPF). In addition, the synthesizer adopted differential tuning modes to suppress the common-mode noise from control lines, power supply, and the substrate. A unique feature of the synthesizer is that it achieved a constant 3-dB closed-loop band￾width. The VCO is designed to achieve a constant band step , as well as a small and constant VCO gain . The CP cur￾rent is adjusted to match the division ratio

936 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES.VOL.57.NO.4.APRIL 2009 VI.CONCLUSION [9]D.Hauspie,E.-C.Park,and J.Craninckx,"Wideband VCO with simul- taneous switching of frequency band,active core,and varactor size," Having a constant bandwidth is essential for phase-noise op- IEEE J.Solid-State Circuits,vol.42.no.7.pp.1472-1480.Jul.2007. timization and ensuring loop stability for wideband frequency [10]T.Nakamura,T.Masuda,N.Shiramizu,K.Washio,T.Kitamura,and synthesizers.This paper reports a fully integrated 1.175-2-GHz N.Hayashi,"A wide-tuning-range VCO with small VCO-gain fluctu- ation for multi-band W-CDMA RFIC,"in Proc.Eur.Solid-State Cir- frequency synthesizer with a constant loop bandwidth for cuits Conf..Sep.2006.pp.448-451. DVB-T applications.Techniques for achieving a constant syn- [11]T.Y.Lin,T.Y.Yu,L.W.Ke,and G.K.Dehng."A low-noise VCO with a constant Fvco for GSM/GPRS/EDGE applications,"in Proc. thesizer loop bandwidth are proposed.To overcome the VCO IEEE Radio Freq.Integr.Circuits Symp.,Jun.208.pp.387-390. gain Kvco and the band step fres variations,a technique by [12]H.Lee,J.-K.Cho,K.-S.Lee.I-C.Hwang.T.-W.Ahn,K.-S.Nah, and B.-H.Park,"A C-L fractional-V frequency synthesizer using a simultaneously adjusting both the sizes of switched capacitors wide-band integrated VCO and a fast AFC technique for GSM/GPRS/ and varactors is developed.The procedure for calculating WCDMA applications,"IEEE J.Solid-State Circuits,vol.39,no.7,pp the switching capacitor and varactor sizes at each frequency 1164-1169,jul.2004. [13]K.-S.Lee,E.-Y.Sung,I.-C.Hwang,and B.-H.Park,"Fast AFC tech- band is also described.Furthermore,the CP current Icp is nique using a code estimation and binary search algorithm for wide- programmed to compensate the variation of division ratio N.In band frequency synthesis,"in Proc.Eur.Solid-State Circuits Conf., addition,an impedance transformation method is employed to Sep.2005,pp.448-451. [14]Z.Tang,J.He,and H.Min,"A low-phase-noise 1-GHz LC VCO dif- reduce the die area of the LPF allowing its on-chip integration. ferentially tuned by switched step capacitors,"in IEEE Asian Solid. The synthesizer was fabricated and validated in a 0.18-um State Circuits Conf..Nov.2005.pp.409-412. CMOS process.It achieved a normalized tuning range of 52% [15]E.Hegazi.H.Sjoland,and A.A.Abidi,"A filtering technique to lower LC oscillator phase noise,"IEEE J.Solid-State Circuits,vol.36,no using a single LC VCO,and a less than 12.5%VCO gain 12,Pp.1921-1930.Dec.2001」 Kvco variation,as well as a less than 4.5%band step fres [16]P.Andreani and S.Mattisson,"On the use of MOS varactors in RF VCO's,"IEEE J.Solid-State Circuits.vol.35,no.6,pp.905-910,Jun variation.The in-band phase noise at a 10-kHz offset is below 20D00 -97 dBc/Hz and the integrated phase error from 100 Hz to [17]R.L.Bunch and S.Raman,"Large-signal analysis of MOS varactors 10 MHz is0.63mIt has a nearly constant 3-dB closed-loop in CMOS-G LC VCOs."IEEE J.Solid-State Circuits.vol.38.no. 8.Pp.1325-1332,Aug.2003. bandwidth and a flat phase-noise characteristic across the entire [18]S.Cheng,H.Tong,J.Silva-Martinez,and A.I.Karsilayan,"Design wide frequency tuning range.The synthesizer consumes only and analysis of an ultrahigh-speed glitch-free fully differential charge 18 mW with a 1.8-V supply. pump with minimum output current variation and accurate matching," IEEE Trans.Circuits Syst.II,Exp.Briefs,vol.53.no.9.pp.843-847. Sep.2006. [19]M.Terrovitis,M.Mack,K.Singh,and M.Zargari,"A 3.2 to 4 GHz ACKNOWLEDGMENT 0.25 Ni CMOS frequency synthesizer for IEEE 802.11a/b/g WLAN." in IEEE Int.Solid-State Circuits Conf.Tech.Dig..Feb.2004.pp.95-96. The authors would like to thank L.Yang and X.Duo,both [20]K.Shu,E.Sanchez-Sinencio,J.Silva-Martinez,and S.Embabi,"A with the Semiconductor Manufacturing International Corpora- 2.4-GHz monolithic fractional-V frequency synthesizer with robust phase switching prescaler and loop capacitance multiplier,"IEEE J. tion (SMIC),Shanghai,China,for providing chip fabrication Solid-State Circuits,vol.38,no.6,pp.866-874,Jun.2003. and testing support.The authors would also like to thank the [21]C.S.Vaucher,I.Ferencic,M.Locher,S.Sedvallson.U.Voegeli,andZ. reviewers for the comments and suggestions,which help to im- Wang,"A family of low-power truly modular programmable dividers in standard 0.35-Ni CMOS technology."IEEE /Solid-State Circuits. prove the quality of this paper. vol.35,no.7,pp.1039-1045,Jul.2000. [22]A.Maxim,R.Poorfard,and J.Kao,"A sub-1.5 phase-noise ring-os cillator-based frequency synthesizer for low-IF single-chip DBS satel- REFERENCES lite tuner-demodulator SoC."in IEEE Int.Solid-State Circuits Conf. Tech.Dig.,Feb.2006,Pp.618-619. [1]D.Saias,F.Montaudon,E.Andre,F.Ballleul,M.Bely,P.Busson.S. [23]M.Marutani,H.Anbutsu,M.Kondo,N.Shirai,H.Yamazaki,and Y. Dedieu,A.Dezzani,A.Moutard,G.Provins,E.Rouat,J.Roux,G. Watanabe,"An 18 mW 90 to 770 MHz synthesizer with agile auto- Wagner.and F.Paillardet."A 0.12 Ni CMOS DVB-T tuner."in /EEE tuning for digital TV-tuners,"in IEEE Int.Solid-State Circuits Conf. Int.Solid-State Circuits Conf.Tech.Dig.,Feb.2005,pp.430-431. Tech.Dig.,Feb.2006,pp.192-193. [2]M.Dawkins,A.P.Burdett,and N.Cowley,"A single-chip tuner for [24]I.Vassiliou,K.Vavelidis,S.Bouras,S.Kavadias,Y.Kokolakis,G. DVB-T,"IEEE J.Solid-State Circuits,vol.38,no.8,pp.1307-1317, Kamoulakos,A.Kyranas,C.Kapnlstls,and N.Haralabldls,"A 0.18 Aug.2003. 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936 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 4, APRIL 2009 VI. CONCLUSION Having a constant bandwidth is essential for phase-noise op￾timization and ensuring loop stability for wideband frequency synthesizers. This paper reports a fully integrated 1.175–2-GHz frequency synthesizer with a constant loop bandwidth for DVB-T applications. Techniques for achieving a constant syn￾thesizer loop bandwidth are proposed. To overcome the VCO gain and the band step variations, a technique by simultaneously adjusting both the sizes of switched capacitors and varactors is developed. The procedure for calculating the switching capacitor and varactor sizes at each frequency band is also described. Furthermore, the CP current is programmed to compensate the variation of division ratio . In addition, an impedance transformation method is employed to reduce the die area of the LPF allowing its on-chip integration. The synthesizer was fabricated and validated in a 0.18- m CMOS process. It achieved a normalized tuning range of 52% using a single VCO, and a less than 12.5% VCO gain variation, as well as a less than 4.5% band step variation. The in-band phase noise at a 10-kHz offset is below 97 dBc Hz and the integrated phase error from 100 Hz to 10 MHz is 0.63 . It has a nearly constant 3-dB closed-loop bandwidth and a flat phase-noise characteristic across the entire wide frequency tuning range. The synthesizer consumes only 18 mW with a 1.8-V supply. ACKNOWLEDGMENT The authors would like to thank L. Yang and X. Duo, both with the Semiconductor Manufacturing International Corpora￾tion (SMIC), Shanghai, China, for providing chip fabrication and testing support. The authors would also like to thank the reviewers for the comments and suggestions, which help to im￾prove the quality of this paper. REFERENCES [1] D. Saias, F. Montaudon, E. Andre, F. Ballleul, M. Bely, P. Busson, S. Dedieu, A. Dezzani, A. Moutard, G. Provins, E. Rouat, J. Roux, G. Wagner, and F. Paillardet, “A 0.12 ￾m CMOS DVB-T tuner,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2005, pp. 430–431. [2] M. Dawkins, A. P. Burdett, and N. Cowley, “A single-chip tuner for DVB-T,” IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1307–1317, Aug. 2003. [3] S. Levantino, C. Samori, A. Bonfanti, S. L. J. Gierkin, A. L. Lacaita, and V. Boccuzzi, “Frequency dependence on bias current in 5-GHz CMOS VCOs: Impact on tuning range and flicker noise upconversion,” IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1003–1011, Aug. 2002. [4] J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, and M. Shankaradas, “Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL,” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1795–1803, Nov. 2003. [5] Y. Akamine, M. Kawabe, K. Hori, T. Okazaki, M. Kasahara, and S. Tanaka, “￾ PLL transmitter with a loop-bandwidth calibration system,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 497–506, Feb. 2008. [6] L. Lu, L. Yuan, H. Min, and Z. Tang, “A fully integrated 1.175-to-2 GHz frequency synthesizer with constant bandwidth for DVB-T appli￾cations,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., Jun. 2008, pp. 303–306. [7] M. G. Floyd, Phaselock Techniques, 3rd ed. New York: Wiley, 2005, pp. 12–28. [8] J. Lee and B. Kim, “A low-noise fast-lock phase-locked loop with adap￾tive bandwidth control,” IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1137–1145, Aug. 2000. [9] D. Hauspie, E.-C. Park, and J. Craninckx, “Wideband VCO with simul￾taneous switching of frequency band, active core, and varactor size,” IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1472–1480, Jul. 2007. [10] T. Nakamura, T. Masuda, N. Shiramizu, K. Washio, T. Kitamura, and N. Hayashi, “A wide-tuning-range VCO with small VCO-gain fluctu￾ation for multi-band W-CDMA RFIC,” in Proc. Eur. Solid-State Cir￾cuits Conf., Sep. 2006, pp. 448–451. [11] T. Y. Lin, T. Y. Yu, L. W. Ke, and G. K. Dehng, “A low-noise VCO with a constant for GSM/GPRS/EDGE applications,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., Jun. 2008, pp. 387–390. [12] H. Lee, J.-K. Cho, K.-S. Lee, I.-C. Hwang, T.-W. Ahn, K.-S. Nah, and B.-H. Park, “A –￾ fractional- frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/ WCDMA applications,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1164–1169, Jul. 2004. [13] K.-S. Lee, E.-Y. Sung, I.-C. Hwang, and B.-H. Park, “Fast AFC tech￾nique using a code estimation and binary search algorithm for wide￾band frequency synthesis,” in Proc. Eur. Solid-State Circuits Conf., Sep. 2005, pp. 448–451. [14] Z. Tang, J. He, and H. Min, “A low-phase-noise 1-GHz  VCO dif￾ferentially tuned by switched step capacitors,” in IEEE Asian Solid￾State Circuits Conf., Nov. 2005, pp. 409–412. [15] E. Hegazi, H. Sjöland, and A. A. Abidi, “A filtering technique to lower  oscillator phase noise,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921–1930, Dec. 2001. [16] P. Andreani and S. Mattisson, “On the use of MOS varactors in RF VCO’s,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 905–910, Jun. 2000. [17] R. L. Bunch and S. Raman, “Large-signal analysis of MOS varactors in CMOS-  VCOs,” IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1325–1332, Aug. 2003. [18] S. Cheng, H. Tong, J. Silva-Martinez, and A. I. Karsilayan, “Design and analysis of an ultrahigh-speed glitch-free fully differential charge pump with minimum output current variation and accurate matching,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 9, pp. 843–847, Sep. 2006. [19] M. Terrovitis, M. Mack, K. Singh, and M. Zargari, “A 3.2 to 4 GHz 0.25 ￾m CMOS frequency synthesizer for IEEE 802.11a/b/g WLAN,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2004, pp. 95–96. [20] K. Shu, E. Sánchez-Sinencio, J. Silva-Martínez, and S. Embabi, “A 2.4-GHz monolithic fractional- frequency synthesizer with robust phase switching prescaler and loop capacitance multiplier,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 866–874, Jun. 2003. [21] C. S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli, and Z. Wang, “A family of low-power truly modular programmable dividers in standard 0.35- ￾m CMOS technology,” IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 1039–1045, Jul. 2000. [22] A. Maxim, R. Poorfard, and J. Kao, “A sub-1.5 phase-noise ring-os￾cillator-based frequency synthesizer for low-IF single-chip DBS satel￾lite tuner-demodulator SoC,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2006, pp. 618–619. [23] M. Marutani, H. Anbutsu, M. Kondo, N. Shirai, H. Yamazaki, and Y. Watanabe, “An 18 mW 90 to 770 MHz synthesizer with agile auto￾tuning for digital TV-tuners,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2006, pp. 192–193. [24] I. Vassiliou, K. Vavelidis, S. Bouras, S. Kavadias, Y. Kokolakis, G. Kamoulakos, A. Kyranas, C. Kapnlstls, and N. Haralabldls, “A 0.18 ￾m CMOS dual-band direct-conversion DVB-H receiver,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2006, pp. 606–607. [25] M. Gupta, S. Lerstaveesin, D. Kang, and B.-S. Song, “A 48-to-860 MHz CMOS direct-conversion TV tuner,” in IEEE Int. Solid-State Cir￾cuits Conf. Tech. Dig., Feb. 2007, pp. 206–207. Lei Lu (S’07) was born in Bengbu, Anhui, China, in 1982. He received the B.S. degree in electronics in￾formation engineering from the Shanghai University of Electric Power (SUEP), Shanghai, China, in 2004 and is currently working toward the Ph.D. degree in microelectronics at Fudan University, Shanghai, China. Since September 2007, he has been with Shanghai Ratio Microelectronics Technology Company Ltd., Shanghai, China, where he designed wideband fractional- frequency synthesizers for DTV ap￾plications as an Intern. His current research interests include modeling and parameter extraction of on-chip inductors, quadrature and wideband VCOs, as well as wideband fractional- and all-digital frequency synthesizers.

LU et al:18-mW 1.175-2-GHz FREQUENCY SYNTHESIZER 937 Jinghong Chen (M'06-SM'07)received the B.S. Hao Min received the B.S.and M.S.degrees in and M.S.degrees in engineering physics from electrical engineering and Ph.D.degree in material Tsinghua University,Beijing.China,in 1992 and science from Fudan University.Shanghai,China,in 1994.respectively,the Master of Engineering degree 1985,1988,and 1991,respectively. in electrical engineering from the University of From 1991 to 1998,he was an Associate Pro- Virginia,Charlottesville,in 1995,and the Ph.D. fessor with the Application Specific Integrated degree in electrical engineering from the University Circuit (ASIC)and Systems State Key Laboratory, of Illinois at Urbana-Champaign.in 2001. Fudan University.From 1995 to 1998.he was a In January 2001,he joined the High-Speed Com- Visiting Associate Professor with the Department munication Very Large Scale Integration (VLSI) of Electrical Engineering,Stanford University, Research Department,Bell Laboratories,Holmdel. Stanford,CA.where he was involved in low-power NJ.In September 2001,he joined Agere Systems (formerly the Microelec- mixed-signal very large scale integration (VLSI)design,especially in the tronics Group,Lucent Technologies).At Bell Laboratories and Agere Systems, design and characterizing of CMOS image sensors.Since 1998,he has been a he was involved with mixed-signal and RF circuits for optical,backplane Professor and Director of the ASIC and System State Key Laboratory.Fudan interconnect,and wireless communications.Since December 2006,he has been University.In 2002.he began the Auto-ID Center of China and is currently the with Analog Devices,Somerset NJ,where he has been involved with circuit Research Director of Auto-ID Laboratory,Fudan University.He has authored and system design for XM satellite radio and MoCa-based home networking or coauthored over 50 papers in journals and conferences.He has ten patents products.His current research interests include wideband circuits.integrated pending.His current research interests include VLSI architecture,RF and RF transceivers,high-performance frequency synthesizers,high-speed sig- mixed-signal integrated circuit (IC)design,digital signal processing,and image naling.and device modeling and computer-aided design(CAD). processing. Lu Yuan received the B.S.and M.S.degrees in Zhangwen Tang(S'01-M'05)received the B.S.and microelectronics from Fudan University,Shanghai, Ph.D.degrees in electrical engineering from Fudan China,in 2005 and 2008,respectively. University,Shanghai,China,in 1999 and 2004,re- Since September 2007,he has been with the spectively. Shanghai Ratio Microelectronics Technology Com- From 2004 to 2007,he was an Assistant Professor pany Ltd..Shanghai,China,where he designed with the School of Microelectronics at Fudan Univer- wideband NF VCOs for DTV applications as an sity.From March to May in 2006,he was studying Intern.His current research interests include NF the course of Analog Design Essentials in the K.U. VCOs and wideband frequency synthesizers. Leuven and IMEC,Belgium.Since 2008,he is an As- sociate Professor with the Department of Microelec- tronics,Fudan University.His current research inter- ests include CMOS mixed-signal and radio-frequency circuits for DTV Tuner applications.He is an author or co-author of more than 40 papers in journals and conference proceedings.He is a co-founder of Ratio Microelectronics Tech- nology,Shanghai,China

LU et al.: 18-mW 1.175–2-GHz FREQUENCY SYNTHESIZER 937 Jinghong Chen (M’06–SM’07) received the B.S. and M.S. degrees in engineering physics from Tsinghua University, Beijing, China, in 1992 and 1994, respectively, the Master of Engineering degree in electrical engineering from the University of Virginia, Charlottesville, in 1995, and the Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign, in 2001. In January 2001, he joined the High-Speed Com￾munication Very Large Scale Integration (VLSI) Research Department, Bell Laboratories, Holmdel, NJ. In September 2001, he joined Agere Systems (formerly the Microelec￾tronics Group, Lucent Technologies). At Bell Laboratories and Agere Systems, he was involved with mixed-signal and RF circuits for optical, backplane interconnect, and wireless communications. Since December 2006, he has been with Analog Devices, Somerset NJ, where he has been involved with circuit and system design for XM satellite radio and MoCa-based home networking products. His current research interests include wideband circuits, integrated RF transceivers, high-performance frequency synthesizers, high-speed sig￾naling, and device modeling and computer-aided design (CAD). Lu Yuan received the B.S. and M.S. degrees in microelectronics from Fudan University, Shanghai, China, in 2005 and 2008, respectively. Since September 2007, he has been with the Shanghai Ratio Microelectronics Technology Com￾pany Ltd., Shanghai, China, where he designed wideband ￾ VCOs for DTV applications as an Intern. His current research interests include ￾ VCOs and wideband frequency synthesizers. Hao Min received the B.S. and M.S. degrees in electrical engineering and Ph.D. degree in material science from Fudan University, Shanghai, China, in 1985, 1988, and 1991, respectively. From 1991 to 1998, he was an Associate Pro￾fessor with the Application Specific Integrated Circuit (ASIC) and Systems State Key Laboratory, Fudan University. From 1995 to 1998, he was a Visiting Associate Professor with the Department of Electrical Engineering, Stanford University, Stanford, CA, where he was involved in low-power mixed-signal very large scale integration (VLSI) design, especially in the design and characterizing of CMOS image sensors. Since 1998, he has been a Professor and Director of the ASIC and System State Key Laboratory, Fudan University. In 2002, he began the Auto-ID Center of China and is currently the Research Director of Auto-ID Laboratory, Fudan University. He has authored or coauthored over 50 papers in journals and conferences. He has ten patents pending. His current research interests include VLSI architecture, RF and mixed-signal integrated circuit (IC) design, digital signal processing, and image processing. Zhangwen Tang (S’01–M’05) received the B.S. and Ph.D. degrees in electrical engineering from Fudan University, Shanghai, China, in 1999 and 2004, re￾spectively. From 2004 to 2007, he was an Assistant Professor with the School of Microelectronics at Fudan Univer￾sity. From March to May in 2006, he was studying the course of Analog Design Essentials in the K. U. Leuven and IMEC, Belgium. Since 2008, he is an As￾sociate Professor with the Department of Microelec￾tronics, Fudan University. His current research inter￾ests include CMOS mixed-signal and radio-frequency circuits for DTV Tuner applications. He is an author or co-author of more than 40 papers in journals and conference proceedings. He is a co-founder of Ratio Microelectronics Tech￾nology, Shanghai, China.