Vol.34,No.9 Journal of Semiconductors September 2013 A high linearity multi-band and gain adjustable channel-select filter for TV-tuner application Wang Xin(王心)，Cheng Tao(程涛)，Liu Jie(刘杰)，and Tang Zhangwen(唐长文) ASIC System State Key Laboratory,Fudan University,Shanghai 201203,China Abstract:This paper presents a channel-select filter that employs an active-RC bi-quad structure for TV-tuner application.A design method to optimize the IIP3 of the bi-quad is developed.Multi-band selection and gain adjustment are implemented using switching resistors in the resistor array and capacitors in the capacitor array. Q-factor degradation is compensated by a tuning segmented resistor.A feed-forward OTA with high gain and low third-order distortion is applied in the bi-quad to maximize linearity performance and minimize area by avoiding extra compensation capacitor use.An RC tuning circuit and DC offset cancellation circuit are designed to overcome the process variation and DC offset,respectively.The experimental results yield an in-band IIP3 of more than 31 dBm at 0 dB gain,a 54 dB gain range with 6 dB gain step,and a continuous frequency tuning range from 0.25 to 4 MHz.The in-band ripple is less than 1.4 dB at high gain mode,while the gain error and frequency tuning error are no more than 3.4%and 5%,respectively.The design,which is fabricated in a 0.18 um CMOS process,consumes 12.6 mW power at a 1.8 V supply and occupies 1.28 mm2 Key words:channel select filter,high linearity;gain adjustable;multi-band,TV tuner D0I:10.1088/1674-4926/34/9/095007 EEACC:1270E 1.Introduction power consumptions has not yet been discussed. In this paper,an optimization method maximizing the bi- Recently,increasing attention has been paid to direct con- quad IIP3 by choosing optimal parameters of passive compo- version receivers (DCRs)due to their low power,small area nents in the bi-quad is discussed in detail for filter design.The and insensitiveness of image problem[].It is shown that multi- band selection is completed not only using a resistor array, mode and multi-band DCR TV-tuner solutions are economical which could just realize discrete frequency selection,but also for applications2).In this architecture,a channel-select filter, using a binary capacitor array,which is economical for realiz- which could select the wanted channels and filter out unwanted ing continuous frequency tuning.An on-chip auto-RC calibra- adjacent-channel interference,is needed.There are two impor- tion circuit is designed to ensure an accurate cutoff frequency tant issues in DCRs that could be harmful to base-band cir- under RC variation cuits3).The first is DC offset due to the self-mixing of the Unlike the traditional structure that uses a programmable mixer and other DC offset sources in the base band,such as gain amplifier(PGA)with a large gain range before the chan- the op-amp offset.The second is the 1/f noise.The most chal- nel select filter to cover the variation in base-band input signal lenging aspect for the design of channel-select filters in the base strength,a gain variable filter with a large gain range and small band is the high linearity requirement due to the large range gain error is proposed in this paper.The benefit of this system is variation in the desired signal strength and the strong out-of- that the optimization of IIP3 and noise can be considered at the band interference,which could destroy the performance of the same time to maximize the SFDR of the base-band circuit.In filter.So,a channel-select filter with DC offset cancellation, the final stage of the signal path,a post-PGA,which functions low noise,high in-band IIP3,as well as out-of-band IIP3 and as an output buffer,is used to realize fine gain adjustment. multiple band selection,is needed for multi-standard TV-tuner applications.An active-RC filter is usually hired due to its high linearity performance[4.5]. 2.System design considerations The Volterra series is usually used to analyze the linear- ity performance of a memory systeml6].But multi-feedback, 2.1.The filter structure which is commonly used in filter design,is not convenient and In a DCR system,the channel-select filter is actually a low- efficient for analysis using a signal flow graph(SFG).To sim- pass filter.The trade-off between power and adjacent rejection plify linearity analysis using the Volterra series,References[7, determines the order of the filter.An elliptic filter is chosen to ]discussed a new approach that treats multiple feedback loops meet the stringent rejection specification,as this type always as a two-port network by introducing three new network trans- provides a larger roll-off rate and moderate group delay at the fer functions.The scaling down technique was introduced to same order compared to other types of filter. deal with the trade-off between the dynamic range or SFDR A Tow-Thomas II bi-quad is chosen as the building block performance and power consumption.But the optimal para- of this active RC filter to realize high linearity performance meter determination of components in the filter under certain and orthogonal adjustment on the DC gain,cutoff frequency Corresponding author.Email:zwtang54@fudan.edu.cn Received 26 February 2013,revised manuscript received 3 April 2013 2013 Chinese Institute of Electronics 095007-1
Vol. 34, No. 9 Journal of Semiconductors September 2013 A high linearity multi-band and gain adjustable channel-select filter for TV-tuner application Wang Xin(王心), Cheng Tao(程涛), Liu Jie(刘杰), and Tang Zhangwen(唐长文) ASIC & System State Key Laboratory, Fudan University, Shanghai 201203, China Abstract: This paper presents a channel-select filter that employs an active-RC bi-quad structure for TV-tuner application. A design method to optimize the IIP3 of the bi-quad is developed. Multi-band selection and gain adjustment are implemented using switching resistors in the resistor array and capacitors in the capacitor array. Q-factor degradation is compensated by a tuning segmented resistor. A feed-forward OTA with high gain and low third-order distortion is applied in the bi-quad to maximize linearity performance and minimize area by avoiding extra compensation capacitor use. An RC tuning circuit and DC offset cancellation circuit are designed to overcome the process variation and DC offset, respectively. The experimental results yield an in-band IIP3 of more than 31 dBm at 0 dB gain, a 54 dB gain range with 6 dB gain step, and a continuous frequency tuning range from 0.25 to 4 MHz. The in-band ripple is less than 1.4 dB at high gain mode, while the gain error and frequency tuning error are no more than 3.4% and 5%, respectively. The design, which is fabricated in a 0.18 m CMOS process, consumes 12.6 mW power at a 1.8 V supply and occupies 1.28 mm2 . Key words: channel select filter; high linearity; gain adjustable; multi-band; TV tuner DOI: 10.1088/1674-4926/34/9/095007 EEACC: 1270E 1. Introduction Recently, increasing attention has been paid to direct conversion receivers (DCRs) due to their low power, small area and insensitiveness of image problemŒ1. It is shown that multimode and multi-band DCR TV-tuner solutions are economical for applicationsŒ2. In this architecture, a channel-select filter, which could select the wanted channels and filter out unwanted adjacent-channel interference, is needed. There are two important issues in DCRs that could be harmful to base-band circuitsŒ3. The first is DC offset due to the self-mixing of the mixer and other DC offset sources in the base band, such as the op-amp offset. The second is the 1/f noise. The most challenging aspect for the design of channel-select filters in the base band is the high linearity requirement due to the large range variation in the desired signal strength and the strong out-ofband interference, which could destroy the performance of the filter. So, a channel-select filter with DC offset cancellation, low noise, high in-band IIP3, as well as out-of-band IIP3 and multiple band selection, is needed for multi-standard TV-tuner applications. An active-RC filter is usually hired due to its high linearity performanceŒ4; 5 . The Volterra series is usually used to analyze the linearity performance of a memory systemŒ6. But multi-feedback, which is commonly used in filter design, is not convenient and efficient for analysis using a signal flow graph (SFG). To simplify linearity analysis using the Volterra series, References [7, 8] discussed a new approach that treats multiple feedback loops as a two-port network by introducing three new network transfer functions. The scaling down technique was introduced to deal with the trade-off between the dynamic range or SFDR performance and power consumption. But the optimal parameter determination of components in the filter under certain power consumptions has not yet been discussed. In this paper, an optimization method maximizing the biquad IIP3 by choosing optimal parameters of passive components in the bi-quad is discussed in detail for filter design. The band selection is completed not only using a resistor array, which could just realize discrete frequency selection, but also using a binary capacitor array, which is economical for realizing continuous frequency tuning. An on-chip auto-RC calibration circuit is designed to ensure an accurate cutoff frequency under RC variation. Unlike the traditional structure that uses a programmable gain amplifier (PGA) with a large gain range before the channel select filter to cover the variation in base-band input signal strength, a gain variable filter with a large gain range and small gain error is proposed in this paper. The benefit of this system is that the optimization of IIP3 and noise can be considered at the same time to maximize the SFDR of the base-band circuit. In the final stage of the signal path, a post-PGA, which functions as an output buffer, is used to realize fine gain adjustment. 2. System design considerations 2.1. The filter structure In a DCR system, the channel-select filter is actually a lowpass filter. The trade-off between power and adjacent rejection determines the order of the filter. An elliptic filter is chosen to meet the stringent rejection specification, as this type always provides a larger roll-off rate and moderate group delay at the same order compared to other types of filterŒ9 . A Tow-Thomas II bi-quad is chosen as the building block of this active RC filter to realize high linearity performance and orthogonal adjustment on the DC gain, cutoff frequency † Corresponding author. Email: zwtang54@fudan.edu.cn Received 26 February 2013, revised manuscript received 3 April 2013 © 2013 Chinese Institute of Electronics 095007-1
J.Semicond.2013,34(9) Wang Xin et al. DCOC DCOC DCOC G=0-54dB G=0-18dB G=0-18dB G=0-18dB Q=0.61 0=1.45 0=5.04 。=0.2-4MHz Biquad 1 Biquad 2 Biquad 3 Fig.1.The filter structure including DCOC R 1+2 Hs)=H。 w C 品 1+-5 vinp von -vop o-RRCC: R w-RRCC. R S3 S2 000000- R R Fig.2.The Tow-Thomas bi-quad structure and O factor.Figure I shows the structure of the filter,includ- the main cause of distortion in the bi-quad is the nonlinearity ing the DC offset cancellation(DCOC)loop at each stage.A of OTAs.As will be shown below,the IIP3 and DC gain of the six order filter is realized by cascading three bi-quads together. OTA determines the IIP3 of the bi-quad.The feedback path Each stage has an 18 dB gain range and the cutoff frequency could also have an impact on the linearity performance.The is tunable.So the filter has a 54 dB gain range in total.Fig- Volterra series is usually used to analyze the linearity perfor- ure 2 shows a detailed schematic of a single bi-quad.All the mance ofa memory system,but it is cumbersome to simplify resistor arrays and capacitor arrays are tunable.A classic net- multiple feedback paths using SFG.In Refs.[7,8],another use- work analysis of the bi-quad reveals the gain,cutoff frequency ful analysis method was introduced and exemplified,but the and O factor,which could change by adjusting Re,Ra and Rd, discussions were mainly restricted to the scaling technique, respectively.To maximize the in-band linearity performance, which needs to scale all the elements using different scaling high-O poles are assigned to the nearby zeros instead of re- factors at the same time.In this paper,employing a similar ap- mote zeros.Figure 3 shows the pole-zero pairing scheme.This proach,a procedure which is used in this design to maximize kind of pole-zero pairing could minimize the amplitude peak the IIIP3 of the bi-quad by normalizing all the passive element of high-O poles near the cutoff frequency.The bi-quads are parameters to a reference resistance and capacitance when the ordered as the O-factor gradually increases to maximize the IIP3 and DC gain of the OTA are fixed is developed. in-band IIP3. Because of balance structure use,the second-order dis- tortion of the bi-quad could be ignored.As shown in Fig.4, 2.2.IIP3 optimization two different kinds of transfer functions,which have been ex- Since passive resistors and capacitors can be very linear, plained in Ref.[8],are used.Hoi is the transfer function from 095007-2
J. Semicond. 2013, 34(9) Wang Xin et al. Fig. 1. The filter structure including DCOC. Fig. 2. The Tow-Thomas bi-quad structure. and Q factor. Figure 1 shows the structure of the filter, including the DC offset cancellation (DCOC) loop at each stage. A six order filter is realized by cascading three bi-quads together. Each stage has an 18 dB gain range and the cutoff frequency is tunable. So the filter has a 54 dB gain range in total. Figure 2 shows a detailed schematic of a single bi-quad. All the resistor arrays and capacitor arrays are tunable. A classic network analysis of the bi-quad reveals the gain, cutoff frequency and Q factor, which could change by adjusting Rc, Ra and Rd, respectively. To maximize the in-band linearity performance, high-Q poles are assigned to the nearby zeros instead of remote zeros. Figure 3 shows the pole-zero pairing scheme. This kind of pole-zero pairing could minimize the amplitude peak of high-Q poles near the cutoff frequency. The bi-quads are ordered as the Q-factor gradually increases to maximize the in-band IIP3. 2.2. IIP3 optimization Since passive resistors and capacitors can be very linear, the main cause of distortion in the bi-quad is the nonlinearity of OTAs. As will be shown below, the IIP3 and DC gain of the OTA determines the IIP3 of the bi-quad. The feedback path could also have an impact on the linearity performance. The Volterra series is usually used to analyze the linearity performance of a memory systemŒ6, but it is cumbersome to simplify multiple feedback paths using SFG. In Refs. [7, 8], another useful analysis method was introduced and exemplified, but the discussions were mainly restricted to the scaling technique, which needs to scale all the elements using different scaling factors at the same time. In this paper, employing a similar approach, a procedure which is used in this design to maximize the IIIP3 of the bi-quad by normalizing all the passive element parameters to a reference resistance and capacitance when the IIP3 and DC gain of the OTA are fixed is developed. Because of balance structure use, the second-order distortion of the bi-quad could be ignored. As shown in Fig. 4, two different kinds of transfer functions, which have been explained in Ref. [8], are used. H0j is the transfer function from 095007-2
J.Semicond.2013,34(9) Wang Xin et al. 1000 p-z of biquad3 600 p-z of biquad2 1,g +8 200 复 p-z of biquadl Feedback -200 network Nearby zero *8 -600 1,3 Remote zero *0 -100 80 -60 -40 -20 0 20 Real part (MHz) Fig.4.The distortion analysis model. Fig.3.Pole and zero pairing. the input of the bi-quad to the output of jth OTA,while Foi is Rd= (5) the transfer function from the input of jth OTA to the output of WpC the bi-quad.In Fig.4,the two-tone input and distortion impact So IIP3 could be expressed like of each OTA are shown.The total third-order intermodulation distortion(IMD3)product of the output is the sum of two dis- tortion outputs from each OTA.This could be expressed like IIP3= V1P3,oTA× 唱 Ho IMD3= —(H61Fo1+H2Fo2). VIP3.OTA (1) ai where ViP3,oTA is the IIP3 of OTA,and is the linear gain of (1+Ho)+QopCRa+1 OTA.IIP3 can be expressed as R (6) IIP3 VuP3.OTA Hoa (2) Ho1 Fo1+Ho2 Fo2 This tells us that the IIP3 of the bi-quad could be improved by increasing the IIP3 of OTA,and the high gain of the fil- Ho1,Ho2,Fo1,Fo2 are calculated using typical network ter means a low IIP3.Suppose OTA has maximum IIP3 and circuit analysis.If we focus on the in-band IIP3,to simplify enough high DC gain at certain power consumption.The IIP3 analysis,p is a reasonable assumption.In this case, of the filter could be improved further by optimizing the feed- back loops,which means choosing proper passive element Ho1≈H0R b Ho2≈Ho, parameters in the feedback network.For a fixed C,if we set Fo1≈1+Ho, F2≈1+ Rb Ra=(3+3Ho)/41 @pOc (7) Substitute these expressions into Eq.(7),and we get maximum IIP3 could be reached.But the optimal value could change if the filter operates under different gain modes.We focus on the low gain mode because the input signal strength IIP3 ViIP3,OTA a ⊙ (3) is typically strong at this mode.In this case,Ho equals 1.Thus, R Ra Ra,p3≈1.57/op0C. (1+Ho)+ +1 Rb Whether Ra could equal this value depends on other spec- ifications.To found out the limitation on Ra,the noise charac- Once the filter has been designed on a system level,all the teristic also needs to be analyzed.The noise analysis model is parameters like p,Q are fixed.This means that the product shown in Fig.5.Rn is the equivalent input noise resistor of the of Ra,Rp,Ci and C2 is constant.The minimum area of the OTA.The total output noise of the bi-quad is capacitors and resistors is achieved when Ra is equal to Rp and Ci equal to C2.For simplifying the analysis,we set C1= C2=C.Using filter parameter expressions,Ro and Ra could be normalized to Ra and C,and expressed as ≈4kTR(2++QCR 1 Rb= RawC2' (4) +++(合+门 095007-3
J. Semicond. 2013, 34(9) Wang Xin et al. Fig. 3. Pole and zero pairing. the input of the bi-quad to the output of j th OTA, while F0j is the transfer function from the input of j th OTA to the output of the bi-quad. In Fig. 4, the two-tone input and distortion impact of each OTA are shown. The total third-order intermodulation distortion (IMD3) product of the output is the sum of two distortion outputs from each OTA. This could be expressed like IMD3 D v 3 in ˛ 3 1V 2 IIP3; OTA H3 01F01 C H3 02F02 ; (1) where VIIP3; OTA is the IIP3 of OTA, and ˛1 is the linear gain of OTA. IIP3 can be expressed as IIP3 D VIIP3; OTAs H0˛ 3 1 H3 01F01 C H3 02F02 : (2) H01, H02, F01, F02 are calculated using typical network circuit analysis. If we focus on the in-band IIP3, to simplify analysis, ! !p is a reasonable assumption. In this case, H01 H0 Rb Rd ; H02 H0; F01 1 C H0; F02 1 C Rd Rb : Substitute these expressions into Eq. (7), and we get IIP3 D VIIP3; OTA H0 vuuuut ˛ 3 1 Rb Rd 3 .1 C H0/ C Rd Rb C 1 : (3) Once the filter has been designed on a system level, all the parameters like !p, Q are fixed. This means that the product of Ra, Rb, C1 and C2 is constant. The minimum area of the capacitors and resistors is achieved when Ra is equal to Rb and C1 equal to C2. For simplifying the analysis, we set C1 D C2 D C. Using filter parameter expressions, Rb and Rd could be normalized to Ra and C, and expressed as Rb D 1 Ra!2 pC2 ; (4) Fig. 4. The distortion analysis model. Rd D Q !pC : (5) So IIP3 could be expressed like IIP3 D VIIP3; OTA H0 vuuuut ˛ 3 1 1 Q!pC 3 1 Ra 3 .1 C H0/ C Q!pCRa C 1 : (6) This tells us that the IIP3 of the bi-quad could be improved by increasing the IIP3 of OTA, and the high gain of the filter means a low IIP3. Suppose OTA has maximum IIP3 and enough high DC gain at certain power consumption. The IIP3 of the filter could be improved further by optimizing the feedback loops, which means choosing proper passive element parameters in the feedback network. For a fixed C, if we set Ra D .3 C 3H0/ 1=4 1 !pQC ; (7) maximum IIP3 could be reached. But the optimal value could change if the filter operates under different gain modes. We focus on the low gain mode because the input signal strength is typically strong at this mode. In this case, H0 equals 1. Thus, Ra; IIP3 1:57=!pQC. Whether Ra could equal this value depends on other specifications. To found out the limitation on Ra, the noise characteristic also needs to be analyzed. The noise analysis model is shown in Fig. 5. Rn is the equivalent input noise resistor of the OTA. The total output noise of the bi-quad is V 2 n; out 4kTRa 2 C H0 C 1 Q!pCRa C 4kTRn " .1 C H0/ 2 C 1 Q C !pRaC 2 # : (8) 095007-3
J.Semicond.2013,34(9) Wang Xin et al. R R =4KTR Fig.5.The noise analysis model 60 60 IIP3 @0 dB+ 50 20 IIP3 18dB+ 40 NF @0dB 30 -20 Frequency range -40 NF 18 dB 20 Fig.7.The band selection and frequency tuning scheme. 60 10 102 10 10 10 109 ferent cutoff frequencies.So,by switching resistors in the re- R(2) sistor array,the bandwidth of the filter could change from one to another.The first flaw in this method is that the number of Fig.6.The optimization of IIP3 and NF trade-off. bands is restricted by the number of resistors in the array,and the second is that it can only realize discrete frequency tuning. According to the definition of noise figure in Ref.[10],we get By adding a capacitor array as shown in Fig.7,a mixed ap- proach is employed in this design.The resistor array is used to NF=1+ select a center frequency,and by increasing or decreasing the 4kTRs number of unit capacitors in the capacitor array,the cutoff fre- quency could change around the center frequency.Thus,the ≈1+ 2+H0+ cutoff frequency of the filter is continuously adjustable.This RsHo QopCRa step is determined by the capacitance of the unit capacitor in the capacitor array.To maintain an elliptic frequency response (1+Ho)2+ (9) shape,Ro,Re,Rd,and Cz should change at the same time ac- RsHo +@pR.C cording to Ra and C. Three indications are conveyed in this expression:(1)the noise Accuracy gain is desired to ensure that the auto gain con- contribution of Ra is individually decided by the filter and ca- trol (AGC)loop is working correctly.As analyzed before,the pacitance parameters;(2)Re contributes more noise at high gain of the bi-quad is determined by the ratio of the two re- gain mode;and (3)the OTA noise could be dominant if its input sistors.Re is chosen to change the gain of the bi-quad due to equivalent noise is large enough. Re having no influence on the cutoff frequency.As shown in To show the trade-off between IIP3 and NF.Figure 6 plots Fig.2.R.is a resistor array with segmented resistors.The array the relationship of NF and IIP3 with Ra.C could be chosen operates synchronously with the switching of Ra to maintain an under chip area consideration.In this example,we set C= elliptic filter frequency response,while segmented resistors are 3 pF.As is shown in the graph,the range of resistor values is used to change the gain of the bi-quad.Figure 8 shows the SFG determined by the specification of IIP3 at low gain and NF at of the bi-quad with a non-ideal integrator model.A(j@)is the high gain.If we choose Ra at the right side of the optimal value, open loop gain of OTA.Using SFG analysis,a more accurate IIP3 could be less sensitive to the variation in Ra.but the noise expression of the bi-quad transfer function is given as will be higher because of the larger value of Ra.Below the optimal value of Ra.IIP3 changes dramatically with Ra while 1+5 s2 十 the NF curve is relatively flat. H6)=Ar“a2aT 1+5 2 (10) 3.Circuit design 0.+ag 3.1.Band selection and gain adjustment Subscriptr indicates the effective filter parameter differing Since the cutoff frequency is determined by the RC prod- from the ideal one.As explained in Ref.[9],gain and O are uct,if C remains constant,then different resistors refer to dif- more dependent on A(j).The ratio of effective gain and O 095007-4
J. Semicond. 2013, 34(9) Wang Xin et al. Fig. 5. The noise analysis model. Fig. 6. The optimization of IIP3 and NF trade-off. According to the definition of noise figure in Ref. [10], we get NF D 1 C V 2 n;in 4kTRs 1 C Ra RsH2 0 2 C H0 C 1 Q!pCRa C Rn RsH2 0 " .1 C H0/ 2 C 1 Q C !pRaC 2 # : (9) Three indications are conveyed in this expression: (1) the noise contribution of Rd is individually decided by the filter and capacitance parameters; (2) Rc contributes more noise at high gain mode; and (3) the OTA noise could be dominant if its input equivalent noise is large enough. To show the trade-off between IIP3 and NF, Figure 6 plots the relationship of NF and IIP3 with Ra. C could be chosen under chip area consideration. In this example, we set C D 3 pF. As is shown in the graph, the range of resistor values is determined by the specification of IIP3 at low gain and NF at high gain. If we choose Ra at the right side of the optimal value, IIP3 could be less sensitive to the variation in Ra, but the noise will be higher because of the larger value of Ra. Below the optimal value of Ra, IIP3 changes dramatically with Ra while the NF curve is relatively flat. 3. Circuit design 3.1. Band selection and gain adjustment Since the cutoff frequency is determined by the RC product, if C remains constant, then different resistors refer to difFig. 7. The band selection and frequency tuning scheme. ferent cutoff frequencies. So, by switching resistors in the resistor array, the bandwidth of the filter could change from one to another. The first flaw in this method is that the number of bands is restricted by the number of resistors in the array, and the second is that it can only realize discrete frequency tuning. By adding a capacitor array as shown in Fig. 7, a mixed approach is employed in this design. The resistor array is used to select a center frequency, and by increasing or decreasing the number of unit capacitors in the capacitor array, the cutoff frequency could change around the center frequency. Thus, the cutoff frequency of the filter is continuously adjustable. This step is determined by the capacitance of the unit capacitor in the capacitor array. To maintain an elliptic frequency response shape, Rb, Rc, Rd, and Cz should change at the same time according to Ra and C. Accuracy gain is desired to ensure that the auto gain control (AGC) loop is working correctly. As analyzed before, the gain of the bi-quad is determined by the ratio of the two resistors. Rc is chosen to change the gain of the bi-quad due to Rc having no influence on the cutoff frequency. As shown in Fig. 2, Rc is a resistor array with segmented resistors. The array operates synchronously with the switching of Ra to maintain an elliptic filter frequency response, while segmented resistors are used to change the gain of the bi-quad. Figure 8 shows the SFG of the bi-quad with a non-ideal integrator model. A(j!/ is the open loop gain of OTA. Using SFG analysis, a more accurate expression of the bi-quad transfer function is given as Hr .s/ D H0r 1 C s !zrQzr C s 2 !2 zr 1 C s !prQr C s 2 !2 pr : (10) Subscript r indicates the effective filter parameter differing from the ideal one. As explained in Ref. [9], gain and Q are more dependent on A(j!/. The ratio of effective gain and Q 095007-4
J.Semicond.2013,34(9) Wang Xin et al. R Input stage IFeedforward stagel Output stage R.C.s Local CMFB · 2-13 vop T+9 Ts+92 R M4 M5 16 M8 M9 9,=-0RC 9,=-3C M3 T=RC TRC2 A(jo) A(j@) Fig.8.The SFG of the bi-quad with a non-ideal integrator model Fig.10.Schematic of the feed-forward OTA. S3 An accurate 6 dB gain step should be achieved if the value of the effective Re also has a binary property.But in Fig.9(a), no matter what sizes of transistors are used.it is impossible to S2 4WL丁 realize a binary effective Re because of non-symmetry.On the contrary,by adding an additional switch and properly sizing, which is shown in Fig.9(b),an effective Re could have a bi- 2WL nary property.Thus,the gain of the bi-quad has a slight error 8WIL because the two effective resistances have a good match. As the conclusion of non-ideal SFG analysis indicated,the 2R 4R phenomenon ofnon-ideal OTA deteriorates the O-factor due to (a) the finite gain and bandwidth product(GBW).A high-O could cause a large ripple in the pass band ofthe filter which is not S3 desired.In high gain mode especially,the GBW is reduced due to heavy load.Noticing that the O-factor is actually the ratio of I w S2 two resistors that hardly vary,a reduced Ra at high gain mode 3L丁E could reduce the effective O,which in turn compensates for the degradation due to finite GBW.So the resistors are constructed I W 7L丁王 by segmented resistors in the array of Rd as shown in Fig.2. By shorting or connecting segmented resistors,the effective 5L丁 Ra could change according to the gain mode of the bi-quad. ·MM◆ The control code of this Q-tuning element comes from the gain R 2R 4R control code.So no additional decoding circuit is needed. (b) 3.2.Feed-forward OTA Fig.9.The match scheme for small gain error.(a)The traditional method.(b)The proposed method. OTA is the most important element in active RC filters.As explained before,an OTA with high gain,low noise and high are approximately expressed as linearity is needed.This is not only beneficial for improving IIP3 and gain accuracy,but also for lowering band ripple. Hor 1 (11) To reduce the total area of the filter,the use of extra ca- H01- pacitors such as Miller compensation capacitors and compen- OwpA(jo) sation capacitors for common mode feedback stability should be avoided in this design.A feed-forward OTA,which was in- 1 0 (12) troduced in Ref.[11],is applied.The schematic of this kind 1-2Ho0- of OTA is shown in Fig.10.Instead of pushing the dominant pA(j@) pole to a lower frequency,it creates a zero on the left plane It is shown that only if the gain ofOTA is large enough,can in the s domain,which is beneficial for the phase margin and the gain of the bi-quad be treated as the ratio of the resistors. high bandwidth at low power.Local common mode feedback is Thus,when the OTA has sufficient gain,the gain accuracy of completed using resistors as shown in the figure,and the OTA the bi-quad is decided only by the match between the two re- gain is limited by them.In Ref.[12],the low distortion benefit sistors.Figure 9(a)shows a traditional segmented resistor with of this feed-forward OTA was discussed in detail by simula- MOS transistors operating as switches.The MOS transistor can tion.In this part,the theoretical analysis of distortion will be be treated as a resistor when it operates in the linear region. discussed in detail.The Volterra series is used again here to Thus,the gain should be the ratio between two equivalent re- analyze the IIP3 of this OTA. sistances which include the output resistances of the transis- Figure 11 shows a differential pair of NMOS transistors. tors.For a fixed band,the value of equivalent Ra is constant. We use the model taking mobility degradation into account.id, 095007-5
J. Semicond. 2013, 34(9) Wang Xin et al. Fig. 8. The SFG of the bi-quad with a non-ideal integrator model. Fig. 9. The match scheme for small gain error. (a) The traditional method. (b) The proposed method. are approximately expressed as H0r H0 1 1 ! Q!pA .j!/ ; (11) Qr Q 1 1 2H0Q ! !pA .j!/ : (12) It is shown that only if the gain of OTA is large enough, can the gain of the bi-quad be treated as the ratio of the resistors. Thus, when the OTA has sufficient gain, the gain accuracy of the bi-quad is decided only by the match between the two resistors. Figure 9(a) shows a traditional segmented resistor with MOS transistors operating as switches. The MOS transistor can be treated as a resistor when it operates in the linear region. Thus, the gain should be the ratio between two equivalent resistances which include the output resistances of the transistors. For a fixed band, the value of equivalent Ra is constant. Fig. 10. Schematic of the feed-forward OTA. An accurate 6 dB gain step should be achieved if the value of the effective Rc also has a binary property. But in Fig. 9(a), no matter what sizes of transistors are used, it is impossible to realize a binary effective Rc because of non-symmetry. On the contrary, by adding an additional switch and properly sizing, which is shown in Fig. 9(b), an effective Rc could have a binary property. Thus, the gain of the bi-quad has a slight error because the two effective resistances have a good match. As the conclusion of non-ideal SFG analysis indicated, the phenomenon of non-ideal OTA deteriorates the Q-factor due to the finite gain and bandwidth product (GBW). A high-Q could cause a large ripple in the pass band of the filterŒ10, which is not desired. In high gain mode especially, the GBW is reduced due to heavy load. Noticing that the Q-factor is actually the ratio of two resistors that hardly vary, a reduced Rd at high gain mode could reduce the effective Q, which in turn compensates for the degradation due to finite GBW. So the resistors are constructed by segmented resistors in the array of Rd as shown in Fig. 2. By shorting or connecting segmented resistors, the effective Rd could change according to the gain mode of the bi-quad. The control code of this Q-tuning element comes from the gain control code. So no additional decoding circuit is needed. 3.2. Feed-forward OTA OTA is the most important element in active RC filters. As explained before, an OTA with high gain, low noise and high linearity is needed. This is not only beneficial for improving IIP3 and gain accuracy, but also for lowering band ripple. To reduce the total area of the filter, the use of extra capacitors such as Miller compensation capacitors and compensation capacitors for common mode feedback stability should be avoided in this design. A feed-forward OTA, which was introduced in Ref. [11], is applied. The schematic of this kind of OTA is shown in Fig. 10. Instead of pushing the dominant pole to a lower frequency, it creates a zero on the left plane in the s domain, which is beneficial for the phase margin and high bandwidth at low power. Local common mode feedback is completed using resistors as shown in the figure, and the OTA gain is limited by them. In Ref. [12], the low distortion benefit of this feed-forward OTA was discussed in detail by simulation. In this part, the theoretical analysis of distortion will be discussed in detail. The Volterra series is used again here to analyze the IIP3 of this OTA. Figure 11 shows a differential pair of NMOS transistors. We use the model taking mobility degradation into account. id, 095007-5
J.Semicond.2013,34(9) Wang Xin et al. Gem.3 =(gml,38m2.R1+g8m2.3R1+8m3,3)R2 is the third-order gain factor.IIP3 could expressed as 'cs-1/2w IP3≈ 4 Gem.1 13 Gemt,3 Fig.11.The differential gm unit. 4 gml,1gm2,1R1十gm3,1 √3gml,3gam2,1R1+g品，18m2,3R1+8m3,3 (16) For phase compensation,z is close to p2,which can be far m? away from the dominant pole pi.Assume 8ml,18m2,1R1+gm3,1=专gm3,1,5>1. Thus, 8ml.3 Vagm IIP3= Fig.12.The nonlinear model of OTA for distortion analysis. 1 3gml,35-1 8m2,35-1,1gm3,3 (17) the differential output current,could be expressed as 8ml,1专 +g品gm15 5gm3,1 It seems that if the zero is designed to compensate for the dom- k (vGSI -Uth)2 k (vGS2-Uth)2 inant pole,which will make equal to 1,then the distortion of ia=h-1h=1+9cs1-m-1+0(wGs2-w】 gmi and gm2 could be minimized.This is not practical because it will consume infinite power to make gm3 become infinite. (ov+ k(ow-》 But increasing gm3 without exceeding the power limit is good for reducing the distortion of gmi and gm2. 1+0(ov+罗)1+0(ov- There are three indications:(1)if p2 is far enough away from p1,then zero compensation for p2 is power economi- (13) cal.Distortion of the first stage is dominant in this case.(2) By Taylor expansion,id could be approximately expressed To lower the influence of second-stage distortion,gmi.1,which like is the linear transconductance of the first stage,should not be too large.(3)If pi and p2 are not far away,designing the cre- a≈k.2+6ou-1ke ated zero to be located between the dominant pole and the non- 40+9row号 dominant pole could compromise the power consumption and 1+0Vov distortion reduction of gmi and gm2,and this may make the dis- tortion of gm3 dominant. =gmlVin-gmV (14) From the previous analysis in this section,we have There is no second-order distortion because of balance appli- 8mj,3 cation.Figure 12 is the model for distortion analysis including 8mj,1 4Vv(2+9ov)1+9ov)31 (18) the nonlinear gm model ofeach stage.The relationship between input and output is So,the increase over the drive voltage is a direct way to reduce the distortion of each gm stage. + 3.3.Others vout≈Gem, +)+) The variation in on-chip resistors and capacitors are de- tected by an on-chip RC time constant detector,which is then calibrated by an auto-RC tuning engine to ensure an accurate (+) cutoff frequency that meets the application requirements.A tra- ditional analog DC feedback method is used to cancel the DC -Gef.3 (15) +)+) offset14).But to achieve a low high-pass corner frequency and minimize the area of capacitors required at the same time,a multiple DCOC loop strategy is adopted here.The feedback Where p1 1/R1C1,p2 1/R2C2,21 p1(1 network senses the DC voltage at the output of the bi-quad and gm1,18m2,1 R1/gm3,1),Z2 =p1(1+(gml,38m2,1R1+ then feeds back current to the resistors in the bi-quad.Thus,a gm1.18m2.3R1)/gm3.3),are the poles and zeros.Gem.1= voltage in the opposite phase is generated to cancel the input (gm1,18m2,1R1+gm3.1)R2 is the equivalent linear gain,and offset voltage 095007-6
J. Semicond. 2013, 34(9) Wang Xin et al. Fig. 11. The differential gm unit. Fig. 12. The nonlinear model of OTA for distortion analysis. the differential output current, could be expressed as id D I1 I2 D k .vGS1 vth/ 2 1 C .vGS1 vth/ k .vGS2 vth/ 2 1 C .vGS2 vth/ D k VOV C vin 2 2 1 C VOV C vin 2 k VOV vin 2 2 1 C VOV vin 2 : (13) By Taylor expansion, id could be approximately expressed like id kVov .2 C VOV/ 1 C VOV vin 1 4 k .1 C VOV/ 4 v 3 in D gm1vin gm3v 3 in: (14) There is no second-order distortion because of balance application. Figure 12 is the model for distortion analysis including the nonlinear gm model of each stage. The relationship between input and output is vout Gefft;1 1 C s z1 1 C s p1 1 C s p2 vin Gefft;3 1 C s z2 1 C s p1 1 C s p2 v 3 in; (15) where p1 D 1/R1C1, p2 D 1/R2C2, z1 D p1.1 C gm1; 1gm2; 1R1/gm3; 1/, z2 D p1(1C (gm1; 3gm2; 1R1 C g 3 m1; 1 gm2; 3R1//gm3; 3/, are the poles and zeros. Gefft; 1 D (gm1; 1gm2; 1R1 C gm3; 1/R2 is the equivalent linear gain, and Gefft; 3 D (gm1; 3gm2; 1R1 C g 3 m1; 1 gm2; 3R1 C gm3; 3/R2 is the third-order gain factor. IIP3 could expressed as IIP3 s 4 3 Gefft; 1 Gefft; 3 D s 4 3 gm1; 1gm2; 1R1 C gm3; 1 gm1; 3gm2; 1R1 C g 3 m1; 1 gm2; 3R1 C gm3; 3 : (16) For phase compensation, z1 is close to p2, which can be far away from the dominant pole p1. Assume gm1; 1gm2; 1R1 C gm3; 1 D gm3; 1; > 1: Thus, IIP3 D vuuut 4 3 1 gm1; 3 gm1; 1 1 C g 2 m1;1 gm2; 3 gm2; 1 1 C 1 gm3; 3 gm3; 1 : (17) It seems that if the zero is designed to compensate for the dominant pole, which will make equal to 1, then the distortion of gm1 and gm2 could be minimized. This is not practical because it will consume infinite power to make gm3 become infinite. But increasing gm3 without exceeding the power limit is good for reducing the distortion of gm1 and gm2. There are three indications: (1) if p2 is far enough away from p1, then zero compensation for p2 is power economical. Distortion of the first stage is dominant in this case. (2) To lower the influence of second-stage distortion, gm1;1, which is the linear transconductance of the first stage, should not be too large. (3) If p1 and p2 are not far away, designing the created zero to be located between the dominant pole and the nondominant pole could compromise the power consumption and distortion reduction of gm1 and gm2, and this may make the distortion of gm3 dominant. From the previous analysis in this section, we have gmj; 3 gmj; 1 D 4Vov .2 C VOV/ .1 C VOV/ 3 : (18) So, the increase over the drive voltage is a direct way to reduce the distortion of each gm stage. 3.3. Others The variation in on-chip resistors and capacitors are detected by an on-chip RC time constant detector, which is then calibrated by an auto-RC tuning engine to ensure an accurate cutoff frequency that meets the application requirements. A traditional analog DC feedback method is used to cancel the DC offsetŒ14. But to achieve a low high-pass corner frequency and minimize the area of capacitors required at the same time, a multiple DCOC loop strategy is adopted here. The feedback network senses the DC voltage at the output of the bi-quad and then feeds back current to the resistors in the bi-quad. Thus, a voltage in the opposite phase is generated to cancel the input offset voltage. 095007-6
J.Semicond.2013,34(9) Wang Xin et al. Hkr31.7853M2 Ref 11 dBm Atten 30 dB 60 (a) -63149a3m amp Marker☐ 0.d 1.705300MHz 40 dB/ -63.149dBm DC Couple 20 .gAv -20 Center 2.000 0 MHz 500n800H2 Res BH 7.5 kHz VBW 7.5 kHz Sweep 54.24 ms (601 pts) -40 28981MH 8.30d8 -60 3 45678910 (a) Frequency(MHz) (dB) 40 0.8 IIP3=31.27 (b) 0.6053(3.36%) 20 0.6 0.4 30 0.2 40 0 GI G3 G4 G5 G6 G7 G8 G9 G10 -60 米丝米米 -0.2 -80 -0.4 -100 10 10 20 30 Fig.15.The gain step test.(a)Gain range and magnified ripple detail, 40 and (b)gain error Input power(dBm) (b) Fig.13.In-band IIP3 test.(a)In-band two-tone test.(b)Extrapolated Table 1.Performance summary IIP3. Parameter Value Technology 0.18 um CMOS Die area 1×1.28mm2 10 Power consumption @1.8V 12.6mW 54 dB/6 dB 0 Gain range/Gain step Resistor tuning Bandwidth tuning range 0.250-4MHz 10 Gain error 31 dBm -60 arrays.The frequency tuning range is from 0.25 to 4 MHz.By comparing the-3 dB point with designed cutoff frequency,the -70 3 3 4 56789 10 automatic tuning accuracy could be evaluated.Data from the Frequency (MHz) traces shows that a frequency tuning error ofless than 5%could be reached. Fig.14.The band selection of the filter. Figure 15(a)shows the gain range,which could vary from 0 to 54 dB.The attenuation at 1.315 times the cutoff frequency 4.Test results and stop band could reach 35 dB and 60 dB,respectively.To show the details of the ripples,the frequency response traces, Figure 13(a)illustrates the two-tone test result when the posted in the upper right of Fig.15(a),are magnified and nor- gain is set at 0 dB.The in-band IIP3 is 31.27 dBm for 1.9 MHz malized by subtracting the average gain ofeach gain mode.All and 2.1 MHz tones.Figure 13(b)is the extrapolated IIP3 graph the normalized traces meet together at high frequency in the from different input and output test results. graph,which indicates that this normalization method is right Figure 14 shows the band-selection function of this filter. because gain error is excluded.It is shown that the biggest rip- The four dark traces are the bands selected by switching resis- ple is less than 1.4 dB.In Fig.15(b),the gain errors ofeach gain tors,while the blue traces are the bands tuned using capacitor mode are shown.The most significant one has a difference of 095007-7
J. Semicond. 2013, 34(9) Wang Xin et al. Fig. 13. In-band IIP3 test. (a) In-band two-tone test. (b) Extrapolated IIP3. Fig. 14. The band selection of the filter. 4. Test results Figure 13(a) illustrates the two-tone test result when the gain is set at 0 dB. The in-band IIP3 is 31.27 dBm for 1.9 MHz and 2.1 MHz tones. Figure 13(b) is the extrapolated IIP3 graph from different input and output test results. Figure 14 shows the band-selection function of this filter. The four dark traces are the bands selected by switching resistors, while the blue traces are the bands tuned using capacitor Fig. 15. The gain step test. (a) Gain range and magnified ripple detail, and (b) gain error. Table 1. Performance summary. Parameter Value Technology 0.18 m CMOS Die area 1 1.28 mm2 Power consumption @1.8V 12.6 mW Gain range/Gain step 54 dB/6 dB Bandwidth tuning range 0.250–4 MHz Gain error 31 dBm arrays. The frequency tuning range is from 0.25 to 4 MHz. By comparing the –3 dB point with designed cutoff frequency, the automatic tuning accuracy could be evaluated. Data from the traces shows that a frequency tuning error of less than 5% could be reached. Figure 15(a) shows the gain range, which could vary from 0 to 54 dB. The attenuation at 1.315 times the cutoff frequency and stop band could reach 35 dB and 60 dB, respectively. To show the details of the ripples, the frequency response traces, posted in the upper right of Fig. 15(a), are magnified and normalized by subtracting the average gain of each gain mode. All the normalized traces meet together at high frequency in the graph, which indicates that this normalization method is right because gain error is excluded. It is shown that the biggest ripple is less than 1.4 dB. In Fig. 15(b), the gain errors of each gain mode are shown. The most significant one has a difference of 095007-7
J.Semicond.2013,34(9) Wang Xin et al. Table 2.Comparison to recently published work Process Type Order Vad (V) Power/Pole fcut-off IIP3 Gain Ripple Continuously DCOC (nm) (mW/Pole) range (dBm) (dB) (dB) tuning Included (MHz) Ref.[4] 130 B/C 1.2 1.36 0.28-3 29 0-18 Yes Yes Ref.[10] 130 C/I 1/3/5 0.6-1.5 1-5 31.3 0 Yes No Ref.[12] 180 Elliptic 3 1.8 0.6 8.5 30.8 0 2.2 No No This work 180 Elliptic 6 1.8 1.05 0.25-4 31.27 0-54 1.4 Yes Yes B indicates Butterworth,while C and I indicate Chebyshev and Inverse-Chebyshev,respectively.The topologies used in these papers are all active-RC.IIP3 is the in-band IIP3. 1000um Acknowledgment The authors would like to thank Zhuo Chenfei for discus- sions,and Huang Qiuzhen and Liu Yuyan for help with the DCec Q Path testing.The authors are indebted to Agilent Opening Lab for the chip test. References PGA CSF 1280 [1]Namgoong W,Meng T H.Direct-conversion RF receiver design. IEEE Trans Commun,2001,49:518 I Path [2]Chang J H,Kim H,Choi J H,et al.A multistandard multiband DCec mobile TV RF SoC in 65 nm CMOS.IEEE ISSCC Dig of Tec Papers..2010:462 [3]Antoine P,Bauser P,Beaulaton H,et al.A direct-conversion re- ceiver for DVB-H.IEEE J Solid-State Circuits,2005,40(12): 2536 Fig.16.The die photo [4]Wang W,Chang X,Wang X,et al.A 4th-order reconfigurable analog baseband filter for software-defined radio applications. 0.6053 dB with the designed value,which means that the gain Journal of Semiconductors,2011,32(4):045008 [5]Zou L,Liao Y,Tang Z.An eighth order channel selection filter error is less than 3.4%.The performance of this filter,including for low-IF and zero-IF DVB tuner applications.Journal of Semi- the DCOC and auto-RC tuning circuit,is summarized in detail conductors.2009,30(11):115002 in Table 1.A comparison to recently published work is shown [6]Wambacq P,Sansen W M C.Distortion analysis of analog inte- in Table 2.The proposed filter with a steeper transient band grated circuits.Springer,1998 or better band selection due to higher order has high linearity [7]Palaskas Y,Tsividis Y.Dynamic range optimization of weakly performance,which is comparable to the best results listed in nonlinear,fully balanced,Gm-C filters with power dissipation Table 2:multi-band selection with continuous frequency tun- constraints.IEEE Trans Circuits Syst II:Analog and Digital Sig- ing,wide gain range with small gain error,and small in-band nal Processing,2003,50(10):714 ripple.Figure 16 is the die photo.The channel-select filter has [8]Meghdadi M.Bakhtiar M S.Analysis and optimization of SFDR I and Q paths in differential active-RC filters.IEEE Trans Circuits Syst I:Reg- ular Papers,2012,59(6):1168 [9]Schaumann R,the late Valkenburg M E V.Design of analog fil- 5.Conclusion ters.Oxford University Press,USA.2001 [10]Amir-Aslanzadeh H,Pankratz E J,Sanchez-Sinencio E.A 1- This paper develops a bi-quad IIP3 optimization procedure V+31 dBm IIP3,reconfigurable,continuously tunable,power- by normalizing passive element parameters to a reference re- adjustable active-RC LPF.IEEE J Solid-State Circuits,2009, sistor.Detailed theoretical analysis can be used in the design 44(2):495 of this particular channel-select filter,and other kinds of filter [11]Harrison J,Weste N.A 500 MHz CMOS anti-alias filter using as well.The gain error control method and frequency tuning feed-forward op-amps with local common-mode feedback.IEEE scheme are also presented.To overcome in-band ripples orig- ISSCC Dig Tec Papers,2003:132 inating from the degradation of the effective O-factor,a seg- [12]Krishnapura N,Agrawal A,Singh S.A High-IIP3 third-order elliptic filter with current-efficient feedforward-compensated mented resistor technique is introduced.Test results show that opamps.IEEE Trans Circuits Syst II:Express Briefs,2011,58(4): the filter,which is suitable for TV-tuner application,has more 205 than 31 dBm in-band IIP3 at a low gain mode and 54 dB gain [13]Mak P I,Seng-Pan U,Martins R P.On the design of a range with a gain error of less than 3.4%.The frequency tuning programmable-gain amplifier with built-in compact DC-offset range covers signal bands of all the applications from 0.25 to cancellers for very low-voltage WLAN systems.IEEE Trans Cir- 4 MHz with a frequency tuning error of no more than 5%. cuits Syst I:Regular Papers,2008,55(2):496 095007-8
J. Semicond. 2013, 34(9) Wang Xin et al. Table 2. Comparison to recently published work. Process (nm) Type Order Vdd (V) Power/Pole (mW/Pole) fcut-off range (MHz) IIP3 (dBm) Gain (dB) Ripple (dB) Continuously tuning DCOC Included Ref. [4] 130 B/C 4 1.2 1.36 0.28–3 29 0–18 — Yes Yes Ref. [10] 130 C/I 1/3/5 1 0.6–1.5 1–5 31.3 0 — Yes No Ref. [12] 180 Elliptic 3 1.8 0.6 8.5 30.8 0 2.2 No No This work 180 Elliptic 6 1.8 1.05 0.25–4 31.27 0–54 1.4 Yes Yes B indicates Butterworth, while C and I indicate Chebyshev and Inverse-Chebyshev, respectively. The topologies used in these papers are all active-RC. IIP3 is the in-band IIP3. Fig. 16. The die photo. 0.6053 dB with the designed value, which means that the gain error is less than 3.4%. The performance of this filter, including the DCOC and auto-RC tuning circuit, is summarized in detail in Table 1. A comparison to recently published work is shown in Table 2. The proposed filter with a steeper transient band or better band selection due to higher order has high linearity performance, which is comparable to the best results listed in Table 2: multi-band selection with continuous frequency tuning, wide gain range with small gain error, and small in-band ripple. Figure 16 is the die photo. The channel-select filter has I and Q paths. 5. Conclusion This paper develops a bi-quad IIP3 optimization procedure by normalizing passive element parameters to a reference resistor. Detailed theoretical analysis can be used in the design of this particular channel-select filter, and other kinds of filter as well. The gain error control method and frequency tuning scheme are also presented. To overcome in-band ripples originating from the degradation of the effective Q-factor, a segmented resistor technique is introduced. Test results show that the filter, which is suitable for TV-tuner application, has more than 31 dBm in-band IIP3 at a low gain mode and 54 dB gain range with a gain error of less than 3.4%. The frequency tuning range covers signal bands of all the applications from 0.25 to 4 MHz with a frequency tuning error of no more than 5%. Acknowledgment The authors would like to thank Zhuo Chenfei for discussions, and Huang Qiuzhen and Liu Yuyan for help with the testing. The authors are indebted to Agilent Opening Lab for the chip test. References [1] Namgoong W, Meng T H. Direct-conversion RF receiver design. IEEE Trans Commun, 2001, 49: 518 [2] Chang J H, Kim H, Choi J H, et al. A multistandard multiband mobile TV RF SoC in 65 nm CMOS. IEEE ISSCC Dig of Tec Papers, 2010: 462 [3] Antoine P, Bauser P, Beaulaton H, et al. A direct-conversion receiver for DVB-H. IEEE J Solid-State Circuits, 2005, 40(12): 2536 [4] Wang W, Chang X, Wang X, et al. A 4th-order reconfigurable analog baseband filter for software-defined radio applications. Journal of Semiconductors, 2011, 32(4): 045008 [5] Zou L, Liao Y, Tang Z. An eighth order channel selection filter for low-IF and zero-IF DVB tuner applications. Journal of Semiconductors, 2009, 30(11): 115002 [6] Wambacq P, Sansen W M C. Distortion analysis of analog integrated circuits. Springer, 1998 [7] Palaskas Y, Tsividis Y. Dynamic range optimization of weakly nonlinear, fully balanced, Gm–C filters with power dissipation constraints. IEEE Trans Circuits Syst II: Analog and Digital Signal Processing, 2003, 50(10): 714 [8] Meghdadi M, Bakhtiar M S. Analysis and optimization of SFDR in differential active-RC filters. IEEE Trans Circuits Syst I: Regular Papers, 2012, 59(6): 1168 [9] Schaumann R, the late Valkenburg M E V. Design of analog filters. Oxford University Press, USA, 2001 [10] Amir-Aslanzadeh H, Pankratz E J, Sanchez-Sinencio E. A 1- V +31 dBm IIP3, reconfigurable, continuously tunable, poweradjustable active-RC LPF. IEEE J Solid-State Circuits, 2009, 44(2): 495 [11] Harrison J, Weste N. A 500 MHz CMOS anti-alias filter using feed-forward op-amps with local common-mode feedback. IEEE ISSCC Dig Tec Papers, 2003: 132 [12] Krishnapura N, Agrawal A, Singh S. A High-IIP3 third-order elliptic filter with current-efficient feedforward-compensated opamps. IEEE Trans Circuits Syst II: Express Briefs, 2011, 58(4): 205 [13] Mak P I, Seng-Pan U, Martins R P. On the design of a programmable-gain amplifier with built-in compact DC-offset cancellers for very low-voltage WLAN systems. IEEE Trans Circuits Syst I: Regular Papers, 2008, 55(2): 496 095007-8
