3-2 IEEE Asian Solid-State Circuits Conference November 12-14.2007/Jeju,Korea A CMOS Wide-Band Low-Noise Amplifier With Balun-Based Noise-Canceling Technique Youchun Liao,Zhangwen Tang*and Hao Min ASIC System State Key Laboratory,Fudan University NO.825 Zhangheng Rd.,Shanghai,201203 China Abstract-A differential high linearity low-noise amplifier (LNA)based on a capacitor-cross-coupled topology is presented RF Front-ended in this paper.An off-chip balun is used for providing DC-bias UpMixer and canceling the channel thermal noise of the transconductance MOS transistors.The LNA uses NMOS load and provides an extra signal feed-forward and noise-canceling path.Analysis shows that the noise contribution of the transconductance MOST Band Limit Balun LNA is only yy/20 and the noise figure (NF)of the proposed LNA is 1+0.2.The chip is implemented in a 0.18-um MMRF CMOS process.Measured results show that in 50M-860MHz frequency range,the LNA achieved 15 dB gain,2.5 dB NF,8.3 dBm IIP3 and consumes only 4 mA current from a 1.8-V supply. I.INTRODUCTION Fig.1.A DZIF tuner architecture. The world-wide spread of high-definition digital television (HDTV)promotes the research of the RF tuners and their building blocks.Among all the DTV standards,the Digital This paper is organized as follows:the balun+LNA topology Video Broadcasting for Cable (DVB-C,50M-860MHz)is and the balun-based noise-canceling technique are introduced regarded as the most difficult one for single-chip integration in Section II.The balun impedance analysis and NF calcu- because of its low center-frequency and high bandwidth-to- lation are given in Section III.The chip implementation and center-frequency ratio (BW/fe). measurement results are given in Section IV,and Section V The low-noise amplifier (LNA)design is a challenge in concludes this work. CMOS tuners.Besides the basic requirements on gain and II.CCC LNA WITH OFF-CHIP BALUN noise figure (NF),it needs to be fully differential to obtain high common-mode restrain ratio (CMRR)and high even- A traditional wide-band CCC common-gate (CG)LNA is order harmonic restrain ability (IIP2).The fully differential shown in Fig.2.The differential signal from the off-chip capacitor-cross-coupled (CCC)topology [1]is a good candi- balun is AC-coupled to the source of the transconductance date for its high linearity and low power dissipation.However, MOS transistors,and then cross-coupled to the gate of the it suffers from high NF.The LNA exploiting a noise-canceling opposite MOSTs through coupling capacitor C1.2.therefore technique [2]achieves very low NF over wide frequency band the effective transconductor is doubled without consuming but consumes too much power,e.g.,for a differential topology, extra current.The source resistor Rs1.2 (or current mirror) the total current is greater than 20 mA [3]. provides the DC-bias.Only considering the channel thermal Fig.1 shows a double-conversion low-IF (DLIF)DVB-C noise of the transconductance MOSTs and assuming input tuner RF architecture.An off-chip balun is used to transform impedance is matched,the minimum NF of this LNA is [1] the single-ended signal received by the antenna to balanced F=1+Y/2 (1) one for the differential-input LNA.In the traditional LNA design,the balun is AC-coupled to the tuner chip and acts Comparing to the basic CG topology without C1.2 whose only as a single-ended to differential(S-D)transformer.In this NF is 1+,the noise contribution of M.2 is half reduced. paper,the balun and the LNA are DC-coupled,and a balun- This can be explained in the noise-canceling point of view: based noise-canceling technique is proposed.Analysis shows The channel thermal noise in flows through the small signal that the proposed balun+LNA topology achieves the lowest impedance at OP and IP,causes two noise voltagen and NF in all published CCC LNAs,and maintains the inherent Un.ip with opposite sign.Then Un.ip is coupled to the gate of advantage of high linearity and low power. M2 by C1-R and amplified by the CS stage M2 to vn.on.The inphase noise vn.n and vn.p reduced the output differential Corresponding author.Email:zwtang@fudan.edu.cn. mode noise voltage and thus reduced the NF.However,the 1-4244-1360-5/07/s25.00©20071EEE 91
A CMOS Wide-Band Low-Noise Amplifier With Balun-Based Noise-Canceling Technique Youchun Liao, Zhangwen Tang* and Hao Min ASIC & System State Key Laboratory, Fudan University NO. 825 Zhangheng Rd., Shanghai, 201203 China Abstract— A differential high linearity low-noise amplifier (LNA) based on a capacitor-cross-coupled topology is presented in this paper. An off-chip balun is used for providing DC-bias and canceling the channel thermal noise of the transconductance MOS transistors. The LNA uses NMOS load and provides an extra signal feed-forward and noise-canceling path. Analysis shows that the noise contribution of the transconductance MOST is only γ/20 and the noise figure (NF) of the proposed LNA is 1+0.2γ. The chip is implemented in a 0.18-μm MMRF CMOS process. Measured results show that in 50M-860MHz frequency range, the LNA achieved 15 dB gain, 2.5 dB NF, 8.3 dBm IIP3 and consumes only 4 mA current from a 1.8-V supply. I. INTRODUCTION The world-wide spread of high-definition digital television (HDTV) promotes the research of the RF tuners and their building blocks. Among all the DTV standards, the Digital Video Broadcasting for Cable (DVB-C, 50M-860MHz) is regarded as the most difficult one for single-chip integration because of its low center-frequency and high bandwidth-tocenter-frequency ratio (BW/fc). The low-noise amplifier (LNA) design is a challenge in CMOS tuners. Besides the basic requirements on gain and noise figure (NF), it needs to be fully differential to obtain high common-mode restrain ratio (CMRR) and high evenorder harmonic restrain ability (IIP2). The fully differential capacitor-cross-coupled (CCC) topology [1] is a good candidate for its high linearity and low power dissipation. However, it suffers from high NF. The LNA exploiting a noise-canceling technique [2] achieves very low NF over wide frequency band but consumes too much power, e.g., for a differential topology, the total current is greater than 20 mA [3]. Fig. 1 shows a double-conversion low-IF (DLIF) DVB-C tuner RF architecture. An off-chip balun is used to transform the single-ended signal received by the antenna to balanced one for the differential-input LNA. In the traditional LNA design, the balun is AC-coupled to the tuner chip and acts only as a single-ended to differential (S-D) transformer. In this paper, the balun and the LNA are DC-coupled, and a balunbased noise-canceling technique is proposed. Analysis shows that the proposed balun+LNA topology achieves the lowest NF in all published CCC LNAs, and maintains the inherent advantage of high linearity and low power. * Corresponding author. Email: zwtang@fudan.edu.cn. PLL Band Limit Filter LNA 75ȍ UpMixer DnMixer 1st LO I Q RF Front-ended Balun 2nd LO Fig. 1. A DZIF tuner architecture. This paper is organized as follows: the balun+LNA topology and the balun-based noise-canceling technique are introduced in Section II. The balun impedance analysis and NF calculation are given in Section III. The chip implementation and measurement results are given in Section IV, and Section V concludes this work. II. CCC LNA WITH OFF-CHIP BALUN A traditional wide-band CCC common-gate (CG) LNA is shown in Fig. 2. The differential signal from the off-chip balun is AC-coupled to the source of the transconductance MOS transistors, and then cross-coupled to the gate of the opposite MOSTs through coupling capacitor C1,2, therefore the effective transconductor is doubled without consuming extra current. The source resistor RS1,2 (or current mirror) provides the DC-bias. Only considering the channel thermal noise of the transconductance MOSTs and assuming input impedance is matched, the minimum NF of this LNA is [1] F =1+ γ/2 (1) Comparing to the basic CG topology without C1,2 whose NF is 1 + γ, the noise contribution of M1,2 is half reduced. This can be explained in the noise-canceling point of view: The channel thermal noise in flows through the small signal impedance at OP and IP, causes two noise voltage vn,op and vn,ip with opposite sign. Then vn,ip is coupled to the gate of M2 by C1-R1 and amplified by the CS stage M2 to vn,on. The inphase noise vn,on and vn,op reduced the output differential mode noise voltage and thus reduced the NF. However, the IEEE Asian Solid-State Circuits Conference 1-4244-1360-5/07/$25.00 2007 IEEE November 12-14, 2007 / Jeju, Korea 3-2 91
R,z .0000车000 Q00022w Off-Chip Fig.2.Traditional CCC LNA. Fig.3.Proposed LNA schematic actual NF of Fig.2 is still higher than 3 dB for a typical 4kTyl9m⊙ M' 4/3 because of the noise contribution of Rs1.2 and RL1.2.The 之12gm other drawback is that Rs1.2 reduced the voltage headroom and therefore reduced the linearity. v生年v M A DC-coupled balun+LNA topology is proposed to over- 2y. -0000200— come these problems,as shown in Fig.3.The two balanced ports of a transformer-type balun are directly connected to the source of M and M2 respectively,with the center-tapped port grounded providing DC-bias for the LNA.The first advantage (a) of this topology is that the source resistor Rs1.2 and the off- chip AC-coupled capacitors can be removed,while the S-D transform function still remains.The load resistor RL1.2 is 4kT/9-包 12g replaced by NMOST M3.4 for two reasons:1)The linearity can be improved due to a"post-correction"approach [4]:2) NMOS loading with extra AC paths Ca-Ra and Ca-Ra can improve the voltage gain and provide an extra noise-canceling Q00000①-①Hl: 2v joL path [5].From Fig.3,it can be shown that there are now three noise-canceling paths(in dot lines)which are: 1)The CCC path C1-R1 and CS stage M2.Un.ip is AC- coupled to the gate of M2 by C1-R1,and then amplified to (b) Un.on by CS stage M2. 2)The balanced ports of the balun and CG stage M2.Unp is Fig.4.A 1:1 balun model.(a)Original model.(b)De-coupled equivalent transformer-coupled to vn.in by the balun,and then amplified circuit. to Un,on by CG stage M2. 3)The extra feed-forward path Ca-Ra and source follow stage M3.Un.ip is AC-coupled to the gate of M3 by C3-R3. The voltage gain is and then followed toby source follow stage M3. Av =1+2gm1/gm3 (3) With these noise-canceling paths,the output differential- mode noise of Mi.2 is remarkable reduced,therefore the NF where the term "1"comes from the feed-forward paths C3- can be very low. R3-M3 and C4-R4-M4. In order to calculate the noise contribution of M.the balun III.PARAMETER CALCULATION impedance characteristic should be analyzed firstly. In this design,we choose a balun with the impedance ratio A.Balun Model 1:1.The differential input impedance of the LNA is 1/gm,so the input impedance matching condition is When the noise voltage of Mi adds to one of the balanced ports,the balun model can be shown in Fig.4(a).For the 1:1 9m=1/Rs (2)balun,the coil ratio is 2:1 and three inductors LL satisfy 92
RL1 Vdd RL2 Vb M1 M2 C1 C2 RS1 RS2 RS S v Off-Chip ni R2 R1 IP IN RFin RFout OP ON n op , v n ip, v n on , v Fig. 2. Traditional CCC LNA. R3 Vdd R4 Vb M1 M2 C1 C2 RS S v Off-Chip C3 C4 R2 R1 M3 M4 n i RFin n op , v n ip, v RFout n on , v n in, v Fig. 3. Proposed LNA schematic. actual NF of Fig. 2 is still higher than 3 dB for a typical γ = 4/3 because of the noise contribution of RS1,2 and RL1,2. The other drawback is that RS1,2 reduced the voltage headroom and therefore reduced the linearity. A DC-coupled balun+LNA topology is proposed to overcome these problems, as shown in Fig. 3. The two balanced ports of a transformer-type balun are directly connected to the source of M1 and M2 respectively, with the center-tapped port grounded providing DC-bias for the LNA. The first advantage of this topology is that the source resistor RS1,2 and the offchip AC-coupled capacitors can be removed, while the S-D transform function still remains. The load resistor RL1,2 is replaced by NMOST M3,4 for two reasons: 1) The linearity can be improved due to a “post-correction” approach [4]; 2) NMOS loading with extra AC paths C3-R3 and C4-R4 can improve the voltage gain and provide an extra noise-canceling path [5]. From Fig. 3, it can be shown that there are now three noise-canceling paths (in dot lines) which are: 1) The CCC path C1-R1 and CS stage M2. vn,ip is ACcoupled to the gate of M2 by C1-R1, and then amplified to vn,on by CS stage M2. 2) The balanced ports of the balun and CG stage M2. vn,ip is transformer-coupled to vn,in by the balun, and then amplified to vn,on by CG stage M2. 3) The extra feed-forward path C3-R3 and source follow stage M3. vn,ip is AC-coupled to the gate of M3 by C3-R3, and then followed to vn,op by source follow stage M3. With these noise-canceling paths, the output differentialmode noise of M1,2 is remarkable reduced, therefore the NF can be very low. III. PARAMETER CALCULATION In this design, we choose a balun with the impedance ratio 1:1. The differential input impedance of the LNA is 1/gm, so the input impedance matching condition is gm = 1/RS (2) RS 2:1 2:1 Rip v 2v v 1/ 2gm Rin L1 L2 L3 M M M ' 4 m1 kT g J (a) 1 i 2i 3 i 1 j LZ 2v v v 2 j Mi Z 3 j Mi Z 2 j LZ 3 1 j LZ j Mi Z 1 jZM i' 3 jZM i' 2 j Mi Z RS Rip 1/ 2gm Rin 4 m1 kT g J (b) Fig. 4. A 1:1 balun model. (a) Original model. (b) De-coupled equivalent circuit. The voltage gain is AV =1+2gm1/gm3 (3) where the term “1” comes from the feed-forward paths C3- R3-M3 and C4-R4-M4. In order to calculate the noise contribution of M1, the balun impedance characteristic should be analyzed firstly. A. Balun Model When the noise voltage of M1 adds to one of the balanced ports, the balun model can be shown in Fig. 4(a). For the 1:1 balun, the coil ratio is 2:1 and three inductors L1∼L3 satisfy 92
IDC VDD VSS gmsv-Vnep m(-V-Vna gm(-2v) ge(2) Rd6 v Fig.5.Small signal circuit for NF calculation. LI=4L2 =4L3.Then the voltage ratio of three ports is 2v:v:(-v).Under conservation of energy it has -2u2+-2 Fig.6.Microphotograph of the chip. Rip Rs129m (4) So that 20 1 Rs Rip=4/Rs +2gm 6 (5) 10 Gain Assuming L~L3 are fully coupled,ie.,coupling coeffi- 5 cient of each two inductors is k 1.The mutual inductance 0 小…小…小小…小小小小 of which are M VL1L2 VL1L3 2L2 and M'= -5 VL2L3=L2.We can obtain the de-coupled balun model in g-10 Fig.4(b),and three current loop formulas are -15 jwLiin jwMi2-jwMis=2v -20 S11 jwMin jwLi2-jwM'is =v (6) -25 -jwMin-jwM'i2+jwL3i3=-v -30 -30 Substituting i1 =-2v/Rs and assuming LI~L3 to be infinite -4 (comparing with Rs)yields 50 250 450 800 860 Frequency(MHz) i2 -i3=4v/Rs (7) Fig.7.Measured gain and S11 From (5)and (7)it can be calculated that Rin =-v/i3=-Rs/2 (8) IV.CHIP IMPLEMENTATION AND MEASUREMENT B.NF Calculation The LNA chip is implemented in a 0.18-um,1P6M MMRF From the small signal circuit as shown in Fig.5,the noise CMOS process,the chip microphotograph is shown in Fig. contribution of M.2 can be calculated as 6.The MIM capacitor is available for coupling capacitors (Rs 1 2 C~C.The core size of the LNA is 0.25 x 0.3mm2 and 2M1,2=(n,op-n,om)2= 4-2gm3 4kTygm1 (9)the total chip size including the PADs and ESD MOSTs is 0.52 x 0.54mm2.The chip consumes only 4 mA current from And the noise contribution of M3.4 is a 1.8-V supply. 2.wa4=4kT/9m3 (10) The differential outputs are both directly connected and after an open drain NMOS pairs for measurement purpose. So the NF of the total circuit is The former are combined to single-ended by an off-chip 1:4 F=1+ 2·哈M1,2+2·v2Md balun for NF and linearity measurement while the latter are (11) A·4kTRs connected to two 50 n resistors and combined to a 1:2 balun Considering the input impedance matching condition (2),and for gain measurement. substituting 9m3 =gm1/2 for 14 dB gain,the NF is The measured gain has a flat value of 15 dB and the S11 (referred to 75 characteristic impedance)is below-24 dB 9 4 Fmn=1+200Y+25Y≈1+0.2n (12) during the 50M-860MHz frequency range,as shown in Fig. 7.The simulated and measured NFs are shown in Fig.8. It can be seen that the noise contribution of the transcon- The measured NF is 2.2~2.9 dB with an average value 2.5 ductance MOST M12 is less than /20 and is no longer the dB,which is very close to the simulated value 2.3 dB.The dominant noise source.Fory=4/3.the minimum NF is measured input-referred third-order intercept point (IIP3)is about 1 dB. shown in Fig.9 with a value of 8.3 dBm at two-tone frequency 93
v v ni gm3(v-vn,op) gm4(-v-vn,on) gm1(-2v) gm2(2v) vn,op vn,on RS/6 -RS/2 Fig. 5. Small signal circuit for NF calculation. L1 = 4L2 = 4L3. Then the voltage ratio of three ports is 2v : v : (−v). Under conservation of energy it has v2 Rip = (2v)2 RS + (−v)2 1/2gm (4) So that Rip = 1 4/RS + 2gm = RS 6 (5) Assuming L1∼L3 are fully coupled, i.e., coupling coeffi- cient of each two inductors is k = 1. The mutual inductance of which are M = √L1L2 = √L1L3 = 2L2 and M = √L2L3 = L2. We can obtain the de-coupled balun model in Fig. 4(b), and three current loop formulas are ⎧ ⎨ ⎩ jωL1i1 + jωMi2 − jωMi3 = 2v jωMi1 + jωL2i2 − jωM i3 = v −jωMi1 − jωM i2 + jωL3i3 = −v (6) Substituting i1 = −2v/RS and assuming L1∼L3 to be infinite (comparing with RS) yields i2 − i3 = 4v/RS (7) From (5) and (7) it can be calculated that Rin = −v/i3 = −RS/2 (8) B. NF Calculation From the small signal circuit as shown in Fig. 5, the noise contribution of M1,2 can be calculated as v2 n,M1,2 = (vn,op−vn,on) 2 = RS 4 − 1 2gm3 2 4kT γgm1 (9) And the noise contribution of M3,4 is v2 n,M3,4 = 4kT γ/gm3 (10) So the NF of the total circuit is F =1+ 2 · v2 n,M1,2 + 2 · v2 n,M3,4 A2 V · 4kTRS (11) Considering the input impedance matching condition (2), and substituting gm3 = gm1/2 for 14 dB gain, the NF is Fmin =1+ 9 200γ + 4 25γ ≈ 1+0.2γ (12) It can be seen that the noise contribution of the transconductance MOST M1,2 is less than γ/20 and is no longer the dominant noise source. For γ = 4/3, the minimum NF is about 1 dB. IP IN OP ON IDC VDD VSS Opendrain buffer Fig. 6. Microphotograph of the chip. 50 250 450 800 860 −40 −30 −30 −25 −20 −15 −10 −5 0 5 10 15 20 Frequency(MHz) dB Gain S11 Fig. 7. Measured gain and S11. IV. CHIP IMPLEMENTATION AND MEASUREMENT The LNA chip is implemented in a 0.18-μm, 1P6M MMRF CMOS process, the chip microphotograph is shown in Fig. 6. The MIM capacitor is available for coupling capacitors C1∼C4. The core size of the LNA is 0.25 × 0.3mm2 and the total chip size including the PADs and ESD MOSTs is 0.52 × 0.54mm2. The chip consumes only 4 mA current from a 1.8-V supply. The differential outputs are both directly connected and after an open drain NMOS pairs for measurement purpose. The former are combined to single-ended by an off-chip 1:4 balun for NF and linearity measurement while the latter are connected to two 50 Ω resistors and combined to a 1:2 balun for gain measurement. The measured gain has a flat value of 15 dB and the S11 (referred to 75 Ω characteristic impedance) is below -24 dB during the 50M-860MHz frequency range, as shown in Fig. 7. The simulated and measured NFs are shown in Fig. 8. The measured NF is 2.2∼2.9 dB with an average value 2.5 dB, which is very close to the simulated value 2.3 dB. The measured input-referred third-order intercept point (IIP3) is shown in Fig. 9 with a value of 8.3 dBm at two-tone frequency 93
20 0 20 40 60 6 ◆-Simulated 1.5 80 -Measured IIP3=8.3dBm .100 250 450 650 860 -20 -10 10 Frequency(MHz) Input power(dBm) Fig.8.Simulated and measured NF. Fig.9.Measured IIP3. TABLE I SUMMARY OF MEASUREMENT RESULTS AND PERFORMANCE COMPARISON [3) [8I 9 This Work CMOS Process 0.12-4m 0.18-m 0.18-4m 0.18-4m 0.18-4m Frequency 48-862MHz 470-860MHz 470-870MHz 1.2-11.9GHz 50-860MHz Gain 17dB 10dB 16dB 9.7dB 15dB S11 NIA NIA -11dB -11dB -24dB NF 3dB 5.7dB 4.3dB 4.8dB 2.5dB IIP3 5.5dBm 10dBm -1.5dBm -6.2dBm 8.3dBm Power 23mA×2.5V 5.2mA×1.8V 12mA×1.8V 11mA×1.8V 4mA×1.8V FOM 0.79 0.73 0.072 0.03 12.08 500M 502MHz.The 1st and 3rd order power are both REFERENCES attenuated by the output balun while the IIP3 value is same [1]W.Zhuo.S.Embabi.J.Pineda de Gyvez,and E.Sanchez-Sinencio to the simulated result. "Using Capacitive Cross-Coupling Technique In RF Low Noise Ampli- A figure of merit (FOM)is used to compare recent wide- fiers and Down-Conversion Mixer Design,"in Proc.26th Eur.Solid-State Circuits Conf,pp.116-119,Sep.2000. band LNAs with this work,which is given by [6] [2]Youchun Liao,Zhangwen Tang,and Hao Min,"A Wide-band CMOS Low-Noise Amplifier for TV Tuner Application."in Proc.of Asian Solid- FOM= Gain.IIP3 BW State Circuit Conf.(A-SSCC),Nov.2006,Hangzhou,China. Pac·(F-1)f (13)[3]D.Saias.et al."A 0.12m CMOS DVB-T Tuner".in Proc.IEEE Int. Solid-State Circuits Conf,2005,pp.430-431. 4]B.Razavi,Design of Analog CMOS Integrated Circuits.U.S.McGraw- where the gain and F are in absolute values.IIP3 and P HiL.2001. are in milliwatts,and the bandwidth is replaced by BW/fe. [5]F.Bruccoleri,E.A.M.Klumperink,and B.Nauta,"Generating All 2- Summary of the measured results and performance comparison MOS Transistors Amplifiers Leads To New Wide-Band LNAs,"IEEE J. Solid-State Circuits,vol.36.pp.1032-1040.July2001 are shown in Table I.The proposed LNA shows a highest FOM [6]A.Amer,E.Hegazi.and H.Ragai,"A Low-Power Wideband CMOS LNA in all published works. for WiMAX",IEEE Tran.on Circuit and Systems-II:Express Briefs,vol. 54,pp.4-8.Jan.2007. [7]T.W.Kim and B.Kim,"A 13-dB IIP3 Improved Low-Power CMOS RF V.CONCLUSION Programmable Gain Amplifier Using Differential Circuit Transconduc- tance Linearization For Various Terrestrial Mobile D-TV Applications. IEEE J.Solid-State Circuits,vol.41,pp.945-953.Apr.2006. In this paper,a differential capacitor-cross-coupled LNA [8]Jianghong Xiao.I.Mehr,and Jose Silva-Martinez,"A High Dynamic with a balun-based noise-canceling technique is proposed. Range CMOS Variable Gain Amplifier for Mobile DTV Tuner".IEEE J. Analysis shows that the noise contribution of the transconduc- Solid-State Circuits,vol.42.pp.292-301,Feb.2007. [9]Chih-Fan Liao,and Shen-luan Liu,"A Broadband Noise-Canceling tance MOST can be greatly reduced with three noise-canceling CMOS LNA for 3.1-10.6-GHz UWB Receivers",IEEE J.Solid-State paths.Measured results shows that the proposed LNA achieves Circuits,vol.42,pp.329-339.Feb.2007. low NF,high linearity and consumes low power during the 50M-860MHz frequency bandwidth. 94
50 250 450 650 860 1 1.5 2 2.5 3 3.5 Frequency(MHz) NF(dB) Simulated Measured Fig. 8. Simulated and measured NF. −30 −20 −10 0 10 −100 −80 −60 −40 −20 0 20 Input power(dBm) Output power(dBm) IIP3=8.3dBm Fig. 9. Measured IIP3. TABLE I SUMMARY OF MEASUREMENT RESULTS AND PERFORMANCE COMPARISON [3] [7] [8] [9] This Work CMOS Process 0.12-μm 0.18-μm 0.18-μm 0.18-μm 0.18-μm Frequency 48-862MHz 470-860MHz 470-870MHz 1.2-11.9GHz 50-860MHz Gain 17dB 10dB 16dB 9.7dB 15dB S11 N/A N/A -11dB -11dB -24dB NF 3dB 5.7dB 4.3dB 4.8dB 2.5dB IIP3 5.5dBm 10dBm -1.5dBm -6.2dBm 8.3dBm Power 23mA×2.5V 5.2mA×1.8V 12mA×1.8V 11mA×1.8V 4mA×1.8V FOM 0.79 0.73 0.072 0.03 12.08 500M & 502MHz. The 1st and 3rd order power are both attenuated by the output balun while the IIP3 value is same to the simulated result. A figure of merit (FOM) is used to compare recent wideband LNAs with this work, which is given by [6] FOM = Gain · IIP3 Pdc · (F − 1) · BW fc (13) where the gain and F are in absolute values, IIP3 and Pdc are in milliwatts, and the bandwidth is replaced by BW/fc. Summary of the measured results and performance comparison are shown in Table I. The proposed LNA shows a highest FOM in all published works. V. CONCLUSION In this paper, a differential capacitor-cross-coupled LNA with a balun-based noise-canceling technique is proposed. Analysis shows that the noise contribution of the transconductance MOST can be greatly reduced with three noise-canceling paths. Measured results shows that the proposed LNA achieves low NF, high linearity and consumes low power during the 50M-860MHz frequency bandwidth. REFERENCES [1] W. Zhuo, S. Embabi, J. Pineda de Gyvez, and E. Sanchez-Sinencio, “Using Capacitive Cross-Coupling Technique In RF Low Noise Ampli- fiers and Down-Conversion Mixer Design,” in Proc. 26th Eur. Solid-State Circuits Conf., pp.116-119, Sep. 2000. [2] Youchun Liao, Zhangwen Tang, and Hao Min, “A Wide-band CMOS Low-Noise Amplifier for TV Tuner Application,” in Proc. of Asian SolidState Circuit Conf. (A-SSCC), Nov. 2006, Hangzhou, China. [3] D. Saias, et al., “A 0.12m CMOS DVB-T Tuner”, in Proc. IEEE Int. Solid-State Circuits Conf., 2005, pp. 430-431. [4] B. Razavi, Design of Analog CMOS Integrated Circuits, U.S.:McGrawHill, 2001. [5] F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, “Generating All 2- MOS Transistors Amplifiers Leads To New Wide-Band LNAs,” IEEE J. Solid-State Circuits, vol. 36, pp. 1032-1040, July 2001. [6] A. Amer, E. Hegazi, and H. Ragai, “A Low-Power Wideband CMOS LNA for WiMAX”, IEEE Tran. on Circuit and Systems-II: Express Briefs, vol. 54, pp. 4-8, Jan. 2007. [7] T. W. Kim and B. Kim, “A 13-dB IIP3 Improved Low-Power CMOS RF Programmable Gain Amplifier Using Differential Circuit Transconductance Linearization For Various Terrestrial Mobile D-TV Applications,” IEEE J. Solid-State Circuits, vol. 41, pp. 945-953, Apr. 2006. [8] Jianghong Xiao, I. Mehr, and Jose Silva-Martinez, “A High Dynamic Range CMOS Variable Gain Amplifier for Mobile DTV Tuner”, IEEE J. Solid-State Circuits, vol. 42, pp. 292-301, Feb. 2007. [9] Chih-Fan Liao, and Shen-Iuan Liu, “A Broadband Noise-Canceling CMOS LNA for 3.1-10.6-GHz UWB Receivers”, IEEE J. Solid-State Circuits, vol. 42, pp. 329-339, Feb. 2007. 94