Switch-embedded opamp-sharing MDAC connected to the common-mode input voltage Viem,while Vinp.b and with dual-input OTA in pipelined ADC Vare the active differential inputs of the shared opamp.In the mean- time,the shared opamp works in holding mode for the S-B stage. R.Yin,X.Wen,Y.Liao,W.Zhang and Z.Tang Similarly,when 2 is high,both Vp.b and Vimb are tied to Viem while Vinp.e and Vinna are the active differential inputs of the shared A switch-embedded opamp-sharing multiplying digital-to-analogue opamp.The shared opamp works in holding mode for the S-A stage. converter (MDAC)with dual-input-differential-pair operational trans- Since both input pairs are reset to a common-mode input voltage alter- conductance amplifier(OTA)is proposed to eliminate the non-resetting nately,the memory effect is completely eliminated without any and successive-stage crosstalk problems in the conventional opamp additional clock phase.Furthermore,the opamp-sharing switches are sharing technique.A 10-bit 80 MS/s pipelined analogue-to-digital embedded into the opamp instead of in series between the capacitor converter(ADC)is implemented in a 0.18 um CMOS process by and the opamp input,therefore the crosstalk path is avoided.In addition, using the proposed MDAC.Compared with a traditional opamp- the charge injection and the input-dependent resistance do not exist for sharing ADC,the measured signal-to-noise ratio is improved from 55.9 to 60.1 dB and the spurious free dynamic range is improved the same reason. from 66 to 76 dB without any additional power or area consumption or clock phase. S-A 1D s.R Introduction:Applications used in many electronic systems,such as 1C1 29 video decoder and wireless communication,require high-resolution low-power analogue-to-digital converters (ADCs).One of the most effi- 02 01D cient ways to save power is opamp-sharing between successive pipelined ADC stages.However,that is achieved at the cost of resolution reduction. since the opamp-sharing ADC has two serious problems.First. because the opamp input summing node is never reset,every input 1D 2 V sample will be affected by the error voltage stored on the input capacitor due to the previous sample.Thus it suffers from the memory effect. 1D which can be considered as a kind of offset [I].Secondly,there is a potential crosstalk path between two successive stages caused by the Fig.2 Schematic of opamp-sharing MDAC parasitic capacitors of switches that are used to implement opamp sharing.The signals in the current and successive stages,which appear at input nodes of the shared opamp,will influence each other Timing considerations:The two-phase non-overlapping clock is always through the crosstalk path.In addition,the opamp-sharing switches used in a pipelined ADC,but is not suitable for controlling the opamp- also introduce charge injection and input-dependent resistances.These sharing switches in the proposed OTA.Because two input differential factors deteriorate both the signal-to-noise ratio (SNR)and the linearity pairs will be disabled in the non-overlapping period,there is no To alleviate the non-resetting problem,feedback signal polarity invert- current path to ground for the above PMOS transistor branches ing (FSPI)is used to alternate the signal polarity,but it can only (M11-M14).The output voltage of the shared opamp will shift to a reduce the opamp offset by 2/3 [2].To break the crosstalk path,isolation much higher level above the common output voltage during the non- switches are added to tie the parasitic capacitor to ground,and the overlapping period.In the worst case,the above PMOS transistors signal-to-noise-and-distortion ratio (SNDR)is improved by 1-2 dB. may enter into the linear region and the holding phase of MDAC but the added switches increase the series resistances and the charge stages would waste some time in the large-signal slew-rate.Therefore, injection [3].Although opamp current reuse can solve the problems of the proposed opamp uses two-phase overlapping clocks (IDn and non-resetting and the crosstalk path by using both NMOS and PMOS Φ2Dn)to avoid this problem.SinceΦIDn andΦ2 Dn are already input differential pairs in shared opamps,the capacitive level shifter used for the CMOS switches,no additional clock phase is needed increases the design complexity and the PMOS input differential pair The overlapping working will not affect either the fidelity of signal decreases the power efficiency [4]. transfer or settling or the quantisation process.On the one hand during the overlapping period,the shared opamp has not been working for signal settling until ID/2D is high.Signal transfer and settling will not be affected because there is no charge leakage path and the two input differential pairs will not affect each other.On the other hand,the comparing operation has already been achieved at a moment between the falling edges of l and dID,so the overlapping 1 12 working has no adverse effect on the quantisation process either. 0 0- -20 fr=8 MHz SFDR=72.1 dB 40 SNDR=601 dB M2 -60 ENOB=9.69 bit -80 M16 CMFB -100 0 -20 fin=39.5 MHz SFDR=76.0 dB Fig.1 Proposed dual-input-differential-pair gain-boosting telescopic ampli- 40 SNDR=59.8 de fier with clock timing -60 ENOB =9.63 bit -80 Proposed switch-embedded opamp-sharing MDAC:To get rid of the -100 d山lal 0 10 30 40 problems of non-resetting and successive-stage crosstalk,a gain-boost- ing telescopic operational transconductance amplifier (OTA)with a dual-input-differential-pair is proposed,as shown in Fig.1.Each input Fig.3 Measured FFT plot at sample frequency of 80 MHz with input signals transistor (MI-M4)is connected with a MOS switch (M5-M8)in of 8 and 39.5 MHz series,respectively.The switch is on when its corresponding control signal(i.e.ΦIDn and④Φ2Dn)is high,and is off when the control Experimental results:A common pipelined ADC is implemented by signal is low.By careful biasing,the switches with small invariable using the proposed MDAC.The ADC is composed of an S/H circuit, resistances will not affect the performance of the shared opamp.A eight 1.5-bit MDACs using four shared opamps,and a 2-bit flash 1.5-bit opamp-sharing multiplying DAC (MDAC)using the proposed ADC as the last stage.The ADC is fabricated in a 0.18 pm CMOS OTA is shown in Fig.2.When l is high,both Vimp.a and Vin are process.The chip consumes 28 mW from a 1.8 V power supply at ELECTRONICS LETTERS 10th June 2010 Vol.46 No.12 Authorized licensed use limited to:FUDAN UNIVERSITY.Downloaded on June 30,2010 at 03:05:13 UTC from IEEE Xplore.Restrictions apply
Switch-embedded opamp-sharing MDAC with dual-input OTA in pipelined ADC R. Yin, X. Wen, Y. Liao, W. Zhang and Z. Tang A switch-embedded opamp-sharing multiplying digital-to-analogue converter (MDAC) with dual-input-differential-pair operational transconductance amplifier (OTA) is proposed to eliminate the non-resetting and successive-stage crosstalk problems in the conventional opampsharing technique. A 10-bit 80 MS/s pipelined analogue-to-digital converter (ADC) is implemented in a 0.18 mm CMOS process by using the proposed MDAC. Compared with a traditional opampsharing ADC, the measured signal-to-noise ratio is improved from 55.9 to 60.1 dB and the spurious free dynamic range is improved from 66 to 76 dB without any additional power or area consumption or clock phase. Introduction: Applications used in many electronic systems, such as video decoder and wireless communication, require high-resolution low-power analogue-to-digital converters (ADCs). One of the most effi- cient ways to save power is opamp-sharing between successive pipelined stages. However, that is achieved at the cost of resolution reduction, since the opamp-sharing ADC has two serious problems. First, because the opamp input summing node is never reset, every input sample will be affected by the error voltage stored on the input capacitor due to the previous sample. Thus it suffers from the memory effect, which can be considered as a kind of offset [1]. Secondly, there is a potential crosstalk path between two successive stages caused by the parasitic capacitors of switches that are used to implement opamp sharing. The signals in the current and successive stages, which appear at input nodes of the shared opamp, will influence each other through the crosstalk path. In addition, the opamp-sharing switches also introduce charge injection and input-dependent resistances. These factors deteriorate both the signal-to-noise ratio (SNR) and the linearity. To alleviate the non-resetting problem, feedback signal polarity inverting (FSPI) is used to alternate the signal polarity, but it can only reduce the opamp offset by 2/3 [2]. To break the crosstalk path, isolation switches are added to tie the parasitic capacitor to ground, and the signal-to-noise-and-distortion ratio (SNDR) is improved by 1– 2 dB, but the added switches increase the series resistances and the charge injection [3]. Although opamp current reuse can solve the problems of non-resetting and the crosstalk path by using both NMOS and PMOS input differential pairs in shared opamps, the capacitive level shifter increases the design complexity and the PMOS input differential pair decreases the power efficiency [4]. overlapping time non-overlapping time delay time F2Dn F1 F2 F2D F1D F2Dn F1Dn F2Dn F1Dn F1Dn Vinn,b Vpc Vb1 Vnc Voutn Voutp VDD Vb4 M15 M16 CMFB M1 M2 M6 M4 M8 M3 M7 M5 M9 M10 M11 M12 M13 M14 Vinn,b Vinn,a Vinn,a Fig. 1 Proposed dual-input-differential-pair gain-boosting telescopic ampli- fier with clock timing Proposed switch-embedded opamp-sharing MDAC: To get rid of the problems of non-resetting and successive-stage crosstalk, a gain-boosting telescopic operational transconductance amplifier (OTA) with a dual-input-differential-pair is proposed, as shown in Fig. 1. Each input transistor (M1 –M4) is connected with a MOS switch (M5 –M8) in series, respectively. The switch is on when its corresponding control signal (i.e. F1Dn and F2Dn) is high, and is off when the control signal is low. By careful biasing, the switches with small invariable resistances will not affect the performance of the shared opamp. A 1.5-bit opamp-sharing multiplying DAC (MDAC) using the proposed OTA is shown in Fig. 2. When F1 is high, both Vinp,a and Vinn,a are connected to the common-mode input voltage Vicm, while Vinp,b and Vinn,b are the active differential inputs of the shared opamp. In the meantime, the shared opamp works in holding mode for the S-B stage. Similarly, when F2 is high, both Vinp,b and Vinn,b are tied to Vicm, while Vinp,a and Vinn,a are the active differential inputs of the shared opamp. The shared opamp works in holding mode for the S-A stage. Since both input pairs are reset to a common-mode input voltage alternately, the memory effect is completely eliminated without any additional clock phase. Furthermore, the opamp-sharing switches are embedded into the opamp instead of in series between the capacitor and the opamp input, therefore the crosstalk path is avoided. In addition, the charge injection and the input-dependent resistance do not exist for the same reason. F1 F1 F2 F2 F1 F2 F1D F1D F1D F2D F2D F2D F2D C4a sub ADC sub DAC sub DAC sub ADC C4b C2a S-A S-B C2b C3a C3b C1a C1b F2D F2D F1D F1D F1D F2Dn F1Dn Voutn Voutp Vicm Vicm Vicm Vicm Vinp,a Vinp,a Vinp,b Vinp,b Vinn Vinp Vinn,b Vinn,b Fig. 2 Schematic of opamp-sharing MDAC Timing considerations: The two-phase non-overlapping clock is always used in a pipelined ADC, but is not suitable for controlling the opampsharing switches in the proposed OTA. Because two input differential pairs will be disabled in the non-overlapping period, there is no current path to ground for the above PMOS transistor branches (M11 –M14). The output voltage of the shared opamp will shift to a much higher level above the common output voltage during the nonoverlapping period. In the worst case, the above PMOS transistors may enter into the linear region and the holding phase of MDAC stages would waste some time in the large-signal slew-rate. Therefore, the proposed opamp uses two-phase overlapping clocks (F1Dn and F2Dn) to avoid this problem. Since F1Dn and F2Dn are already used for the CMOS switches, no additional clock phase is needed. The overlapping working will not affect either the fidelity of signal transfer or settling or the quantisation process. On the one hand, during the overlapping period, the shared opamp has not been working for signal settling until F1D/F2D is high. Signal transfer and settling will not be affected because there is no charge leakage path and the two input differential pairs will not affect each other. On the other hand, the comparing operation has already been achieved at a moment between the falling edges of F1 and F1D, so the overlapping working has no adverse effect on the quantisation process either. 0 –100 –80 –60 dB–40 –20 0 –100 –80 –60 dB–40 –20 0 10 20 30 f in = 39.5 MHz SFDR = 76.0 dB SNDR = 59.8 dB ENOB = 9.63 bit f in = 8 MHz SFDR = 72.1 dB SNDR = 60.1 dB ENOB = 9.69 bit 40 frequency, MHz Fig. 3 Measured FFT plot at sample frequency of 80 MHz with input signals of 8 and 39.5 MHz Experimental results: A common pipelined ADC is implemented by using the proposed MDAC. The ADC is composed of an S/H circuit, eight 1.5-bit MDACs using four shared opamps, and a 2-bit flash ADC as the last stage. The ADC is fabricated in a 0.18 mm CMOS process. The chip consumes 28 mW from a 1.8 V power supply at ELECTRONICS LETTERS 10th June 2010 Vol. 46 No. 12 Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on June 30,2010 at 03:05:13 UTC from IEEE Xplore. Restrictions apply
80 MS/s.Fig.3 shows the FFT plot for the input frequencies of 8 and opamp-sharing method eliminates the memory effect and crosstalk path 39.5 MHz at 80 MHz sample rate.The ADC achieves a peak SNDR of without any additional power or area consumption or clock phase.The 60.1 dB and a peak spurious free dynamic range(SFDR)of 76 dB. measured SNDR and SFDR are improved from 55.9 to 60.1 dB and while the effective number of bits (ENOB)is maintaining more than from 66 to 76 dB,respectively. 9.6 bit for the full Nyquist input bandwidth.When the input frequency is close to the sample rate,the ADC still maintains 9.47 ENOB.Fig.4 C The Institution of Engineering and Technology 2010 shows the measured SNDR and SFDR compared between this work and 7 January 2010 a traditional ADC with the additional isolated switches as in [3],and the doi:10.1049/el.2010.0051 two ADCs are the same except the shared method of opamp.A perform- One or more of the Figures in this Letter are available in colour online. ance summary is shown in Table 1. R.Yin,X.Wen,W.Zhang and Z.Tang (ASIC System State Key 80 Laboratory,Fudan University,Shanghai.People's Republic of China) E-mail:yinrui@fudan.edu.cn SFDR Y.Liao (Ratio Microelectronics Co.Ltd,Shanghai.People's Republic SFDR of China) 60 SNDR References SNb常· f,=80 MS/s 1 Nagaraj,K.,Fetterman,H.S.,Anidjar,J.,Lewis,S.H.,and Renninger, R.G.:A 250-mW.8-b,52-Msamples/s parallel-pipelined A/D 0 2040 6080 converter with reduced number of amplifiers',IEEE Solid-State input frequency,MHz Circuits,1997,32,(3),Pp.312-320 2 Min.B..Kim.P..Boisvert.D..and Aude,A.:'A 69mW 10b 80MS/s Fig.4 Measured SNDR and SFDR compared between this work and tra- pipelined CMOS ADC'.ISSCC Dig.Tech.Pprs.February 2003. ditional opamp-sharing ADC pP.324-325 3 Li,J.,Zeng,X.,Xie,L.,Chen,J.,Zhang,J.,and Guo,Y.:'A 1.8-V 22. Table 1:Performance comparisons of traditional and proposed mW 10-bit 30-MS/s pipelined CMOS ADC for low-power subsampling ADC applications',IEEE J.Solid-State Circuits,2008,43,(2),pp.321-329 4 Ryu,S.-T.,Song,B.-S.,and Bacrania,K.:'A 10 b 50 MS/s pipelined Traditional ADC This work ADC with opamp current reuse'.ISSCC Dig.Tech.Pprs,February Opamp-sharing method Adding isolated switches Switch-embedded 2005,pp.792-801 Resolution 10bits Sample rate 80 MS/s Process 0.18μn CMOS (MIM cap) Input range 1.6V SNDR 55.9dB 60.1dB SFDR 66 dB 76 dB DNL +0.75/-0.63LSB+0.37/-0.23LSB INL +0.84/-1.12LSB+0.53/-0.87LSB Power consumption 28 mW Active die area 1.1mm Conclusions:This Letter describes a switch-embedded opamp-sharing MDAC based on a dual-input-differential-pair opamp.A 10-bit 80MS/s pipelined ADC was implemented by using the proposed MDAC.Compared with a traditional opamp-sharing ADC,the proposed ELECTRONICS LETTERS 10th June 2010 Vol.46 No.12 Authorized licensed use limited to:FUDAN UNIVERSITY.Downloaded on June 30.2010 at 03:05:13 UTC from IEEE Xplore.Restrictions apply
80 MS/s. Fig. 3 shows the FFT plot for the input frequencies of 8 and 39.5 MHz at 80 MHz sample rate. The ADC achieves a peak SNDR of 60.1 dB and a peak spurious free dynamic range (SFDR) of 76 dB, while the effective number of bits (ENOB) is maintaining more than 9.6 bit for the full Nyquist input bandwidth. When the input frequency is close to the sample rate, the ADC still maintains 9.47 ENOB. Fig. 4 shows the measured SNDR and SFDR compared between this work and a traditional ADC with the additional isolated switches as in [3], and the two ADCs are the same except the shared method of opamp. A performance summary is shown in Table 1. 0 50 60 70 80 20 40 f s=80 MS/s 60 SNDR SNDR SFDR SFDR input frequency, MHz dB 80 this work traditional ADC Fig. 4 Measured SNDR and SFDR compared between this work and traditional opamp-sharing ADC Table 1: Performance comparisons of traditional and proposed ADC Traditional ADC This work Opamp-sharing method Adding isolated switches Switch-embedded Resolution 10 bits Sample rate 80 MS/s Process 0.18 mm CMOS (MIM cap) Input range 1.6 Vpp SNDR 55.9 dB 60.1 dB SFDR 66 dB 76 dB DNL +0.75/ 2 0.63 LSB +0.37/ 2 0.23 LSB INL +0.84/ 2 1.12 LSB +0.53/ 2 0.87 LSB Power consumption 28 mW Active die area 1.1 mm2 Conclusions: This Letter describes a switch-embedded opamp-sharing MDAC based on a dual-input-differential-pair opamp. A 10-bit 80 MS/s pipelined ADC was implemented by using the proposed MDAC. Compared with a traditional opamp-sharing ADC, the proposed opamp-sharing method eliminates the memory effect and crosstalk path without any additional power or area consumption or clock phase. The measured SNDR and SFDR are improved from 55.9 to 60.1 dB and from 66 to 76 dB, respectively. # The Institution of Engineering and Technology 2010 7 January 2010 doi: 10.1049/el.2010.0051 One or more of the Figures in this Letter are available in colour online. R. Yin, X. Wen, W. Zhang and Z. Tang (ASIC & System State Key Laboratory, Fudan University, Shanghai, People’s Republic of China) E-mail: yinrui@fudan.edu.cn Y. Liao (Ratio Microelectronics Co. Ltd, Shanghai, People’s Republic of China) References 1 Nagaraj, K., Fetterman, H.S., Anidjar, J., Lewis, S.H., and Renninger, R.G.: ‘A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers’, IEEE J. Solid-State Circuits, 1997, 32, (3), pp. 312 –320 2 Min, B., Kim, P., Boisvert, D., and Aude, A.: ‘A 69mW 10b 80MS/s pipelined CMOS ADC’. ISSCC Dig. Tech. Pprs, February 2003, pp. 324– 325 3 Li, J., Zeng, X., Xie, L., Chen, J., Zhang, J., and Guo, Y.: ‘A 1.8-V 22- mW 10-bit 30-MS/s pipelined CMOS ADC for low-power subsampling applications’, IEEE J. Solid-State Circuits, 2008, 43, (2), pp. 321–329 4 Ryu, S.-T., Song, B.-S., and Bacrania, K.: ‘A 10 b 50 MS/s pipelined ADC with opamp current reuse’. ISSCC Dig. Tech. Pprs, February 2005, pp. 792 –801 ELECTRONICS LETTERS 10th June 2010 Vol. 46 No. 12 Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on June 30,2010 at 03:05:13 UTC from IEEE Xplore. Restrictions apply