Analysis of Self-resonant Frequency for Differential-driven Symmetric and Single-ended Inductors Hongyan Jian*,Zhangwen Tang,Jie He,Hao Min ASIC System State Key Laboratory,Fudan University,Shanghai 200433,China *Email:hyjian@fudan.edu.cn Abstract In this paper,a distributed capacitance model (DCM)for fow=xC) (2) monolithic inductors is developed to predict the equiva- The DCM for monolithic spiral has been studied in lent parasitical capacitances of inductor.The ratio of the recently years [2-4].In this paper,DCMs of inductors self-resonant frequency (sR)of the differentially driven are developed to accurately quantify the equivalent symmetric inductor (fsR dim)to the fsR of the single-ended driven inductor (fsRs)has been firstly predicted and capacitive coupling capacitances(C)between the explained.Compared with an equivalent single-ended two terminals and the equivalent capacitance between configuration,experimental data demonstrate that the the metal track and the substrate (Cm)of the differential inductor offers a 127%greater maximum symmetric inductors that are driven differentially and quality factor(Omax)and a broader range of operating frequencies.Design guidelines have been obtained from single-ended.Consequently the ratio of the fsRdi the fsR se has been firstly predicted and explained.Design DCM. guidelines have been obtained from DCM. Key words:Distributed capacitance model (DCM, 2.Distributed capacitance model self-resonant frequency (fsR)ratio,high quality factor Inductors that are driven differentially or single-ended (O),on-chip inductor,optimum designs. (Seen Figure 1)have differentC 1.Introduction Monolithic inductor is an important component in highly Cm_m_symmetric Cm_m_symmetric Cm m_se_spiral integrated radio frequency circuits(RF ICs)for wireless communication systems.But on-chip inductor has low O due to metal ohmic loss and conductive silicon substrate loss.Many researchers found quite a few methods to improve o of on-chip inductor [1].A symmetric inductor that is driven differentially can realize a substantially greater factor without altering the fabrication process. If an inductor is modeled as a simple parallel RLC tank, it can be shown that (E-E) Cm_s 2Cm_s Cms Oind =20 (1) (a) (b) (c) Figure 1.The planar on-chip inductors with the same where E,E,pa denote the average magnetic and track width,space,inner and outer radius:(a) electric energies stored and the average power dissipated Differentially driven symmetric configuration (DSP/);(b in the inductor,respectively.Ethe total equivalent Single-ended driven symmetric configuration (SSPD):(c) Single-ended spiral configuration (SEPD).(Note:123456 capacitance of the inductor (C),therefore,the lower are current flow direction in inductor,i.e.AC signal voltage profile or half turns serial number;Capacitances the C the higher Q and Isk the inductor have.The are the equivalent parasitical capacitance of the on-chip Isg can be defined as the frequency while o drops to inductor. zero The electrical energy stored in the equivalent capacitor of the inductor can be divided into two parts:one is in 0-7803-8511-X/04/S20.00©2004EEE
Analysis of Self-resonant Frequency for Differential-driven Symmetric and Single-ended Inductors Hongyan Jian*, Zhangwen Tang, Jie He, Hao Min ASIC & System State Key Laboratory, Fudan University, Shanghai 200433, China *Email: hyjian@fudan.edu.cn Abstract In this paper, a distributed capacitance model (DCM) for monolithic inductors is developed to predict the equivalent parasitical capacitances of inductor. The ratio of the self-resonant frequency (fSR) of the differentially driven symmetric inductor (fSR_diff) to the fSR of the single-ended driven inductor (fSR_se) has been firstly predicted and explained. Compared with an equivalent single-ended configuration, experimental data demonstrate that the differential inductor offers a 127% greater maximum quality factor (Qmax) and a broader range of operating frequencies. Design guidelines have been obtained from DCM. Key words: Distributed capacitance model (DCM), self-resonant frequency (fSR) ratio, high quality factor (Q), on-chip inductor, optimum designs. 1. Introduction Monolithic inductor is an important component in highly integrated radio frequency circuits (RF ICs) for wireless communication systems. But on-chip inductor has low Q due to metal ohmic loss and conductive silicon substrate loss. Many researchers found quite a few methods to improve Q of on-chip inductor [1]. A symmetric inductor that is driven differentially can realize a substantially greater factor without altering the fabrication process. If an inductor is modeled as a simple parallel RLC tank, it can be shown that ( ) 2 av av m e ind av l E E Q P ω − = (1) where av Em ， av Ee ， av Pl denote the average magnetic and electric energies stored and the average power dissipated in the inductor, respectively. av Ee ∝the total equivalent capacitance of the inductor (Ceq ), therefore, the lower the Ceq , the higher Q and SR f the inductor have. The SR f can be defined as the frequency while Q drops to zero. ( ) 1 2 SR eq eq f LC π − = (2) The DCM for monolithic spiral has been studied in recently years [2-4]. In this paper, DCMs of inductors are developed to accurately quantify the equivalent capacitive coupling capacitances (Cm m_ ) between the two terminals and the equivalent capacitance between the metal track and the substrate ( Cm s _ ) of the symmetric inductors that are driven differentially and single-ended. Consequently the ratio of the fSR_diff the fSR_se has been firstly predicted and explained. Design guidelines have been obtained from DCM. 2. Distributed capacitance model Inductors that are driven differentially or single-ended (Seen Figure 1.) have differentCeq . 1 2 + Vs 1 2 − Vs Vs Vs Signal Ground 1 5 3 4 2 6 1 5 3 4 2 6 1 3 5 6 4 2 Cm_m_symmetric Cm_m_symmetric Cm_m_se_spiral Cm_s Cm_s 0 Cm_s Cm_s 1 2 1 2 (a) (b) (c) Figure 1. The planar on-chip inductors with the same track width, space, inner and outer radius: (a) Differentially driven symmetric configuration (DSPI); (b) Single-ended driven symmetric configuration (SSPI); (c) Single-ended spiral configuration (SEPI). (Note: 123456 are current flow direction in inductor, i.e. AC signal voltage profile or half turns serial number; Capacitances are the equivalent parasitical capacitance of the on-chip inductor.) The electrical energy stored in the equivalent capacitor of the inductor can be divided into two parts: one is in 0-7803-8511-X/04/$20.00 ©2004 IEEE
the metal-to-metal capacitor,i.e.Ec.and the other inductor is equally divided into k units (i>oo); is in the metal-to-substrate capacitor,i.emand it According to assumption 2),the voltage ith unit is V, can be derived as =。m-石(ag.) (6) where, 2 ((m)(m)Therefore.the electrical energy stored in the capacitor between the ith unit metal and the substrate can be expressed as Therefore,the equivalent capacitor of the inductor can 50-号co-(af-cm-j(の be expressed as where Cms represents the capacitance per unit area between the mth half turn and the substrate.The Cog=Cm_+Cm_ (4) electrical energy stored in the equivalent capacitance between the metal tracks of the Lms(m)and the substrate 2.1 Assumptions and definitions can be derived from [5] To accurately quantify Cm and Cms in inductors,the proposed DCM can analytically calculate them rather E_(m)=Cw(mV(m)+V(m)+V(m)V(m)(8) than qualitatively approximate [2].The fundamental 6 assumptions of DCM can be derived from the voltage Whatever structure inductor is,we can get entire distribution over the inductor,which is called voltage E.by adding up all E.m(m). profile in [3].For the conveniences of calculation and analysis,the following assumptions are made. Two terminal voltages of the differentially driven 1)The same layer metal traces of inductor have the same resistivity p,current,and metal track width w(at least inductor with symmetrically planar configuration(DSPD), in the same half turn),metal thickness t. ae+与'and-ly respectively.Hence 2)Voltage distribution is proportional to the lengths of 2 the metal tracks [3]. 11 (9) 3)The kth unit voltage difference between the adjacent 2m邮 half turns is regarded as constant and it is determined by averaging the beginning voltage and the ending voltage (10) of the half turns,regardless of the type of the inductor. Cm.=12m k (Note:This assumption only using in quantifing Cmm, where Cis equivalent capacitance between the not in quantifing Cm s) metal track and the substrate of the D.SPI The length of each half turn can be defined The signal terminal voltage of the single-ended driven as,,,..(n is turn number,sequential m planar inductor (SEPD)is Is and that of another represent current flow direction in inductor),and the terminal is 0,hence total length is defined asl=++.+).AC 11 1 signal voltage of one terminal of inductor is e while Ec.ms_dug= (11) 23 2 that of the other is Vend.According assumptions,AC signal voltage at the end terminal of the mth half turn C=CmWl (12) 3 inductor nd(m)]can be expressed as where Cis the equivalent capacitance between the metal track and the substrate of the SEPI (5) According to equation (10)and (12),under the same AC signal voltage at the beginning terminal of the mth equivalent area between the metal track and the substrate, half turn inductor [bee(m)]equal to the Vend(m-1). we can get the following equation Vbeg(0)=Vbeg. CC (13) 2.2.Equivalent Capacitance C Formula The DSPI can be regarded as two SEPI that have The lowest layer metal track of the mth half turn identical substrate parasitics at signal ports,which is half
the metal-to-metal capacitor, i.e. ECm m , _ and the other is in the metal-to-substrate capacitor, i.e., ECm s , _ and it can be derived as ( ) 2 , ,_ ,_ 22 2 _ _ __ 1 2 111 (3) 222 C total eq s C m s C m m mm s ms s mm ms s E CV E E C V CV C C V = =+ = + =⋅ + ⋅ Therefore, the equivalent capacitor of the inductor can be expressed as CC C eq m m m s = + _ _ (4) 2.1 Assumptions and definitions To accurately quantify Cm_m and Cm_s in inductors, the proposed DCM can analytically calculate them rather than qualitatively approximate [2]. The fundamental assumptions of DCM can be derived from the voltage distribution over the inductor, which is called voltage profile in [3]. For the conveniences of calculation and analysis, the following assumptions are made. 1) The same layer metal traces of inductor have the same resistivity ρ , current, and metal track width w (at least in the same half turn), metal thickness t. 2) Voltage distribution is proportional to the lengths of the metal tracks [3]. 3) The kth unit voltage difference between the adjacent half turns is regarded as constant and it is determined by averaging the beginning voltage and the ending voltage of the half turns, regardless of the type of the inductor. (Note: This assumption only using in quantifing Cm_m, not in quantifing Cm_s) The length of each half turn can be defined as, 12 2 , ,... , m n ll l l (n is turn number, sequential m represent current flow direction in inductor), and the total length is defined as 12 2 ( ... ) tot n l ll l =+++ . AC signal voltage of one terminal of inductor is Vbeg, while that of the other is Vend. According assumptions, AC signal voltage at the end terminal of the mth half turn inductor [Vend(m)] can be expressed as ( ) 1 1 ( ) m j j end beg end tot l Vm V V l + = = − ∑ (5) AC signal voltage at the beginning terminal of the mth half turn inductor [Vbeg(m)] equal to the Vend(m-1). Vbeg(0)= Vbeg. 2.2. Equivalent CapacitanceCm s _ Formula The lowest layer metal track of the mth half turn inductor is equally divided into k units ( i → ∞ ); According to assumption 2), the voltage ith unit is Vi, i beg m ( ) () ( ) i V V m Vi k = − ⋅∆ (6) where, 1 ( ) ( ( ) ( )) k Vi V m V m m beg end k →∞ ∆≡ − . Therefore, the electrical energy stored in the capacitor between the ith unit metal and the substrate can be expressed as ( ) ( ) 2 2 , 1 11 () () ( ) ( ) 2 2 c ms m ms beg end wl E i Ci V C V m V m k k ⎛ ⎞⎛ ⎞ ∆ = ⋅ ⋅∆ = ⋅ ⋅ − ⎜ ⎟⎜ ⎟ ⎝ ⎠⎝ ⎠ (7) where Cms represents the capacitance per unit area between the mth half turn and the substrate. The electrical energy stored in the equivalent capacitance between the metal tracks of the Lms(m) and the substrate can be derived from [5] ( ) 2 2 , _ 1 () () () () () () 6 beg E m C wl m V m V m V m V m c m s ms end beg end = + +⋅ (8) Whatever structure inductor is, we can get entire Ecm s , _ by adding up all , _ ( ) E m cm s . Two terminal voltages of the differentially driven inductor with symmetrically planar configuration (DSPI), are 1 2 + VS and 1 2 − Vs , respectively. Hence 2 2 , _ __ 11 1 2 12 2 E C wl V C V c ms diff ms tot s m s diff s ⎛ ⎞ = = ⎜ ⎟ ⎝ ⎠ i ii i (9) _ _ 1 12 tot m s diff ms wl C C k = (10) where Cm s diff _ _ is equivalent capacitance between the metal track and the substrate of the DSPI. The signal terminal voltage of the single-ended driven planar inductor (SEPI) is VS and that of another terminal is 0, hence 2 2 , _ __ 11 1 23 2 E C wl V C V c ms diff ms tot s m s se s ⎛ ⎞ = = ⎜ ⎟ ⎝ ⎠ i ii i (11) _ _ 1 3 C C wl m s se ms = (12) where Cm s se _ _ is the equivalent capacitance between the metal track and the substrate of the SEPI. According to equation (10) and (12), under the same equivalent area between the metal track and the substrate, we can get the following equation __ __ 1 4 C C m s diff m s se = (13) The DSPI can be regarded as two SEPI that have identical substrate parasitics at signal ports, which is half
of whole inductor;Their connection point is signal 1 ground: Signal terminal voltage is+s c"-}7 1 and - V respectively and the C.of two 3.Model validation and design guidelines inductors are in series connection,hence,we can obtain the same result as equation (13). 2.3.Equivalent Capacitance Cm Formula The voltage difference between the ith and ith half turn n■■■■ can be expressed as (a) (b) Figure 2.Die photos of the inductors (a)in 0.35 um A=g-yw-小0≤sm (14) CMOS processes and (b)one inductor with probes. The electrical energy stored in the equivalent In order to verify the accuracy,inductors have been capacitance between the metal tracks of the ith half turn fabricated in a 0.35 L m two-poly four-metal CMOS and ith half turn can be expressed as processes as shown in Figure 2(a).The prototype chips also include the de-embed layouts to calibrate the Eni=∑AEW肉)-2 Vi-V 2(15) on-wafer testing wiring and pads [6].The S parameters 2 were measured by a network analyzer and Cascade where C is the unit capacitance between the ith Microtech Probe Station using coplanar ground-signal-ground probes.The prediction error of fsR and ith adjacent half turns of inductor:W is metal tracks and width w of inductor(when the ith half turn and ith half Ratio with DCM is less than 10%. turn are stacked)or metal thickness t (when the ith half demonstrating the accuracy of the DCM. turn and ith half turn are in the same layer). Thus,the equivalent capacitor of the inductor can be Regardless of the structures(stacked,spiral,symmetric, calculated,when we know the inductance,according to etc.)and driven modes (differentially or single-ended), equation (2),(10)and (16),the ratio of the fsR of the the electrical energy stored in the equivalent capacitance optional two inductors with equivalent inductance L between the metal can be expressed as the sum of the Le and the equivalent capacitor CCrespectively electrical energy stored in the equivalent capacitance can be expressed as between the metal traces at same layers and at the Ratio Le×Cg2 (18) adjacent layers.Different Cformulascan be derived Lg×Ca rom(51)and￡m=C.化e-a The inductance equal approximately, Lsymmetric,if the current flows in the same direction We define the C of the DSPI as C the along each adjacent conductor of the planar inductors with the same geometric parameters [such as Figure Cof the symmetric inductor in single-ended driven 1(a),(b),(c)],and the voltage differences between the adjacent turns of the DSPI and SSPI is larger than those configuration (SSEI)as C and the of the SEPI,So Cm_m_se_symmetric=Cm_m_dift symmetric> Cm of the SEPI as Cpral Thus, Cmm_se_spiral,but 4Cmditt symmetrie-Cm_sse symmetric= Cm_mse_spiral, therefore, sR_diff_symmetric/SR_se_spiral SR_se_symmetric and OsR_dift_symmetricOsR_se_spiral OsR se_symmetrie.This conclusion and equation (18)can offer design guidelines to select inductor and circuit configurations. (16) The Ratio can be predicted and explained from equations (18).Compared with an equivalent single-ended configuration, experimental data
of whole inductor; Their connection point is signal ground; Signal terminal voltage is 1 2 + VS and 1 2 − V s respectively and the Cm s _ of two inductors are in series connection, hence, we can obtain the same result as equation (13). 2.3. Equivalent CapacitanceCm m_ Formula The voltage difference between the ith and jth half turn can be expressed as , ( ),(0 , ) j k k i i j i j beg end tot l V V V V V ij n l = ∆ =− = − ≤ ≤ ∑ i (14) The electrical energy stored in the equivalent capacitance between the metal tracks of the ith half turn and jth half turn can be expressed as ( ) ( ) 2 _ 2 ,_ ,_ 2 1 ( ) 1 (, ) ( ) 2 2 j N mm ij i j k k i c m s c m m beg end k tot C kWl l l E ij E k V V l →∞ = = ⎛ ⎞ ⋅⋅+ ⋅⎜ ⎟ ⎝ ⎠ = ∆ =⋅ ⋅ − ∑ ∑ (15) where Cmm ij _ is the unit capacitance between the ith and jth adjacent half turns of inductor; W is metal tracks width w of inductor (when the ith half turn and jth half turn are stacked) or metal thickness t (when the ith half turn and jth half turn are in the same layer). Regardless of the structures (stacked, spiral, symmetric, etc.), and driven modes (differentially or single-ended), the electrical energy stored in the equivalent capacitance between the metal can be expressed as the sum of the electrical energy stored in the equivalent capacitance between the metal traces at same layers and at the adjacent layers. Different Cm m_ formulas can be derived from equation (15) and ( )2 , _ 1 2 E CVV c mm m m beg end = − . We define the Cm m_ of the DSPI as Cm m diff _ _ , the Cm m_ of the symmetric inductor in single-ended driven configuration (SSEI) as Cm m diff se __ _ and the Cm m_ of the SEPI as Cm m se spiral ___ . Thus， ( ) ( ) 2 1 _ _ _ _ _ _, 1 2 2 2 2 2 _ ,2 2 2 ( ) 2 ( ) (16) 2 n k n k k nk k k m m diff m m diff se mm k n k k tot n k n k k nk k k mm k n k k tot l Wl l C C Ck l l Wl l C k l − − − = − = + − + − = + − = ⎛ ⎞ ⎜ ⎟ + = = ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ ⎛ ⎞ ⎜ ⎟ + + ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ ∑ ∑ ∑ ∑ ( ) 2 2 2 2 1 2 ___ _ 1 ( ) 2 n k k k k m m se spiral mm ij k tot Wl l l l C Ck l − + + + = ⎛ ⎞ + ⎛ ⎞ + = ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ ⎝ ⎠ ∑ (17) 3. Model validation and design guidelines (a) (b) Figure 2. Die photos of the inductors (a) in 0.35 µ m CMOS processes and (b) one inductor with probes. In order to verify the accuracy, inductors have been fabricated in a 0.35 µ m two-poly four-metal CMOS processes as shown in Figure 2 (a). The prototype chips also include the de-embed layouts to calibrate the on-wafer testing wiring and pads [6]. The S parameters were measured by a network analyzer and Cascade Microtech Probe Station using coplanar ground–signal–ground probes. The prediction error of fSR and SR R f atio with DCM is less than 10%, demonstrating the accuracy of the DCM. Thus, the equivalent capacitor of the inductor can be calculated, when we know the inductance, according to equation (2), (10) and (16), the ratio of the fSR of the optional two inductors with equivalent inductance Leq1, Leq2 and the equivalent capacitor Ceq1, Ceq2, respectively can be expressed as 1 2 2 2 1 1 SR L SR eq eq f L SR eq eq f L C Ratio f LC × = = × (18) The inductance equal approximately, Lunsymmetric ≈ Lsymmetric, if the current flows in the same direction along each adjacent conductor of the planar inductors with the same geometric parameters [such as Figure 1(a),(b),(c)], and the voltage differences between the adjacent turns of the DSPI and SSPI is larger than those of the SEPI, so Cm_m_se_symmetric ＝ Cm_m_diff_symmetric > Cm_m_se_spiral, but 4Cm_s_diff_symmetric ＝ Cm_s_se_symmetric ＝ Cm_m_se_spiral, therefore, fSR_diff_symmetric>fSR_se_spiral> fSR_se_symmetric and QSR_diff_symmetric>QSR_se_spiral> QSR_se_symmetric. This conclusion and equation (18) can offer design guidelines to select inductor and circuit configurations. The SR R f atio can be predicted and explained from equations (18). Compared with an equivalent single-ended configuration, experimental data
demonstrate that the differential inductor offers a 127% The lower the total parasitic capacitance has in an greater factor(maximum)and a much broader range inductor,the higher quality factor the inductor has.Two of operating frequencies.In figure 3(a) optimum designs of the symmetric planar on-chip Ratio (L)/Ratio (L2)=1.55.The Ratio inductor driven differentially have been developed. difference of the inductors with the same metal geometry C is reduced by decreasing the voltage parameters can be explained by the theory difference between the adjacent turns in figure 2(a) that Ratiodecreases with CC from equation through multilevel interconnects and by increasing the space of adjacent turns with larger voltage difference (17),shown in figure 3(c).The pn junction are formed at the interface between n+diffuse layer and p substrate cetnaemecrf8 and pn junction capacitor is serially connected with the stacked or 3D inductor has the voltage nearer signal oxide capacitance between the inductor and the silicon ground substrate,thus the equivalent Care greatly reduced, but C of both inductors are same,i.e.C is In addition,DCM can be high accurate at different structure inductors if the current crowding effects are variable,resulting in different Ratio The pattern considered in assumption 2) ground shielding made of the lowest layer metal make lower substrate loss than the pattern n+floating does, 4.Conclusions therefore, >at low frequency and A differentially driven symmetric inductor that enhances inductor quality factor on silicon RF ICs is firstly at high frequency due to interpreted by a distributed capacitance model (DCM) 02.ma Eior发 =6.4% for monolithic inductors.Design guidelines can be (7.0,15.9到 Eror2.=8.2% obtained from DCM Qtr(max） (575,124) Error =8.3% 10 Acknowledgments Q1,（ma) Error=9.6% The authors would like to thank Prof.Lingling Sun,Dr. 3.5,875 (b) Jiang Hu of the Hangzhou University of Electronic 分 20 Science Technology and Prof.Fuxiao Li,Jiangwei Shi Q2.（max of the Nanjing 55th Research Institute of Information 3.2,7.5 Industrial Department for measurements.This work was 138 supported by Shanghai Science Technology Committee (1375 under System-Design-Chip (SDC) program (NO. 72 037062019). 5 10 15 20 Frequency (GHz) Ratioc References (a) (c) [1]Burghartz,J.N.;Rejaei,B.,"On the design of RF Figure 3.(a)The same inductor with the pattern ground spiral inductors on silicon,"IEEE Transactions on shielding made of the lowest layer metal (L1)and Electron Devices,p.718-729(2003). pattern n+floating(L2);(b)The prediction errors with [2]Chia-Hsin Wu,Chih-Chun Tang and Shen-Iuan Liu. DCM.(c)Ratio decreases with RioCIC "Analysis of on-chip spiral inductors using the distributed capacitance model,"IEEE J.Solid-State Circuits,vol.38,p.1040-1044(2003). [3]A.Zolfaghari,A.Chan,and B.Razavi,"Stacked Inductors and Transformers in CMOS Technology," IEEE J.Solid-State Circuits,vol.36,p.620-628 (2001). [4]Chih-Chun Tang;Chia-Hsin Wu;Shen-Iuan Liu, m3/4 "Miniature 3-D inductors in standard CMOS process,"IEEE J.Solid-State Circuits,vol.37,p.471 -480(2002). (a) (b) [5]Zhangwen Tang,PhD dissertation,Fudan Univ., Figure 5.Two optimum symmetric on-chip inductors China(2004). driven differentially.(Note:123456 is current in inductor [6]Maget,J.,PhD dissertation,Dept.of Electr.Eng., flow direction,i.e.AC signal voltage profile;In mi,i Univ.of Bundeswehr,Neubiberg,Germany (2002). represents metal layer number)
demonstrate that the differential inductor offers a 127% greater Q factor (maximum) and a much broader range of operating frequencies. In figure 3(a) ( 1) / ( 2) SR SR R f f atio L Ratio L =1.55. The SR R f atio difference of the inductors with the same metal geometry parameters can be explained by the theory that SR R f atio decreases with _ __ / C C m m m s diff from equation (17), shown in figure 3(c). The pn junction are formed at the interface between n+ diffuse layer and p substrate, and pn junction capacitor is serially connected with the oxide capacitance between the inductor and the silicon substrate, thus the equivalent Cm s _ are greatly reduced, but Cm m_ of both inductors are same, i.e. _ __ / C C m m m s diff is variable, resulting in different SR R f atio . The pattern ground shielding made of the lowest layer metal make lower substrate loss than the pattern n+ floating does, therefore, L1 2 L Q Q se se > at low frequency and L1 2 L Q Q f . (a) (c) Figure 3. (a) The same inductor with the pattern ground shielding made of the lowest layer metal (L1) and pattern n+ floating (L2); (b) The prediction errors with DCM; (c) SR R f atio decreases with _ __ / Ratio C C C m m m s diff = . 1 1 3 2 2 1 3 3 5 2 4 6 1 4 5 2 6 3 m2 m3//4 m1 (a) (b) Figure 5. Two optimum symmetric on-chip inductors driven differentially. (Note:123456 is current in inductor flow direction, i.e. AC signal voltage profile; In mi, i represents metal layer number) The lower the total parasitic capacitance has in an inductor, the higher quality factor the inductor has. Two optimum designs of the symmetric planar on-chip inductor driven differentially have been developed. Cm m diff _ _ is reduced by decreasing the voltage difference between the adjacent turns in figure 2(a) through multilevel interconnects and by increasing the space of adjacent turns with larger voltage difference such as figure 2(b). According to equation (10), the Cm_m will be reduced if the lowest metal tracks layer of the stacked or 3D inductor has the voltage nearer signal ground. In addition, DCM can be high accurate at different structure inductors if the current crowding effects are considered in assumption 2). 4. Conclusions A differentially driven symmetric inductor that enhances inductor quality factor on silicon RF ICs is firstly interpreted by a distributed capacitance model (DCM) for monolithic inductors. Design guidelines can be obtained from DCM. Acknowledgments The authors would like to thank Prof. Lingling Sun, Dr. Jiang Hu of the Hangzhou University of Electronic Science & Technology and Prof. Fuxiao Li, Jiangwei Shi of the Nanjing 55th Research Institute of Information Industrial Department for measurements. This work was supported by Shanghai Science & Technology Committee under System-Design-Chip (SDC) program (NO. 037062019). References [1] Burghartz, J.N.; Rejaei, B., “On the design of RF spiral inductors on silicon,” IEEE Transactions on Electron Devices, p.718 – 729(2003). [2] Chia-Hsin Wu,Chih-Chun Tang and Shen-Iuan Liu, “ Analysis of on-chip spiral inductors using the distributed capacitance model,” IEEE J. Solid-State Circuits, vol.38, p. 1040-1044(2003). [3] A. Zolfaghari, A. Chan, and B. Razavi, “Stacked Inductors and Transformers in CMOS Technology,” IEEE J. Solid-State Circuits, vol. 36, p.620-628 (2001). [4] Chih-Chun Tang; Chia-Hsin Wu; Shen-Iuan Liu, “Miniature 3-D inductors in standard CMOS process,” IEEE J. Solid-State Circuits, vol. 37, p.471 – 480(2002). [5] Zhangwen Tang, PhD dissertation, Fudan Univ., China (2004). [6] Maget, J., PhD dissertation, Dept. of Electr. Eng., Univ. of Bundeswehr, Neubiberg, Germany (2002). _ 1 2 _ 1 2 6.4% 8.2% 8.3% 9.6% SR se SR fSR fSR L f L f se L Ratio L Ratio Error Error Error Error = = = = (b)