Vol.32,No.7 Journal of Semiconductors July 2011 A wideband CMOS VGLNA based on single-to-differential stage and resistive attenuator for TV tuners* Han Kefeng(韩科锋)，Tan Xi(谈熙)t,Tang Zhangwen(唐长文)，and Min Hao(闵昊) State Key Laboratory of ASIC&System,Fudan University,Shanghai 201203,China Abstract:A wideband CMOS variable gain low noise amplifier(VGLNA)based on a single-to-differential(S2D) stage and resistive attenuator is presented for TV tuner applications.Detailed analysis of input matching,noise figure(NF)and linearity for S2D is given.A highly linear passive resistive attenuator is proposed to provide 6 dB attenuation and input matching for each gain stage.The chip was fabricated by a 0.18 um 1P6M CMOS process, and the measurements show that the VGLNA covers a gain range over 36.4 dB and achieves a maximum gain of 21.3 dB,a minimum NF of 3.0 dB,an IIP3 of 0.9 dBm and an IIP2 of 26.3 dBm at high gain mode with a power consumption less than 10 mA from a 1.8 V supply. Key words:S2D;VGLNA;TV tuner;attenuator;wideband;noise canceling D0:10.1088/1674-4926/32/7/075003 EEACC:1220 1.Introduction drawn a lot of attention recently.With the proposal of a noise canceling technique in wideband LNAs,S2D is predicted to The frequency plan of a DVB-T poses a great challenge to- be a wideband low noise amplifier owing to noise cancella- wards the design of a LNA over such a wideband of frequency tion4.S2D is also very linear because of distortion cancella- (50-860 MHz)because a traditional narrow band LNA can- tion[4.71.As a result,this topology is well studied and adopted not cover the full band and the frequency of 50 MHz is also in some wideband receivers[8].The well-known S2D(also a nightmare in realizing an on-chip LC tank.A tunable LNA called balun-LNA or active balun)is composed of a common suffers from the same problem.As a result,a wideband LNA gate (CG)stage with a common source(CS)stage,as shown shows its superiority over other solutions.With the technique in Fig.1. of noise canceling proposed in 20031,the NF can be lowered to 2 dB,thus it is more practical to implement a wideband low 2.1.Input impedance noise receiver,such as a TV tunerl2]or SDR receiver[31. Designing a LNA for a TV tuner pose three problems.The The impedance of the S2D seen from the input can be cal- first one is the wideband requirement,which is no more a prob- culated as lem with the scaling property of CMOS technology-the mea- sured 3 dB bandwidth of LNA can be up to several giga hertzl7. CG C1 However,flicker noise is a problem at 50 MHz for CMOS tech- Cgs1 +CG nology.The second is a linearity problem because the input sig- nal without filtering contains more than 100 channels allocated Here,CG is the capacitor(not shown here)connected to to the received band.so the 2nd and 3rd inter-modulation dis- M1 for AC grounding and gmi is the transconductance of CG. tortions are much more serious than for narrow band receivers Assuming CG>Cgsi and C1>Ces2,then Zin is given as (e.g.GSM)[5,121.The last one is that the input signal level can be up to 0 dBm when receiving all of the channels each with CG stage (A F)CS stage (A,.F) S2D=CG+CS (A.FSaD) a strong power,so an attenuation strategy is generally consid- ered(2.6,14] This paper presents a highly linear,low-noise wideband VGLNA based on a S2D and resistive attenuator for TV tuner applications9.A new insight into noise in S2D is given.An attenuator employing an RF switch with fewer parasitics and M2 better linearity is presented. 2.Single-to-differential stage The S2D stage with a history of over 20 years[iol has Fig.1.CG and CS stages form a noise canceling S2D stage. Project supported by the National Science Funding of China(No.60876019),the National S&T Major Project of China(No.2009ZX0131- 002-003-02),the Shanghai Rising-Star Program,China (No.09QA1400300),the National Scientists and Engineers Service for Enterprise Program,China (No.2009GJC00046),and the ASIC State-Key Laboratory Funding.China (No.09MS007). Corresponding author.Email:tanxi@fudan.edu.cn Received 19 December 2010,revised manuscript received 2 March 2011 C2011 Chinese Institute of Electronics 075003-1
Vol. 32, No. 7 Journal of Semiconductors July 2011 A wideband CMOS VGLNA based on single-to-differential stage and resistive attenuator for TV tuners Han Kefeng(韩科锋), Tan Xi(谈熙) , Tang Zhangwen(唐长文), and Min Hao(闵昊) State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China Abstract: A wideband CMOS variable gain low noise amplifier (VGLNA) based on a single-to-differential (S2D) stage and resistive attenuator is presented for TV tuner applications. Detailed analysis of input matching, noise figure (NF) and linearity for S2D is given. A highly linear passive resistive attenuator is proposed to provide 6 dB attenuation and input matching for each gain stage. The chip was fabricated by a 0.18 m 1P6M CMOS process, and the measurements show that the VGLNA covers a gain range over 36.4 dB and achieves a maximum gain of 21.3 dB, a minimum NF of 3.0 dB, an IIP3 of 0.9 dBm and an IIP2 of 26.3 dBm at high gain mode with a power consumption less than 10 mA from a 1.8 V supply. Key words: S2D; VGLNA; TV tuner; attenuator; wideband; noise canceling DOI: 10.1088/1674-4926/32/7/075003 EEACC: 1220 1. Introduction The frequency plan of a DVB-T poses a great challenge towards the design of a LNA over such a wideband of frequency (50–860 MHz) because a traditional narrow band LNA cannot cover the full band and the frequency of 50 MHz is also a nightmare in realizing an on-chip LC tank. A tunable LNA suffers from the same problem. As a result, a wideband LNA shows its superiority over other solutions. With the technique of noise canceling proposed in 2003Œ1, the NF can be lowered to 2 dB, thus it is more practical to implement a wideband low noise receiver, such as a TV tunerŒ2 or SDR receiverŒ3 . Designing a LNA for a TV tuner pose three problems. The first one is the wideband requirement, which is no more a problem with the scaling property of CMOS technology — the measured 3 dB bandwidth of LNA can be up to several giga hertzŒ7 . However, flicker noise is a problem at 50 MHz for CMOS technology. The second is a linearity problem because the input signal without filtering contains more than 100 channels allocated to the received band, so the 2nd and 3rd inter-modulation distortions are much more serious than for narrow band receivers (e.g. GSM)Œ5; 12. The last one is that the input signal level can be up to 0 dBm when receiving all of the channels each with a strong power, so an attenuation strategy is generally consideredŒ2; 6; 14 . This paper presents a highly linear, low-noise wideband VGLNA based on a S2D and resistive attenuator for TV tuner applicationsŒ9. A new insight into noise in S2D is given. An attenuator employing an RF switch with fewer parasitics and better linearity is presented. 2. Single-to-differential stage The S2D stage with a history of over 20 yearsŒ10 has drawn a lot of attention recently. With the proposal of a noise canceling technique in wideband LNAs, S2D is predicted to be a wideband low noise amplifier owing to noise cancellationŒ4. S2D is also very linear because of distortion cancellationŒ4; 7. As a result, this topology is well studied and adopted in some wideband receiversŒ8. The well-known S2D (also called balun-LNA or active balun) is composed of a common gate (CG) stage with a common source (CS) stage, as shown in Fig. 1. 2.1. Input impedance The impedance of the S2D seen from the input can be calculated as Zin D CG Cgs1 C CG gm1 C sCgs1 C C1 Cgs2 C C1 sCgs21 : (1) Here, CG is the capacitor (not shown here) connected to M1 for AC grounding and gm1 is the transconductance of CG. Assuming CG Cgs1 and C1 Cgs2, then Zin is given as Fig. 1. CG and CS stages form a noise canceling S2D stage. * Project supported by the National Science Funding of China (No. 60876019), the National S&T Major Project of China (No. 2009ZX0131- 002-003-02), the Shanghai Rising-Star Program, China (No. 09QA1400300), the National Scientists and Engineers Service for Enterprise Program, China (No. 2009GJC00046), and the ASIC State-Key Laboratory Funding, China (No. 09MS007). Corresponding author. Email: tanxi@fudan.edu.cn Received 19 December 2010, revised manuscript received 2 March 2011 c 2011 Chinese Institute of Electronics 075003-1
J.Semicond.2011,32(7) Han Kefeng et al. C=515fF 1s(Cal+Ce） Co2=787 fF FeM=1+(Ec-1)4+(Fcs-14 C=9.1 pF -5 C=9.1 pF 5 NF 恩0 &m=18.9mS f(-3 dB) ++++++++ R=502 Noise suppression due to f(-10 dB) signal doubled in amplitude -15 -20 liga 1+g,R -25 2 R(C Cuo ≈3.1f" Noise cancellation for CG -30 500 1000 1500 2000 0.01 0.1 1 10 100 Frequency(MHz) (GHz) Fig.3.Simulated NF for CG,CS and S2D respectively. Fig.2.Impact of parasitic capacitance on S11. The first term in the polynomial means noise cancellation Zin [gm +s(Casl +Cg2)]1. for CG.The condition for noise canceling is solved to be (2) As shown in Fig.2,S11 depends on gmi at low frequency, Acs gm2R2 =gmIR1=ACG. (8) and parasitic capacitors Cs and Cas2 will deteriorate S when It can be learnt form Eg.(8)that all of the thermal noise the frequency increases.With Eq.(2),the bandwidth for the generated from the CG transistor is eliminated when the out- acceptable limit(e.g.-10 dB)of S1 is determined by puts of S2D are balanced.So Equation(7)can be modified to fBw,-I0dB≈ 11+gm1Rs (3) 3.12πRs(Cgs1+Cgs2) 8m1R+ FB2D=1+1 8m2R1 (9) So the parasitic capacitance of Cs and C2should be kept According to the noise analysis proposed in our previous small for wideband input matching,and scaled Lmin for MOS work,the noise factor of S2D can be expressed as transistors will be very helpful towards the matching band- width /w.-10B) FCAL.=1+Fco-1+Fes-1 4 4 2.2.Voltage gain =1+4+,1+为+1 (10) 4 The voltage gain(AcG)of CG is gmI Ri and for a CS stage gml R1 8m2Rs gm2R1 (Acs)is gm2 R2 regardless of the source impedance Rs.The The cancelled part is y1/4 according to Eqs.(9)and (10). small-signal voltage gain for a S2D stage is given by Actually,this part is a small portion of the overall noise,and a low noise factor is achieved for S2D mostly lies in the principle gmI R1 +8m2 R2 AcG +Acs (4) that useful signal doubles in amplitude at the differential out- 1+gmlRs 1+gmlRs puts while the unrelated noises should be added in power as shown in Fig.3. 2.3.Noise figure Moreover,if the ratio of R/R2 is defined as k in the con- With the condition of input matching,the noise factor for dition of Eq.(8),there is the CG stage is k R1/R2 =gm2/gm1. (11) FCG=1+y1+ 8m1R=1+n+ 4 (5) AcG Then the noise factor of S2D can be re-arranged as 如=1+++衣 1 and the noise factor of CS stage is (12) 4 Fcs =1+ayks*gno Rs42 (6) Here,A is the voltage gain for CG and CS with Eq.(8). When varying A and k,NF contours can be plotted in Fig.4. With a small-signal model for each noise source,the noise Compared to our previous work,three points should be factor for the S2D stage is expressed as highlighted in noise optimization.Firstly,the noise generated from CG cannot be fully cancelled because the noises of CG to the differential outputs are not the same in amplitude,though a Fs2D =1+(RsAcs -R1)y18m!+4R3Y28m2+4R1+4R2 CR high pass path is added to the CG stage.Secondly,accord- (AcG +Acs)2 Rs ing to the figure plotted in Fig.4,increasing power consump- (7) tion of the CS stage and gain will lower the NF effectively, 075003-2
J. Semicond. 2011, 32(7) Han Kefeng et al. Fig. 2. Impact of parasitic capacitance on S11. Zin gm1 C s Cgs1 C Cgs21 : (2) As shown in Fig. 2, S11 depends on gm1 at low frequency, and parasitic capacitors Cgs1 and Cgs2 will deteriorate S11 when the frequency increases. With Eq. (2), the bandwidth for the acceptable limit (e.g. –10 dB) of S11 is determined by fBW, –10dB 1 3:1 1 C gm1RS 2RS Cgs1 C Cgs2 : (3) So the parasitic capacitance of Cgs1 and Cgs2 should be kept small for wideband input matching, and scaled Lmin for MOS transistors will be very helpful towards the matching bandwidth fBW, –10dB Œ7 . 2.2. Voltage gain The voltage gain (ACG/ of CG is gm1R1 and for a CS stage (ACS/ is gm2R2 regardless of the source impedance RS. The small-signal voltage gain for a S2D stage is given by AS2D D gm1R1 C gm2R2 1 C gm1RS D ACG C ACS 1 C gm1RS : (4) 2.3. Noise figure With the condition of input matching, the noise factor for the CG stage is FCG D 1 C 1 C 4 gm1R1 D 1 C 1 C 4 ACG ; (5) and the noise factor of CS stage is FCS D 1 C 4 2 gm2RS C 4 gm2RSA2 : (6) With a small-signal model for each noise source, the noise factor for the S2D stage is expressed as FS2D D 1C .RSACS R1/ 2 1gm1 C 4R2 2 2gm2 C 4R1 C 4R2 .ACG C ACS/ 2 RS : (7) Fig. 3. Simulated NF for CG, CS and S2D respectively. The first term in the polynomial means noise cancellation for CG. The condition for noise canceling is solved to be ACS D gm2R2 D gm1R1 D ACG: (8) It can be learnt form Eq. (8) that all of the thermal noise generated from the CG transistor is eliminated when the outputs of S2D are balanced. So Equation (7) can be modified to FS2D D 1 C 1 gm1R1 C 2 gm2RS C 1 gm2R1 : (9) According to the noise analysis proposed in our previous workŒ9, the noise factor of S2D can be expressed as FCAL D 1 C FCG 1 4 C FCS 1 4 D 1 C 1 4 C 1 gm1R1 C 2 gm2RS C 1 gm2R1 : (10) The cancelled part is 1/4 according to Eqs. (9) and (10). Actually, this part is a small portion of the overall noise, and a low noise factor is achieved for S2D mostly lies in the principle that useful signal doubles in amplitude at the differential outputs while the unrelated noises should be added in powerŒ11 , as shown in Fig. 3. Moreover, if the ratio of R1/R2 is defined as k in the condition of Eq. (8), there is k D R1=R2 D gm2=gm1: (11) Then the noise factor of S2D can be re-arranged as FS2D D 1 C 1 A C 2 k C 1 Ak : (12) Here, A is the voltage gain for CG and CS with Eq. (8). When varying A and k, NF contours can be plotted in Fig. 4. Compared to our previous workŒ9, three points should be highlighted in noise optimization. Firstly, the noise generated from CG cannot be fully cancelled because the noises of CG to the differential outputs are not the same in amplitude, though a CR high pass path is added to the CG stage. Secondly, according to the figure plotted in Fig. 4, increasing power consumption of the CS stage and gain will lower the NF effectively, 075003-2
.Semicond..2011,32(7) Han Kefeng et al. 26 80 70 ▲Sim.llP3 ●Sim.IP2 60 50 Cal.IIP2 by Ref.[7] 40 Cal.IIP2 in g 30 20 10 0 Cal.IIP3 in gm -10 Cal.IIP3 by Ref.[7] 10 -20 0.4 0.5 0.6 0.7 0.8 0.9 V of CS stage (V) Fig.4.Calculated NF (in dB)contours for S2D core. Fig.5.IIP3 and IIP2 calculations from IV curves of the CS stage. so a 0.9 dB NF improvement is achieved compared to Ref.[9] in Fig.4.It is worth pointing out that the BW of S2D will be S2D core VDD-1.8 V small because the loads are increased for the exchange of gain enhancement.Finally,if the noise from current bias is added, M6 the contribution to the noise factor is y1gm3 Rs because it can be seen as an outside noise source to the S2D.The length L and over-drive voltage for this bias transistor should be kept large to lower the noise contribution.As a result,the overall M& expression for the noise factor is 1 +2 1 FS2D =1+- gmiRgmR gm +y38m3Rs.(13) 2.4.Linearity analysis IIP3 and IIP2 can be optimized from the /-V curves of the Fig.6.Schematic for the S2D stage with bias branch. CS stagel7,which dominates the non-linearity in S2D because the distortion in CG can be cancelled in the principle of noise cancellation.As stated in Ref.[13],the distortion mostly comes region.In Ref.[9],IIP2 performance (8.6 dBm)is not good from gm if the load resistance is small (such as 100 )So the enough without any optimization:actually.the specification expressions for IIP3 and IIP2 of a single CS stage are should be 20 dBm or morel7,so if a higher IIP2 is wanted,the bias voltage of CS should be chosen carefully,such as 0.71 V gml according to Fig.5,though IIP3 degrades a little but the value 10dB. (14) 8m2 is still above 0 dBm. 2.5.Phase and magnitude imbalance IIP3dBm 20 g +10dB (15) 3gm3 It is impractical to realize a perfect matching between CS and CG stages,so gain and phase errors do exist for the differ- Here,gmn represents the nth order derivation from I-V ential outputs.As stated in Section 2.3,the transconductance curve,that is of CS should be k times as the CG stage,so is the ratio of load 1 d"Ips resistance for CG over CS.Accordingly,a 3 dB bandwidth for gmn= n!dves (16) CG is much smaller than the CS stage,and thus the phase and Figure 5 shows the calculated results versus simulations gain error increase with frequency,and the parasitic capaci- for IIP2 and IIP3.The method in Ref.[7]overestimates the tance should be kept as small as possible for the layout. values of IIP2 by the technology used in this work while the 2.6.S2D circuit design gm-based method gives a relative accurate prediction versus simulation results. The schematic of S2D is given in Fig.6.MI with R1 forms A diode connected load will improve the linearity perfor- a CG stage for in-phase amplification and M2 with R2 is con- mance because of the post-correctioneffect11.However,the figured as the CS stage for anti-phase path.In order to reduce limitation is that the overdrive voltage should be kept large the impact of flicker noise at low frequency,a 0.3 um length enough for a higher gain and a lower NF.As a result,the large transistor is chosen.MI is of the DNW transistor to eliminate overdrive voltage will drive the CG transistor into the triode the body effect.M3 is a current bias for MI and the channel 075003-3
J. Semicond. 2011, 32(7) Han Kefeng et al. Fig. 4. Calculated NF (in dB) contours for S2D core. so a 0.9 dB NF improvement is achieved compared to Ref. [9] in Fig. 4. It is worth pointing out that the BW of S2D will be small because the loads are increased for the exchange of gain enhancement. Finally, if the noise from current bias is added, the contribution to the noise factor is 1gm3RS because it can be seen as an outside noise source to the S2D. The length L and over-drive voltage for this bias transistor should be kept large to lower the noise contribution. As a result, the overall expression for the noise factor is FS2D D 1 C 1 gm1R1 C 2 gm2RS C 1 gm2R1 C 3gm3RS: (13) 2.4. Linearity analysis IIP3 and IIP2 can be optimized from the I –V curves of the CS stageŒ7, which dominates the non-linearity in S2D because the distortion in CG can be cancelled in the principle of noise cancellation. As stated in Ref. [13], the distortion mostly comes from gm if the load resistance is small (such as 100 ). So the expressions for IIP3 and IIP2 of a single CS stage are IIP2dBm D 20 lg ˇ ˇ ˇ ˇ gm1 gm2 ˇ ˇ ˇ ˇ C 10 dB; (14) IIP3dBm D 20 lg ˇ ˇ ˇ ˇ ˇ s 4gm1 3gm3 ˇ ˇ ˇ ˇ ˇ C 10 dB: (15) Here, gm n represents the nth order derivation from I –V curve, that is gm n D 1 nŠ d n IDS dV n GS : (16) Figure 5 shows the calculated results versus simulations for IIP2 and IIP3. The method in Ref. [7] overestimates the values of IIP2 by the technology used in this work while the gm-based method gives a relative accurate prediction versus simulation results. A diode connected load will improve the linearity performance because of the post-correction effectŒ9; 11. However, the limitation is that the overdrive voltage should be kept large enough for a higher gain and a lower NF. As a result, the large overdrive voltage will drive the CG transistor into the triode Fig. 5. IIP3 and IIP2 calculations from IV curves of the CS stage. Fig. 6. Schematic for the S2D stage with bias branch. region. In Ref. [9], IIP2 performance (8.6 dBm) is not good enough without any optimization; actually, the specification should be 20 dBm or moreŒ7, so if a higher IIP2 is wanted, the bias voltage of CS should be chosen carefully, such as 0.71 V according to Fig. 5, though IIP3 degrades a little but the value is still above 0 dBm. 2.5. Phase and magnitude imbalance It is impractical to realize a perfect matching between CS and CG stages, so gain and phase errors do exist for the differential outputs. As stated in Section 2.3, the transconductance of CS should be k times as the CG stage, so is the ratio of load resistance for CG over CS. Accordingly, a 3 dB bandwidth for CG is much smaller than the CS stage, and thus the phase and gain error increase with frequency, and the parasitic capacitance should be kept as small as possible for the layout. 2.6. S2D circuit design The schematic of S2D is given in Fig. 6. M1 with R1 forms a CG stage for in-phase amplification and M2 with R2 is configured as the CS stage for anti-phase path. In order to reduce the impact of flicker noise at low frequency, a 0.3 m length transistor is chosen. M1 is of the DNW transistor to eliminate the body effect. M3 is a current bias for M1 and the channel 075003-3
J.Semicond.2011,32(7) Han Kefeng et al. (a) RF (b) High gain mode (c) High gain mode Low gain mode Low gain mode Fig.7.(a)Tapped attenuator.(b)Two gain modes front-end.(c)Two gain modes with S2D Feed-through the gate,which forms a high pass path,and the voltage at gate follows the input signal,so Vgs is a constant and the linear- ity improves.To gain a better linearity performance,a new RF switch is adopted,as shown in Fig.9.R is placed at the termi- nal of the body because Csb also introduces distortion and the threshold voltage related to Vsb too.The simulation results are shown in Fig.10 for the NMOS switch with dimensions of 100 um/0.18 um.When a two-tone signal with frequencies of 495 MHz and 505 MHz is applied to the different types of switch,a Fig.8.Schematic of the 6-step resistive attenuator 19 dB improvement of IM3 is achieved for the adopted switch to a traditional one at an input level of 0 dBm. length is set to 1 um.C is AC grounding for CG,and C2 is An additional benefit of this topology is that the input par- for DC blocking of M2.The bias voltages of CG and CS come asitic capacitance is greatly reduced due to resistors of R.and from diode-connected transistors.The CG draws 1.6 mA and Ro.According to the simulations,the equivalent input capaci- CS stage consumes 7.5 mA,and the total current of S2D in- tance is 392 fF for a switch of 100 um/0.18 um,when a resistor cluding the bias is less than 10 mA from the supply. Re is applied to the gate,the value is reduced to 212 fF,and the adopted topology shows a capacitance of less than 10 fF. 3.Attenuator design As shown in Fig.8,a great limitation for the gain range of the attenuator is the feed-through effect,which also degrades A passive attenuator can be either capacitive or resistive. the linearity performance simultaneously.The feed-through re- A capacitive network is sensitive to parasitics so the gain step lates to switch dimensions;a larger switch will bring in poor cannot be easily controlled.In addition.it needs an extra in- isolation performance but with improvement of linearity.So put matching parA resistive network can match the source the switches of S1-S7 are of different dimensions and a trade- impedance easily with an accurate gain step.Figure 7(a)shows offmust be made between linearity,gain steps and input match- a tapped resistive attenuator with one Gm-stage for each step, ing.The dimension of S1 should be much less than S7 because and the matching is done by attenuator,so the NF is not good the feed-through is most serious at this branch.The layout enoughl15).Figure 7(b)is composed of two gain modes;this also plays an important role in the proposed attenuator,espe- topology can achieve a low NF but with poor IIP2 perfor- cially for the source and drain connections in the switches,be- mance for the single-ended LNA[16].The scheme of this work cause the parasitic capacitance can also introduce serious feed- is shown in Fig.7(c);this is similar to Fig.7(b)but in replace through to the output.As a result,the gain range of this design of two S2Ds,so this choice has good performance in both noise is larger than our previous work]with a similar topology. and linearity] The presented attenuator is based on a R-2R ladder,as 4.Chip fabrication and measurements shown in Fig.8.In this way,the attenuator shows an input impedance of(2/3)R for each step,so R is 75 for a 50 This chip was fabricated by a SMIC 0.18 um 1P6M CMOS system.The switches are of a single NMOS transistor in the process.It accounts for an area of 0.54 mm2 with ESD pro- triode region,so the turn-on resistance is tected PADs and the core area of S2D is 0.06 mm2,as shown L in Fig.11. Ron = (17 The measured S1 for all gain steps are plotted in Fig.12. uCoxW (Vgs -VT) Even in the worst case,S11 is still below-10 dB from 50 MHz In a traditional way,a simple NMOS is applied with rel- to 1.2 GHz. atively good linearity when the signal is weak.However,as The gains of each step are firstly measured from 10 MHz the input level increases,the distortion increases dramatically to I GHz in Fig.13.Because a source follow buffer and an off- because Vgs is no more a constant and hence the switch be- chip balun with a ratio of 2:I are applied for testing,so an haves non-linearly.A modified schemel7l is with a resistor at extra 9 dB should be added to S21 to calculate voltage gains. 075003-4
J. Semicond. 2011, 32(7) Han Kefeng et al. Fig. 7. (a) Tapped attenuator. (b) Two gain modes front-end. (c) Two gain modes with S2D. Fig. 8. Schematic of the 6-step resistive attenuator. length is set to 1 m. C1 is AC grounding for CG, and C2 is for DC blocking of M2. The bias voltages of CG and CS come from diode-connected transistors. The CG draws 1.6 mA and CS stage consumes 7.5 mA, and the total current of S2D including the bias is less than 10 mA from the supply. 3. Attenuator design A passive attenuator can be either capacitive or resistive. A capacitive network is sensitive to parasitics so the gain step cannot be easily controlled. In addition, it needs an extra input matching partŒ14. A resistive network can match the source impedance easily with an accurate gain step. Figure 7(a) shows a tapped resistive attenuator with one Gm-stage for each step, and the matching is done by attenuator, so the NF is not good enoughŒ15. Figure 7(b) is composed of two gain modes; this topology can achieve a low NF but with poor IIP2 performance for the single-ended LNAŒ16. The scheme of this work is shown in Fig. 7(c); this is similar to Fig. 7(b) but in replace of two S2Ds, so this choice has good performance in both noise and linearityŒ9 . The presented attenuator is based on a R–2R ladder, as shown in Fig. 8. In this way, the attenuator shows an input impedance of (2/3)R for each step, so R is 75 for a 50 system. The switches are of a single NMOS transistor in the triode region, so the turn-on resistance is Ron D L CoxW Vgs VT : (17) In a traditional way, a simple NMOS is applied with relatively good linearity when the signal is weak. However, as the input level increases, the distortion increases dramatically because Vgs is no more a constant and hence the switch behaves non-linearly. A modified schemeŒ17 is with a resistor at the gate, which forms a high pass path, and the voltage at gate follows the input signal, so Vgs is a constant and the linearity improves. To gain a better linearity performance, a new RF switch is adopted, as shown in Fig. 9. Rb is placed at the terminal of the body because Csb also introduces distortion and the threshold voltage related to Vsb too. The simulation results are shown in Fig. 10 for the NMOS switch with dimensions of 100 m/0.18 m. When a two-tone signal with frequencies of 495 MHz and 505 MHz is applied to the different types of switch, a 19 dB improvement of IM3 is achieved for the adopted switch to a traditional one at an input level of 0 dBm. An additional benefit of this topology is that the input parasitic capacitance is greatly reduced due to resistors of Rg and Rb. According to the simulations, the equivalent input capacitance is 392 fF for a switch of 100 m/0.18 m, when a resistor Rg is applied to the gate, the value is reduced to 212 fF, and the adopted topology shows a capacitance of less than 10 fF. As shown in Fig. 8, a great limitation for the gain range of the attenuator is the feed-through effect, which also degrades the linearity performance simultaneously. The feed-through relates to switch dimensions; a larger switch will bring in poor isolation performance but with improvement of linearity. So the switches of S1–S7 are of different dimensions and a tradeoff must be made between linearity, gain steps and input matching. The dimension of S1 should be much less than S7 because the feed-through is most serious at this branch. The layout also plays an important role in the proposed attenuator, especially for the source and drain connections in the switches, because the parasitic capacitance can also introduce serious feedthrough to the output. As a result, the gain range of this design is larger than our previous workŒ9 with a similar topology. 4. Chip fabrication and measurements This chip was fabricated by a SMIC 0.18m 1P6M CMOS process. It accounts for an area of 0.54 mm2 with ESD protected PADs and the core area of S2D is 0.06 mm2 , as shown in Fig. 11. The measured S11 for all gain steps are plotted in Fig. 12. Even in the worst case, S11 is still below –10 dB from 50 MHz to 1.2 GHz. The gains of each step are firstly measured from 10 MHz to 1 GHz in Fig. 13. Because a source follow buffer and an offchip balun with a ratio of 2 : 1 are applied for testing, so an extra 9 dB should be added to S21 to calculate voltage gains. 075003-4
J.Semicond.2011,32(7) Han Kefeng et al. Traditional RF switch Modified RF switch Adopted RF switch 1.8V R 1.8V R.18V o o Fig.9.Analysis of different types of RF switches. 20 -8 0 -10 High gain mode (S2D) 1 order -12 1"ATT (S2D+ATT) -20 -14 40 Simple RF switch 16 -60 RF switch with gate resistor 18 -20 Other modes(ATT) -80 Proposed RF switch 22 -100 24 -120 20 -15 -10 -5 0 26 0.10.20.30.40.50.60.70.80.91.01.112 Input power (dBm) Frequency (GHz) Fig.10.Simulated IM3 for different types of RF switches. Fig.12.The measured S11 for each gain step. 30 High gain mode =855 MHz 20 10 -20 50-860MHz Gain loss at low gain mode 30 Fig.11.Die photo of VGLNA for a TV tuner 0.050.100.200.350.500.751.00 Frequency (GHz) The measured voltage gain at high gain mode is 21.3 dB with Fig.13.The measured gain of VGLNA for each gain step. a 3 dB bandwidth of 855 MHz.The gains at attenuation mode drop to low frequency due to a high pass pole by Ci and Zin in Figure 16 shows the measured performance versus gain Fig.7(c),thus C1 should be chosen as large as possible. steps.The maximum gain error is less than 0.4 dB at 450 MHz IIP3 and IIP2 are measured by two-tone methods.IIP3 is and NF increases from 3.0 to 39.0 dB for attenuation.IIP3 is 0.9 measured to be 0.9 dBm and IIP2 is 26.3 dBm at high gain dBm at high gain mode and it achieves a value of 23.5 dBm for mode,and the frequencies for the tones are given in Fig.14. maximum attenuation.It is also limited by the input switches in NF at high gain mode is also measured,as shown in front of the R-2R ladder.The reason is also applicable for IIP2 Fig.15.The NF is in accordance with the post-layout simula- with the peak value of 50.0 dBm for maximum attenuation. tion,especially for the low frequency band,and the measured Table 1 summarized the measurements of this proposed NF increases with frequency because of gain drops. VGLNA and comparisons are also made between similar 075003-5
J. Semicond. 2011, 32(7) Han Kefeng et al. Fig. 9. Analysis of different types of RF switches. Fig. 10. Simulated IM3 for different types of RF switches. Fig. 11. Die photo of VGLNA for a TV tuner. The measured voltage gain at high gain mode is 21.3 dB with a 3 dB bandwidth of 855 MHz. The gains at attenuation mode drop to low frequency due to a high pass pole by C1 and Zin in Fig. 7(c), thus C1 should be chosen as large as possible. IIP3 and IIP2 are measured by two-tone methods. IIP3 is measured to be 0.9 dBm and IIP2 is 26.3 dBm at high gain mode, and the frequencies for the tones are given in Fig. 14. NF at high gain mode is also measured, as shown in Fig. 15. The NF is in accordance with the post-layout simulation, especially for the low frequency band, and the measured NF increases with frequency because of gain drops. Fig. 12. The measured S11 for each gain step. Fig. 13. The measured gain of VGLNA for each gain step. Figure 16 shows the measured performance versus gain steps. The maximum gain error is less than 0.4 dB at 450 MHz and NF increases from 3.0 to 39.0 dB for attenuation. IIP3 is 0.9 dBm at high gain mode and it achieves a value of 23.5 dBm for maximum attenuation. It is also limited by the input switches in front of the R–2R ladder. The reason is also applicable for IIP2 with the peak value of 50.0 dBm for maximum attenuation. Table 1 summarized the measurements of this proposed VGLNA and comparisons are also made between similar 075003-5
.Semicond..2011,32(7) Han Kefeng et al. Table 1.Performance summary and comparisons. JSSC08l可 ASSCC'08[9] JSSC'0714 ISSCC'09l1可 CICC'05[18] This work CMOS process 65 nm 0.18um 0.18um 0.13um 130nm 0.18um Power supply (V) 1.2V 1.8 1.8 1.2 1.8 1.8 Bandwidth(GHz) 0.2-5.2 0.05-0.86 0.47-0.87 0.2-1 0.8-6 0.01-0.855 NF (dB)@Max gain 20 18-20 -15.1to21.3 Gain range(dB) 31 33 36.4 IIP3 (dBm) >0 2.6 -1.5 2.5 1 0.9-23.5 IIP2 (dBm) >20 8.6 >28 26.3-50.0 S11(dB) <-10 <-10 -11 <-10 <-10 <-10.4 Power(mA) 11.67 5.56 12.2 6.5 6.5 <10 Size(mm2) 0.009* 0.29 0.32 0.06* Core area * 50 50 25 IIP3 =0.9 dBm (wgP/gP) 40 0 IIP2 26.3 dBm -25 20 -50 Gain 75 Two-tone for IIP3:495 505 MHz Two-tone for IIP2:210&290 MHz -10 40-30 -20-100102030 40 -20 3 4 Input power (dBm) Gain step setting Fig.14.The measured IIP3 and IIP2 performance at high gain mode. Fig.16.Performance of this VGLNA with gain steps. 5.0 made for accurate linearity calculations and it can be learnt that 4.5 the transconductance still dominates the non-linearity in S2D (P For the adaptation of high signal level,a resistive attenuator is Measurements 4.0 presented with a 6 dB gain step and constant input matching. A RF switch has also been proposed to improve the linearity and reduce the parasitic capacitance.Measurements show that SIOU 3.5 this VGLNA achieves a minimum NF of 3.0 dB with a voltage gain of 21.3 dB,the IIP3 is 0.9 dBm and IIP2 is 26.3 dBm at 3.0 Flicker noise 心心 high gain mode.With the attenuation,the value IIP3 reaches Post-layout simulation 23.5 dBm and IIP2 is close to 50 dBm.The total area for this 2.5 VGLNA is 0.54 mm2(0.06 mm2 for S2D)and the power con- sumption is less than 10 mA from a 1.8 V supply. 2.0 0.05 0.10 0.200.350.500.751.00 Frequency (GHz) References Fig.15.The measured NF for VGLNA at high gain mode. [1]Bruccoleri F,Klumperink E A M,Nauta B.Wide-band CMOS low-noise amplifier exploiting thermal noise canceling.IEEE J works. Solid-State Circuits,2004,39(2):275 [2]Lerstaveesin S,Gupta M,Kang D,et al.A 48-860 MHz CMOS low-IF direct-conversion DTV tuner.IEEE J Solid-State Circuits. 5.Conclusion 2008.43(9):2013 [3]Giannini V,Nuzzol P.Soens C,et al.A 2 mm2 0.1-5 GHz In this paper,a wideband RF VGLNA has been presented. software-defined radio receiver in 45 nm digital CMOS.IEEE This VGLNA employs a S2D stage for single-to-differential ISSCO,2009:408 conversion with low noise and high linearity.The paper gives [4]Bruccoleri F.Wideband low noise amplifiers exploiting thermal a detailed noise analysis for S2D.Comparison has also been noise cancellation.PhD Thesis,2005 075003-6
J. Semicond. 2011, 32(7) Han Kefeng et al. Table 1. Performance summary and comparisons. JSSC’08Œ7 ASSCC’08Œ9 JSSC’07Œ14 ISSCC’09Œ16 CICC’05Œ18 This work CMOS process 65 nm 0.18 m 0.18 m 0.13 m 130 nm 0.18 m Power supply (V) 1.2 V 1.8 1.8 1.2 1.8 1.8 Bandwidth (GHz) 0.2–5.2 0.05–0.86 0.47–0.87 0.2–1 0.8–6 0.01–0.855 NF (dB) @ Max gain 20 18–20 –15.1 to 21.3 Gain range (dB) — 31 33 — — 36.4 IIP3 (dBm) > 0 2.6 –1.5 2.5 1 0.9–23.5 IIP2 (dBm) > 20 8.6 — > 28 4 26.3–50.0 S11 (dB) < –10 < –10 –11 < –10 < –10 < –10.4 Power (mA) 11.67 5.56 12.2 6.5 6.5 < 10 Size (mm2 ) 0.009* 0.29 0.32 — — 0.06* * Core area. Fig. 14. The measured IIP3 and IIP2 performance at high gain mode. Fig. 15. The measured NF for VGLNA at high gain mode. works. 5. Conclusion In this paper, a wideband RF VGLNA has been presented. This VGLNA employs a S2D stage for single-to-differential conversion with low noise and high linearity. The paper gives a detailed noise analysis for S2D. Comparison has also been Fig. 16. Performance of this VGLNA with gain steps. made for accurate linearity calculations and it can be learnt that the transconductance still dominates the non-linearity in S2D. For the adaptation of high signal level, a resistive attenuator is presented with a 6 dB gain step and constant input matching. A RF switch has also been proposed to improve the linearity and reduce the parasitic capacitance. Measurements show that this VGLNA achieves a minimum NF of 3.0 dB with a voltage gain of 21.3 dB, the IIP3 is 0.9 dBm and IIP2 is 26.3 dBm at high gain mode. With the attenuation, the value IIP3 reaches 23.5 dBm and IIP2 is close to 50 dBm. The total area for this VGLNA is 0.54 mm2 (0.06 mm2 for S2D) and the power consumption is less than 10 mA from a 1.8 V supply. References [1] Bruccoleri F, Klumperink E A M, Nauta B. Wide-band CMOS low-noise amplifier exploiting thermal noise canceling. IEEE J Solid-State Circuits, 2004, 39(2): 275 [2] Lerstaveesin S, Gupta M, Kang D, et al. A 48–860 MHz CMOS low-IF direct-conversion DTV tuner. IEEE J Solid-State Circuits, 2008, 43(9): 2013 [3] Giannini V, Nuzzo1 P, Soens C, et al. A 2 mm2 0.1–5 GHz software-defined radio receiver in 45 nm digital CMOS. IEEE ISSCC, 2009: 408 [4] Bruccoleri F. Wideband low noise amplifiers exploiting thermal noise cancellation. PhD Thesis, 2005 075003-6
J.Semicond.2011,32(7) Han Kefeng et al. [5]Im D,Nam I,Kim HT,et al.A wideband CMOS low noise ampli- GrawHill.2001 fier employing noise and IM2 distortion cancellation for a digital [121 Mastantuono D.Manstretta D.A low-noise active balun with TV tuner.IEEE J Solid-State Circuits,2009,44(3):686 IM2 cancellation for multi-band portable DVB-H receivers. [6]Gatta F,Gomez R,Shin Y J,et al.An embedded 65 nm CMOS IEEE ISSCC,2009:216 baseband IQ 48 MHz-1 GHz dual tuner for DOCSIS 3.0.IEEE [13]Kang S,Choi B,Kim B.Linearity analysis of CMOS for RF ap- J Solid-State Circuits,2009.44(12):3511 plication.IEEE Trans Microw Theory Tech,2003,51(3):972 [7]Blaakmeer S C.Klumperink E A M.Leenaert D M W.et al. [14]Xiao J,Mehr I,Silva-Martinez J,et al.A high dynamic range Wideband balun-LNA with simultaneous output balancing.noise CMOS variable gain amplifier for mobile DTV tuner.IEEE J canceling and distortion canceling.IEEE J Solid-State Circuits, Solid-State Circuits,2007,42(2):292 2008.43(6):1341 [15]Manstretta D,Dauphinee L.A highly linear broadband variable [8]Bagheri R,Mirzaei A,Chehrazi S,et al.An 800-MHz-6-GHz gain LNA for TV applications.IEEE CICC,2007:531 software-defined wireless receiver in 90-nm CMOS.IEEE J [16]Huang Y T,Yang C M,Huang S C,et al.A 1.2 V 67 mW 4 mm2 Solid-State Circuits,2006,41(12):2860 mobile ISDB-T tuner in 0.13 um CMOS.IEEE ISSCC,2009: [9]Han K,Zou L,Liao Y,et al.A wideband CMOS variable gain low 124 noise amplifier based on single-to-differential stage for TV tuner [17]Dogan H,Meyer R G,Niknejad A M.Analysis and design of RF applications.IEEE Asia Solid-state Circuit Conference,2008: CMOS attenuators.IEEE J Solid-State Circuits,2008,43(10): 457 2269 [10]Enrique F.Single input to differential output amplifier.US Patent,[18]Chehrazi S,Mirzaei A,Bagheri R,et al.A 6.5 GHz wideband No.4885550,1988 CMOS low noise amplifier for multi-band use.IEEE CICC. [11]Razavi B.Design of analog CMOS integrated circuits,US:Mc- 2005:801 075003-7
J. Semicond. 2011, 32(7) Han Kefeng et al. [5] Im D, Nam I, Kim H T, et al. A wideband CMOS low noise amplifier employing noise and IM2 distortion cancellation for a digital TV tuner. IEEE J Solid-State Circuits, 2009, 44(3): 686 [6] Gatta F, Gomez R, Shin Y J, et al. An embedded 65 nm CMOS baseband IQ 48 MHz–1 GHz dual tuner for DOCSIS 3.0. IEEE J Solid-State Circuits, 2009, 44(12): 3511 [7] Blaakmeer S C, Klumperink E A M, Leenaert D M W, et al. Wideband balun-LNA with simultaneous output balancing, noise canceling and distortion canceling. IEEE J Solid-State Circuits, 2008, 43(6): 1341 [8] Bagheri R, Mirzaei A, Chehrazi S, et al. An 800-MHz–6-GHz software-defined wireless receiver in 90-nm CMOS. IEEE J Solid-State Circuits, 2006, 41(12): 2860 [9] Han K, Zou L, Liao Y, et al. A wideband CMOS variable gain low noise amplifier based on single-to-differential stage for TV tuner applications. IEEE Asia Solid-state Circuit Conference, 2008: 457 [10] Enrique F. Single input to differential output amplifier. US Patent, No. 4885550, 1988 [11] Razavi B. Design of analog CMOS integrated circuits, US: McGrawHill, 2001 [12] Mastantuono D, Manstretta D. A low-noise active balun with IM2 cancellation for multi-band portable DVB-H receivers. IEEE ISSCC, 2009: 216 [13] Kang S, Choi B, Kim B. Linearity analysis of CMOS for RF application. IEEE Trans Microw Theory Tech, 2003, 51(3): 972 [14] Xiao J, Mehr I, Silva-Martinez J, et al. A high dynamic range CMOS variable gain amplifier for mobile DTV tuner. IEEE J Solid-State Circuits, 2007, 42(2): 292 [15] Manstretta D, Dauphinee L. A highly linear broadband variable gain LNA for TV applications. IEEE CICC, 2007: 531 [16] Huang Y T, Yang C M, Huang S C, et al. A 1.2 V 67 mW 4 mm2 mobile ISDB-T tuner in 0.13 m CMOS. IEEE ISSCC, 2009: 124 [17] Dogan H, Meyer R G, Niknejad A M. Analysis and design of RF CMOS attenuators. IEEE J Solid-State Circuits, 2008, 43(10): 2269 [18] Chehrazi S, Mirzaei A, Bagheri R, et al. A 6.5 GHz wideband CMOS low noise amplifier for multi-band use. IEEE CICC, 2005: 801 075003-7