Vol.32,No.2 Journal of Semiconductors February 2011 A 10-bit 80-MS/s opamp-sharing pipelined ADC with a switch-embedded dual-input MDAC* Yin Rui((尹容)，2，Liao Youchun(廖友春)2，Zhang Wei(张卫)'，and Tang Zhangwen((唐长文)l,t 1ASIC&System State Key Laboratory,Fudan University,Shanghai 201203,China 2Ratio Microelectronics Co.,Ltd,Shanghai 200433,China Abstract:A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18-um CMOS.An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique.The ADC achieves a peak SNDR of 60.1 dB(ENOB =9.69 bits)and a peak SFDR of 76 dB,while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth.The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply. Key words:pipelined ADC;opamp-sharing;low power,switch-embedded;dual-input MDAC D0:10.1088/1674-4926/32/2/025006 EEACC:1205:1265H:1280 sharing pipelined ADC utilizing a switch-embedded dual-input 1.Introduction MDAC that achieves a very high accuracy Applications used in many electronic systems,such as 2.Conventional opamp-sharing MDAC video decoder and a high-speed wire line and wireless com- munication,require high-resolution low-power Nyquist-rate Although opamp sharing technology can save nearly half analog-to-digital converters (ADCs).The specifications of of the power consumption,it is achieved at the cost of reso- conversion rates higher than 50 MSample/s and signal-to- lution reduction,since the conventional opamp-sharing ADC noise-and-distortion ratio (SNDR)in the range of 50-60 dB has two serious problems.First,because the opamp input sum- are usually required.To meet the applications of the integra- ming node is never reset,every input sample is affected by the tion of on-chip ADCs in the analog front-end with digital signal error voltage stored on the input capacitor due to the previ- processors,low-power ADCs are much preferred.In addition, ous sample.Thus it suffers from the memory effect,which can for the increasingly popular portable amusement,low power be considered as a signal-dependent OTA offset.To avoid consumption is even more crucial for extending the duration memory effects,the OTA inputs can be reset using a short du- of the system powered by a battery.Among many ADC archi- ration third phase.However,this would reduce the time avail- tectures,the pipelined ADC architecture has commonly been able for MDAC stage output settling.Second,there is a poten- employed to optimize speed,resolution.power dissipation and tial crosstalk path between two successive stages caused by the chip area,and has proved to be very efficient in meeting these parasitic capacitors of switches,which are used to implement requirements of high speed,high resolution,and low power opamp sharing.The conventional opamp-sharing MDAC with consumption.The efficiency mainly depends on the"pipeline" parasitic capacitance is shown in Fig.1.The signals in the cur- operation of the ADC stages.Each stage processes data from rent and successive stages,which appear at input nodes of the the previous stage as soon as its output is passed to the next shared opamp,will influence each other through the crosstalk stage for sampling.This means that the pipelined ADC can path.In addition,the opamp-sharing switches also introduce achieve one conversion in each clock cycle.The most efficient charge injection and signal-dependent resistance.These factors method that has been utilized to obtain significant power sav- degrade both the linearity and the signal-to-noise-ratio(SNR). ing is opamp sharing between multiplying digital-to-analogue To alleviate the non-resetting problem,the feedback signal converter(MDAC)stages in pipelined ADCs[1-51.That is be- polarity inverting(FSPI)is used to alternate the signal polar- cause the signal amplification in each MDAC stage is in al- ity,but it can only reduce the opamp offset by 2/321.To break ternate phases,so the operational transconductance amplifier the crosstalk path,isolation switches are added to tie the para- (OTA)only works in a half clock cycle.Therefore,half of sitic capacitance to ground in the sample phase,the SNDR is the opamps can be removed,leading to nearly 50%power improved only by 1-2 dB,but the added switches increase the reduction.However,the conventional opamp-sharing MDAC series resistance and the charge injection Although opamp has the issues of non-resetting and successive stage crosstalk. current reuse can solve the problems of non-resetting and To overcome these problems,this paper proposes an opamp- crosstalk path by using both NMOS and PMOS input differ- Project supported by the National Natural Science Foundation of China(No.60876019),the National S&T Major Project of China(No. 2009ZX0131-002-003-02),the Shanghai Rising-Star Program (No.09QA1400300),the National Scientists and Engineers Service for Enterprise Program,China(No.2009GJC00046),and the ASIC State-Key Laboratory Funding,China (No.09MS007). Corresponding author.Email:zwtang @fudan.edu.cn Received 12 August 2010,revised manuscript received 14 September 2010 C2011 Chinese Institute of Electronics 025006-1
Vol. 32, No. 2 Journal of Semiconductors February 2011 A 10-bit 80-MS/s opamp-sharing pipelined ADC with a switch-embedded dual-input MDAC Yin Rui(尹睿) 1; 2, Liao Youchun(廖友春) 2 , Zhang Wei(张卫) 1 , and Tang Zhangwen(唐长文) 1; 1ASIC & System State Key Laboratory, Fudan University, Shanghai 201203, China 2Ratio Microelectronics Co., Ltd, Shanghai 200433, China Abstract: A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18-m CMOS. An opampsharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB (ENOB = 9.69 bits) and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply. Key words: pipelined ADC; opamp-sharing; low power; switch-embedded; dual-input MDAC DOI: 10.1088/1674-4926/32/2/025006 EEACC: 1205; 1265H; 1280 1. Introduction Applications used in many electronic systems, such as video decoder and a high-speed wire line and wireless communication, require high-resolution low-power Nyquist-rate analog-to-digital converters (ADCs). The specifications of conversion rates higher than 50 MSample/s and signal-tonoise-and-distortion ratio (SNDR) in the range of 50–60 dB are usually required. To meet the applications of the integration of on-chip ADCs in the analog front-end with digital signal processors, low-power ADCs are much preferred. In addition, for the increasingly popular portable amusement, low power consumption is even more crucial for extending the duration of the system powered by a battery. Among many ADC architectures, the pipelined ADC architecture has commonly been employed to optimize speed, resolution, power dissipation and chip area, and has proved to be very efficient in meeting these requirements of high speed, high resolution, and low power consumption. The efficiency mainly depends on the “pipeline” operation of the ADC stages. Each stage processes data from the previous stage as soon as its output is passed to the next stage for sampling. This means that the pipelined ADC can achieve one conversion in each clock cycle. The most efficient method that has been utilized to obtain significant power saving is opamp sharing between multiplying digital-to-analogue converter (MDAC) stages in pipelined ADCsŒ15. That is because the signal amplification in each MDAC stage is in alternate phases, so the operational transconductance amplifier (OTA) only works in a half clock cycle. Therefore, half of the opamps can be removed, leading to nearly 50% power reduction. However, the conventional opamp-sharing MDAC has the issues of non-resetting and successive stage crosstalk. To overcome these problems, this paper proposes an opampsharing pipelined ADC utilizing a switch-embedded dual-input MDAC that achieves a very high accuracy. 2. Conventional opamp-sharing MDAC Although opamp sharing technology can save nearly half of the power consumption, it is achieved at the cost of resolution reduction, since the conventional opamp-sharing ADC has two serious problems. First, because the opamp input summing node is never reset, every input sample is affected by the error voltage stored on the input capacitor due to the previous sample. Thus it suffers from the memory effect, which can be considered as a signal-dependent OTA offsetŒ1. To avoid memory effects, the OTA inputs can be reset using a short duration third phase. However, this would reduce the time available for MDAC stage output settling. Second, there is a potential crosstalk path between two successive stages caused by the parasitic capacitors of switches, which are used to implement opamp sharing. The conventional opamp-sharing MDAC with parasitic capacitance is shown in Fig. 1. The signals in the current and successive stages, which appear at input nodes of the shared opamp, will influence each other through the crosstalk path. In addition, the opamp-sharing switches also introduce charge injection and signal-dependent resistance. These factors degrade both the linearity and the signal-to-noise-ratio (SNR). To alleviate the non-resetting problem, the feedback signal polarity inverting (FSPI) is used to alternate the signal polarity, but it can only reduce the opamp offset by 2/3Œ2. To break the crosstalk path, isolation switches are added to tie the parasitic capacitance to ground in the sample phase, the SNDR is improved only by 1–2 dB, but the added switches increase the series resistance and the charge injectionŒ3. Although opamp current reuse can solve the problems of non-resetting and crosstalk path by using both NMOS and PMOS input differ- * Project supported by the National Natural Science Foundation of China (No. 60876019), the National S&T Major Project of China (No. 2009ZX0131-002-003-02), the Shanghai Rising-Star Program (No. 09QA1400300), the National Scientists and Engineers Service for Enterprise Program, China (No. 2009GJC00046), and the ASIC State-Key Laboratory Funding, China (No. 09MS007). Corresponding author. Email: zwtang@fudan.edu.cn Received 12 August 2010, revised manuscript received 14 September 2010 c 2011 Chinese Institute of Electronics 025006-1
1.Semicond.2011,32(2) Yin Rui et al. Φ1 2 Φ1 2 sub sub ADC DAC sub sub DAC Fig.1.Conventional opamp-sharing MDAC. non-overlapping time M13 1Φ1 iΦ1D 1D2 2D iDn overlapping time b2D加 IDn 2Dn M6 M& M2 M15 M16 CMFB Fig.2.Proposed two-input-differential-pair gain-boosting telescopic amplifier with clock timing. ential pairs in shared opamps,the capacitive level shifter in- 3.1.Switch-embedded OTA creases the design complexity and the PMOS input differential pair decreases the power efficiency[41.In Ref.[5],the OTA em- The topology of the proposed switch-embedded gain- ploys dual-NMOS input differential pairs but needs two differ- boosting telescopic OTA with dual NMOS differential input ent common-mode input voltages for resetting.This methodol- pairs is shown in Fig.2.Each input transistor(M1-M4)is con- ogy is restricted to telescopic cascode OTAs,which have most nected with an embedded NMOS switch(M5-M8)in series. power efficiency and result in loss of output swing.The adding The switch is on when its corresponding control signal (i.e. switch also reduced the OTA DC gain AoL and GBW in 2 due IDn and 2Dn)is high,and is off when the control signal to the on-resistance of the switches. is low.To achieve a wide swing,a stable high-swing bias cir- cuit is employed for the proposed gain-boosting telescopic am- 3.Proposed ADC with dual-input MDAC plifier,as shown in Fig.3.To match the switch transistors in the opamp,a corresponding NMOS switch is added with its To get rid of the problems of non-resetting and succes- gate connected to the VDD.The opamp achieves 1.6-Vpp dif- sive stage crosstalk,this paper proposes an opamp-sharing ferential signal swing from a 1.8-V power supply considering pipelined ADC using a switch-embedded MDAC with dual process,temperature and power supply variations.Because of NMOS differential input pairs current-reuse OTA controlled the delicate biasing,the overdrive voltage of the NMOS switch by two-phase overlapping clocks. transistors is constant,thus the Ron of each switch only has a 025006-2
J. Semicond. 2011, 32(2) Yin Rui et al. Φ1 Φ2 C4 C1 C3 C2 sub DAC sub ADC Φ1 Φ1 Φ2 Φ1 Φ2 Φ2 sub ADC sub DAC Vout Vin Φ2 Φ1 Fig. 1. Conventional opamp-sharing MDAC. Vb1 Vb4 Vinn, a Vinp, b Vinp, a Vinn, b Φ2Dn Φ1Dn Φ1Dn Φ2Dn M3 M1 M2 M4 M5 M6 M8 M9 M10 M11 M12 M13 M14 M15 M16 CMFB Voutn Voutp Vnc Vpc Φ1 Φ1D Φ1Dn Φ2 Φ2D Φ2Dn overlapping time non-overlapping time VSS VDD M7 Fig. 2. Proposed two-input-differential-pair gain-boosting telescopic amplifier with clock timing. ential pairs in shared opamps, the capacitive level shifter increases the design complexity and the PMOS input differential pair decreases the power efficiencyŒ4. In Ref. [5], the OTA employs dual-NMOS input differential pairs but needs two different common-mode input voltages for resetting. This methodology is restricted to telescopic cascode OTAs, which have most power efficiency and result in loss of output swing. The adding switch also reduced the OTA DC gain AOL and GBW in ˚2 due to the on-resistance of the switches. 3. Proposed ADC with dual-input MDAC To get rid of the problems of non-resetting and successive stage crosstalk, this paper proposes an opamp-sharing pipelined ADC using a switch-embedded MDAC with dual NMOS differential input pairs current-reuse OTA controlled by two-phase overlapping clocks. 3.1. Switch-embedded OTA The topology of the proposed switch-embedded gainboosting telescopic OTA with dual NMOS differential input pairs is shown in Fig. 2. Each input transistor (M1–M4) is connected with an embedded NMOS switch (M5–M8) in series. The switch is on when its corresponding control signal (i.e., ˆ1Dn and ˆ2Dn) is high, and is off when the control signal is low. To achieve a wide swing, a stable high-swing bias circuit is employed for the proposed gain-boosting telescopic amplifier, as shown in Fig. 3. To match the switch transistors in the opamp, a corresponding NMOS switch is added with its gate connected to the VDD. The opamp achieves 1.6-Vpp differential signal swing from a 1.8-V power supply considering process, temperature and power supply variations. Because of the delicate biasing, the overdrive voltage of the NMOS switch transistors is constant, thus the Ron of each switch only has a 025006-2
J.Semicond.2011,32(2) Yin Rui et al. Fig.3.Wide-swing bias circuit of the shared opamp. S-A Φ1D 2D S-B 1D Φ2D 2D Φ1 9Φ1Dn Φ1D 2 sub sub sub sub ADC DAC ADC DAC n.b 2D Φ1 Φ1D Φ1D 2D C 1D 2D Fig.4.Proposed opamp-sharing MDAC small invariable resistance and will not affect the performance period of 1Dn and 2Dn,the opamp is working on dual- of the shared opamp. input-on mode.During this time,both pairs of input are active and have a half current,but are still in saturation.When 2D 3.2.Dual-input MDAC is high,the signal pathway is on.Meanwhile,Vinp,b and Vim.b are disabled since 2Dn goes low,Vinp.a and Vn.a are the only The proposed 1.5-bit opamp-sharing MDAC using the active inputs and the opamp is working on holding mode for switch-embedded amplifier is shown in Fig.4.When I is stage-A. high,both Vinp.a and Vinn,a are connected to the common-mode input voltage Viem for resetting.When ID is high,the sam- Since both input pairs are reset to a common-mode input pling switches are on and Cia and C2a sample the input signal voltage alternately,the memory effect is completely eliminated for stage-A while the opamp is working on holding mode for without needing any additional clock phase.Furthermore,the stage-B.At the end of the sample process,1 turns to low be- opamp-sharing switches are embedded into the opamp instead foreΦlD,which is so called“bottom plate sampling”.At the of in series between the sampling capacitors and the opamp moment after the bottom plate sampling switch is completely inputs,therefore the crosstalk path is avoided.In addition, off and the previous signal is still holding,the sub-ADC com- since the opamp-sharing switches do not connect directly to pares the result,passes the 2-bit digital codes to the sub-DAC the opamp input transistors,the charge injection and the signal- and the digital error correction module.During the overlapping dependent resistance do not exist for the same reason. 025006-3
J. Semicond. 2011, 32(2) Yin Rui et al. Vnc Vpc Vb3 Vicm VDD VDD I ref1 I ref2 Vb4 Vb1 Vb2 VSS Fig. 3. Wide-swing bias circuit of the shared opamp. sub DAC Φ1Dn Φ2Dn C1a C3a Φ1D Φ1D Φ2D Vinp C2a C4a Φ1D Vinn Vicm Φ1 Φ1 Voutp Voutn Vinp, a Vinn, b Vinn, a C1b C3b Φ2D C2b C4b Φ2D Φ2 Φ1D Φ2D S-A S-B Φ2D Φ2D Φ1D Φ1D sub ADC sub DAC sub ADC Vicm Φ2 Vinn, b V Vinp, b inp, b Fig. 4. Proposed opamp-sharing MDAC small invariable resistance and will not affect the performance of the shared opamp. 3.2. Dual-input MDAC The proposed 1.5-bit opamp-sharing MDAC using the switch-embedded amplifier is shown in Fig. 4. When ˆ1 is high, both Vinp; a and Vinn; a are connected to the common-mode input voltage Vicm for resetting. When ˆ1D is high, the sampling switches are on and C1a and C2a sample the input signal for stage-A while the opamp is working on holding mode for stage-B. At the end of the sample process, ˆ1 turns to low before ˆ1D, which is so called “bottom plate sampling”. At the moment after the bottom plate sampling switch is completely off and the previous signal is still holding, the sub-ADC compares the result, passes the 2-bit digital codes to the sub-DAC and the digital error correction module. During the overlapping period of ˆ1Dn and ˆ2Dn, the opamp is working on dualinput-on mode. During this time, both pairs of input are active and have a half current, but are still in saturation. When ˆ2D is high, the signal pathway is on. Meanwhile, Vinp; b and Vinn; b are disabled since ˆ2Dn goes low, Vinp; a and Vinn; a are the only active inputs and the opamp is working on holding mode for stage-A. Since both input pairs are reset to a common-mode input voltage alternately, the memory effect is completely eliminated without needing any additional clock phase. Furthermore, the opamp-sharing switches are embedded into the opamp instead of in series between the sampling capacitors and the opamp inputs, therefore the crosstalk path is avoided. In addition, since the opamp-sharing switches do not connect directly to the opamp input transistors, the charge injection and the signaldependent resistance do not exist for the same reason. 025006-3
1.Semicond.2011,32(2) Yin Rui et al. MDAC3 MDAC5 MDAC7 2-b S/H Flash MDAC2 MDAC4 MDAC6 MDAC8 ADC ADC h 2b /18b Clock Digital Correction Logic Generator 10 Fig.5.Block diagram of the proposed pipelined ADC architecture. mm igital Correction Technology 0.18-um CMOS 9.69 bit 8 MHz Input Resolution 10 bit ENOB 9.63 bit 39.5 MHz Input Conversion rate 80 MS/s 9.64 bit 60 MHz Input Input range 1.6 Vpp,diff SFDR 76.0 dB 39.5 MHz Input Supply voltage 1.8V Peak DNL +0.37/-0.23LSB Power 32.4 mW (Core:28 mW) Peak INL +0.53/-0.87LSB Active area 1.4 mm2 (Core:1.1 mm2) FOM 0.42 pJ/step Fig.6.Die micrograph and performance summary. 3.3.Timing consideration or the quantization process.On the one hand,during the over- lapping period,the shared opamp has not been working for sig- The two-phase non-overlapping clock is always used in a nal settling until 1D/2D is high.Signal transfer and settling pipelined ADC but is not suitable for controlling the opamp- will not be affected because there is no charge leakage path and sharing switches in the proposed OTA.If the non-overlapping two input differential pairs will not affect each other.Further. clocks 1D and 2D are used,during the non-overlapping pe- the opamp input transistors in saturation region in the overlap- riod,both pairs of opamp input transistors will be disabled, ping period can improve the settling time.On the other hand. so there is no current path to the ground for PMOS transis- the comparing operation has already achieved at a moment be- tor branches (M11-M14).The output voltages of the shared tween the falling edges of I and ID,so the overlapping opamp will shift to a much higher level above the common out- working has no adverse effect on the quantization process. put voltage during this period.In the worst case,PMOS tran- sistors may enter into the linear region and the holding phase of 3.4.ADC architecture MDAC stages would waste some time in the large-signal slew- rate.Therefore,the proposed opamp uses two-phase overlap- A common pipelined ADC configuration is used in this ping clocks (1Dn and 2Dn)to avoid this problem.Since work,as shown in Fig.5.The ADC is composed of an S/H IDn and 2Dn are already used for CMOS switches,no ad- circuit,eight 1.5-bit MDACs using four shared opamps,and ditional clock phase is needed.The use of an overlapping work- a 2-bit flash ADC as the last stage.The ADC also has an on- ing scheme will not affect the fidelity of signal transfer,settling chip bandgap reference,a distributed clock generation circuit, 025006-4
J. Semicond. 2011, 32(2) Yin Rui et al. Clock Digital Correction Logic Generator Vinp Vinn 18b 10b MDAC1 & MDAC2 S/H 2b 2-b Flash ADC 1.5-b Flash ADC 2b 1.5-b Flash ADC 2b MDAC3 & MDAC4 1.5-b Flash ADC 2b Flash ADC 2b MDAC5 & MDAC6 1.5-b 1.5-b Flash ADC 2b 1.5-b Flash ADC 2b MDAC7 & MDAC8 1.5-b Flash ADC 2b 1.5-b Flash ADC 2b Fig. 5. Block diagram of the proposed pipelined ADC architecture. Fig. 6. Die micrograph and performance summary. 3.3. Timing consideration The two-phase non-overlapping clock is always used in a pipelined ADC but is not suitable for controlling the opampsharing switches in the proposed OTA. If the non-overlapping clocks ˆ1D and ˆ2D are used, during the non-overlapping period, both pairs of opamp input transistors will be disabled, so there is no current path to the ground for PMOS transistor branches (M11–M14). The output voltages of the shared opamp will shift to a much higher level above the common output voltage during this period. In the worst case, PMOS transistors may enter into the linear region and the holding phase of MDAC stages would waste some time in the large-signal slewrate. Therefore, the proposed opamp uses two-phase overlapping clocks (ˆ1Dn and ˆ2Dn) to avoid this problem. Since ˆ1Dn and ˆ2Dn are already used for CMOS switches, no additional clock phase is needed. The use of an overlapping working scheme will not affect the fidelity of signal transfer, settling or the quantization process. On the one hand, during the overlapping period, the shared opamp has not been working for signal settling until ˆ1D/ˆ2D is high. Signal transfer and settling will not be affected because there is no charge leakage path and two input differential pairs will not affect each other. Further, the opamp input transistors in saturation region in the overlapping period can improve the settling time. On the other hand, the comparing operation has already achieved at a moment between the falling edges of ˆ1 and ˆ1D, so the overlapping working has no adverse effect on the quantization process. 3.4. ADC architecture A common pipelined ADC configuration is used in this work, as shown in Fig. 5. The ADC is composed of an S/H circuit, eight 1.5-bit MDACs using four shared opamps, and a 2-bit flash ADC as the last stage. The ADC also has an onchip bandgap reference, a distributed clock generation circuit, 025006-4
.Semicond.2011,32(2) Yin Rui et al. 0 80 =8 MHz -20 =80 MHz SFDR =72.1 dB 40/ SNDR =60.1 dB 75 ENOB =9.69 bit SFDR -60 1 70 -80 ---1------ 65 -100 0 10 20 30 40 SNR 60 -20 =39.5 MHz -----7 ------sFDR=76.0dB 55 40 --------- -SNDR =59.8 dB 20 40 60 80 60-----}----- 1 ENOB =9.63 bit 9.8 -80 80 MHz 1000 FKMm 10 20 30 40 (q) 9.6 Frequency (MHz) Fig.7.Measured FFT plot at a sample frequency of 80 MHz with input signals of 8 MHz and 39.5 MHz. a digital error correction circuit and voltage buffers. 20 40 80 The input-sampling switch in the S/H circuit is boot- 60 Input Frequency (MHz) strapped,while the bottom-sampling switch is a symmetrical gate-bootstrapping one to increase linearityl3).Capacitor sizes 80 f8 MHz are carefully chosen to meet matching and noise requirements. 75 By using the technique of redundant-signed-digit(RSD) e ◆ correction,which allows a large offset error for a simple 0 dynamic latch-type comparator without static power con- SFDR sumption,the power consumption could be reduced further. 65 The comparators in all flash ADCs employ a high-speed SNR 60 mismatch-insensitive dynamic latch-type circuit without any pre-amplifier. 55 0 40 60 80 100 9.8 4.Measurement results 8 MHz The ADC is fabricated in a 0.18-um CMOS process with 9.6H a core die size of 1.1 mm2.To maintain the characteristics of 邑 full Nyquist input bandwidth,the differential input and output 9.4 signal paths are carefully designed and simulated on the cir- cuit and layout-level.For better isolation,analog and digital 9.2 were placed far from each other with guard rings,respectively. MIM capacitors were also well matched.The die micrograph and performance summary are shown in Fig.6.The chip con- 900 40 60 80 100 sumes 28 mW from a 1.8 V power supply at 80 MSample/s,not Sample Frequency (MHz) including the bandgap reference and voltage buffers.Figure 7 shows the FFT plot for the input frequencies of 8 MHz and Fig.8.SFDR,SNR and ENOB versus input frequency and sample 39.5 MHz at a 80 MHz sample rate.The spurious free dynamic frequency range(SFDR),SNR and effective number of bits(ENOB)ver- sus input frequency are shown in Fig.8.The ADC achieves of Power/(2ENOB x fs),the ADC achieves 0.42 pJ/conversion- a peak ENOB of 9.69 bits and a peak SFDR of 76 dB,while step maintaining more than 9.6 ENOB for the full Nyquist input bandwidth.When the input frequency is close to sample rate, 5.Conclusion the ADC still maintains 9.47 ENOB.Figure 8 also provides SFDR,SNR and ENOB versus sample frequency at an input This paper describes a 10-bit 80-MS/s pipelined ADC frequency of 8 MHz.When the sample rate rises to 100 MHz, using the proposed switch-embedded opamp-sharing MDAC there is still 9.1 ENOB.The measured SNDR and SFDR are based on a dual NMOS input pairs current-reuse opamp.Com- better than other recently published works of 10-bit pipelined pared with a traditional opamp-sharing ADC,the proposed ADCs2-51,as shown in Fig.9.Figure 10 shows the differential opamp-sharing method achieved an improved accuracy by nonlinearity (DNL)of +0.37/-0.23 LSB and the integral non- eliminating the memory effect and crosstalk path without any linearity (INL)of +0.53/-0.87 LSB.Using a figure-of-merit additional power,area consumption and clock phase.The mea- 025006-5
J. Semicond. 2011, 32(2) Yin Rui et al. 0 10 20 30 40 -100 -80 -60 -40 -20 0 0 10 20 30 40 -100 -40 -20 0 -80 -60 dB dB Frequency (MHz) f in = 8 MHz SFDR = 72.1 dB SNDR = 60.1 dB ENOB = 9.69 bit f in = 39.5 MHz SFDR = 76.0 dB SNDR = 59.8 dB ENOB = 9.63 bit Fig. 7. Measured FFT plot at a sample frequency of 80 MHz with input signals of 8 MHz and 39.5 MHz. a digital error correction circuit and voltage buffers. The input-sampling switch in the S/H circuit is bootstrapped, while the bottom-sampling switch is a symmetrical gate-bootstrapping one to increase linearityŒ3. Capacitor sizes are carefully chosen to meet matching and noise requirements. By using the technique of redundant-signed-digit (RSD) correction, which allows a large offset error for a simple dynamic latch-type comparator without static power consumption, the power consumption could be reduced further. The comparators in all flash ADCs employ a high-speed mismatch-insensitive dynamic latch-type circuit without any pre-amplifier. 4. Measurement results The ADC is fabricated in a 0.18-m CMOS process with a core die size of 1.1 mm2 . To maintain the characteristics of full Nyquist input bandwidth, the differential input and output signal paths are carefully designed and simulated on the circuit and layout-level. For better isolation, analog and digital were placed far from each other with guard rings, respectively. MIM capacitors were also well matched. The die micrograph and performance summary are shown in Fig. 6. The chip consumes 28 mW from a 1.8 V power supply at 80 MSample/s, not including the bandgap reference and voltage buffers. Figure 7 shows the FFT plot for the input frequencies of 8 MHz and 39.5 MHz at a 80 MHz sample rate. The spurious free dynamic range (SFDR), SNR and effective number of bits (ENOB) versus input frequency are shown in Fig. 8. The ADC achieves a peak ENOB of 9.69 bits and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. When the input frequency is close to sample rate, the ADC still maintains 9.47 ENOB. Figure 8 also provides SFDR, SNR and ENOB versus sample frequency at an input frequency of 8 MHz. When the sample rate rises to 100 MHz, there is still 9.1 ENOB. The measured SNDR and SFDR are better than other recently published works of 10-bit pipelined ADCsŒ25, as shown in Fig. 9. Figure 10 shows the differential nonlinearity (DNL) of +0.37/–0.23 LSB and the integral nonlinearity (INL) of +0.53/–0.87 LSB. Using a figure-of-merit Fig. 8. SFDR, SNR and ENOB versus input frequency and sample frequency. of Power/(2ENOB fs/, the ADC achieves 0.42 pJ/conversionstep. 5. Conclusion This paper describes a 10-bit 80-MS/s pipelined ADC using the proposed switch-embedded opamp-sharing MDAC based on a dual NMOS input pairs current-reuse opamp. Compared with a traditional opamp-sharing ADC, the proposed opamp-sharing method achieved an improved accuracy by eliminating the memory effect and crosstalk path without any additional power, area consumption and clock phase. The mea- 025006-5
J.Semicond.2011,32(2) Yin Rui et al. 61 60 ●This work 59 Ref.[2] 8 Ref.[5] Ref.[3] 55 Ref.[4] 00 0.2 0.4 0.6 0.8 1.0 fogu/fpe FOM SFDR ENOB Ref. Process (V (MS/s) (pJ /step (dB) (bit) Ref.[2] 0.18 um DGO CMOS 3 80 1.21 74 9.47 Ref.[3] 0.18 um CMOS 1.8 30 1.19 69 9.24 Ref.[4] 0.18 um CMOS 1.8 50 0.61 70 9.2 Ref.[5] 0.18 um CMOS 1.8 50 0.29 74 9.3 This work 0.18 um CMOS 1.8 80 0.42 76 9.69 Fig.9.SNDR and other performance comparisons with some recently published works. sured SNDR and SFDR are 60.1 dB and 76 dB,respectively. [2]Min B,Kim P,Boisvert D,et al.A69 mW 10 b80 MS/s pipelined This technique is also suitable for other ADC architectures. CMOS ADC.ISSCC Digest of Technical Papers,2003:324 such as multi-bit per stage and multi-channel for achieving [3]Li J,Zeng X,Xie L,et al.A 1.8-V 22-mW 10-bit 30-MS/s high power efficient and high accuracy applications. pipelined CMOS ADC for low-power subsampling applications. IEEE J Solid-State Circuits,2008,43(2):321 References [4]Ryu S,Song B,Bacrania K.A 10-bit 50-MS/s pipelined ADC with opamp current reuse.IEEE J Solid-State Circuits,2007, [1]Nagaraj K,Fetterman H S,Anidjar J,et al.A 250-mW,8-b,52- 42(3):475 Msamples/s parallel-pipelined A/D converter with reduced num- [5]Chandrashekar K,Bakkaloglu B.A 10 b 50 MS/s opamp-sharing ber of amplifiers.IEEE J Solid-State Circuits,1997,32(3):312 pipeline A/D with current-reuse OTAs.IEEE CICC,2009:263 025006-6
J. Semicond. 2011, 32(2) Yin Rui et al. This work Ref. [2] Ref. [3] Ref. [4] Process VDD f s FOM SFDR ENOB (V) (MS /s) (pJ /step ) (dB ) (bit ) Ref. [2] Ref. [3] Ref. [4] Ref. [5] This work 0.18 μm DGO CMOS 3 80 1.21 74 9.47 0.18 μm CMOS 1.8 0.18 μm CMOS 1.8 50 0.61 70 9.2 30 1.19 69 9.24 0.18 μm CMOS 1.8 50 0.29 74 9.3 0.18 μm CMOS 1.8 80 0.42 76 9.69 Ref . f input / f sample SNDR (dB) 0.0 0.2 0.4 0.6 0.8 1.0 54 55 56 57 58 59 60 61 Ref. [5] Fig. 9. SNDR and other performance comparisons with some recently published works. sured SNDR and SFDR are 60.1 dB and 76 dB, respectively. This technique is also suitable for other ADC architectures, such as multi-bit per stage and multi-channel for achieving high power efficient and high accuracy applications. References [1] Nagaraj K, Fetterman H S, Anidjar J, et al. A 250-mW, 8-b, 52- Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers. IEEE J Solid-State Circuits, 1997, 32(3): 312 [2] Min B, Kim P, Boisvert D, et al. A 69 mW 10 b 80 MS/s pipelined CMOS ADC. ISSCC Digest of Technical Papers, 2003: 324 [3] Li J, Zeng X, Xie L, et al. A 1.8-V 22-mW 10-bit 30-MS/s pipelined CMOS ADC for low-power subsampling applications. IEEE J Solid-State Circuits, 2008, 43(2): 321 [4] Ryu S, Song B, Bacrania K. A 10-bit 50-MS/s pipelined ADC with opamp current reuse. IEEE J Solid-State Circuits, 2007, 42(3): 475 [5] Chandrashekar K, Bakkaloglu B. A 10 b 50 MS/s opamp-sharing pipeline A/D with current-reuse OTAs. IEEE CICC, 2009: 263 025006-6
