复旦大学：微电子工程教学资源（参考论文）A 2-to-2.4-GHz differentially-tuned fractional-N frequency synthesizer for DVB tuner applications

Vol.31,No.7 Journal of Semiconductors July 2010 A 2-to-2.4-GHz differentially-tuned fractional-N frequency synthesizer for DVB tuner applications* Meng Lingbu(孟令部)，Lu Lei(卢磊)，Zhao Wei(赵薇)，and Tang Zhangwen(唐长文)t (State Key Laboratory of ASIC System,Fudan University.Shanghai 201203.China) Abstract:This paper describes the design of a fractional-N frequency synthesizer for digital video broadcasting- terrestrial(DVB-T)receivers.Transfer functions in differentially-tuned PLL are derived and loop parameters are de- signed.In addition,a fully-differential charge pump is presented.An 8/9 high speed prescaler is analyzed and the design considerations for the CML logic are also presented.Test results show that the RMS phase error is less than 0.7 in integer-N mode and less than 1 in fractional-N mode.The implemented frequency synthesizer draws 10 mA from a 1.8-V supply while occupying a die area of about 1-mm2 in a 0.18-um CMOS process. Key words:frequency synthesizer;fully-differential;phase noise;charge pump D0:10.1088/1674-4926/31/7/075007 EEACC:1270 straightforward.In this paper the closed-loop transfer func- 1.Introduction tions of the differentially-tuned synthesizers are derived and are analyzed in detail.The transfer functions and phase noise The fast growing market of digital video broadcasting contribution are the same as single-end tuned frequency syn- has driven much research towards the development of high- thesizers except that the thermal noise of resistors in loop fil- performance low-cost silicon tuners.This is especially true ter doubles their phase noise contribution to the PLL output. when referring to the implementation of highly integrated and But by choosing proper loop parameters the noise deterioration low phase noise RF frequency synthesizers.DVB tuners with from the loop filter can be lowered and is not of much concern. double conversion architecture need a wide range frequency This makes the differentially-tuned frequency synthesizers de- synthesizer to cover the whole tuning range as well as a narrow- sirable where stringent phase noise and small area requirements band frequency synthesizer to down-convert the target signal are needed. band[1.2).The synthesizer should fulfill a stringent phase noise The paper is organized as follows.In section 2,open loop requirement over the entire tuning range and have a fast lock- and closed-loop transfer functions for differentially-tuned fre- ing time.Usually a fractional-Nsynthesizer[3]is adopted be- quency synthesizers are derived and compared to their single- cause the fractional-N synthesizer can avoid some intrinsic ended tuned counterparts.Section 3 shows the detailed circuits limitations of the integer-N synthesizer.The main one is that design,including fully-differential charge pump,high speed the output frequency resolution has to be equal to a multiple 8/9 prescaler and other blocks.Section 4 gives some measure- of the reference frequency.If a finer frequency resolution is ment results,such as phase noise,RMS phase error and ref- needed,a lower reference frequency has to be used.This makes erence spurs at different output frequencies.The last section the loop bandwidth small because it must be much lower than draws some conclusions. 1/10 of the reference frequency to keep loop stablel4l.The consequence of the narrow bandwidth is that PLL locking is PFD+CP LPF very slow.Moreover,a low reference frequency needs a high /2 feedback division ratio N to synthesize the desired output fre- Z(s h(s) quency range,thus causing a strong degradation of in-band 03 phase noisels].Fractional-N synthesizers can solve the prob- lems mentioned above and achieve fast locking,potentially ar- bitrary output frequency resolution,and more freedom in the (S) reference oscillator choicel6]. Differentially-tuned synthesizers are area-efficient and ef- Divider fectively suppress the common-mode noise compared to their single-ended tuned counterpartsl71.However,the closed-loop characteristics in differentially-tuned synthesizer are relatively complicated since both the charge pump and the loop filter Fig.1.Simplified block diagram for differentially-tuned frequency have two equal branches.The transfer function becomes not synthesizer. Project supported by the National Natural Science Foundation of China (No.60876019),the National S&T Major Project of China (No. 2009ZX0131-002-003-02),the Shanghai Rising-Star Program,China (No.09QA1400300),and the National Scientists and Engineers Service for Enterprise Program,China(No.2009GJC00046). Corresponding author.Email:zwtang@fudan.edu.cn Received 4 January 2010,revised manuscript received 24 February 2010 C2010 Chinese Institute of Electronics 075007-1

Vol. 31, No. 7 Journal of Semiconductors July 2010 A 2-to-2.4-GHz differentially-tuned fractional-N frequency synthesizer for DVB tuner applications Meng Lingbu(孟令部), Lu Lei(卢磊), Zhao Wei(赵薇), and Tang Zhangwen(唐长文) Ž (State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China) Abstract: This paper describes the design of a fractional-N frequency synthesizer for digital video broadcasting￾terrestrial (DVB-T) receivers. Transfer functions in differentially-tuned PLL are derived and loop parameters are de￾signed. In addition, a fully-differential charge pump is presented. An 8/9 high speed prescaler is analyzed and the design considerations for the CML logic are also presented. Test results show that the RMS phase error is less than 0.7ı in integer-N mode and less than 1ı in fractional-N mode. The implemented frequency synthesizer draws 10 mA from a 1.8-V supply while occupying a die area of about 1-mm2 in a 0.18-m CMOS process. Key words: frequency synthesizer; fully-differential; phase noise; charge pump DOI: 10.1088/1674-4926/31/7/075007 EEACC: 1270 1. Introduction The fast growing market of digital video broadcasting has driven much research towards the development of high￾performance low-cost silicon tuners. This is especially true when referring to the implementation of highly integrated and low phase noise RF frequency synthesizers. DVB tuners with double conversion architecture need a wide range frequency synthesizer to cover the whole tuning range as well as a narrow￾band frequency synthesizer to down-convert the target signal bandŒ1; 2. The synthesizer should fulfill a stringent phase noise requirement over the entire tuning range and have a fast lock￾ing time. Usually a fractional-NsynthesizerŒ3 is adopted be￾cause the fractional-N synthesizer can avoid some intrinsic limitations of the integer-N synthesizer. The main one is that the output frequency resolution has to be equal to a multiple of the reference frequency. If a finer frequency resolution is needed, a lower reference frequency has to be used. This makes the loop bandwidth small because it must be much lower than 1/10 of the reference frequency to keep loop stableŒ4. The consequence of the narrow bandwidth is that PLL locking is very slow. Moreover, a low reference frequency needs a high feedback division ratio N to synthesize the desired output fre￾quency range, thus causing a strong degradation of in-band phase noiseŒ5. Fractional-N synthesizers can solve the prob￾lems mentioned above and achieve fast locking, potentially ar￾bitrary output frequency resolution, and more freedom in the reference oscillator choiceŒ6 . Differentially-tuned synthesizers are area-efficient and ef￾fectively suppress the common-mode noise compared to their single-ended tuned counterpartsŒ7. However, the closed-loop characteristics in differentially-tuned synthesizer are relatively complicated since both the charge pump and the loop filter have two equal branches. The transfer function becomes not straightforward. In this paper the closed-loop transfer func￾tions of the differentially-tuned synthesizers are derived and are analyzed in detail. The transfer functions and phase noise contribution are the same as single-end tuned frequency syn￾thesizers except that the thermal noise of resistors in loop fil￾ter doubles their phase noise contribution to the PLL output. But by choosing proper loop parameters the noise deterioration from the loop filter can be lowered and is not of much concern. This makes the differentially-tuned frequency synthesizers de￾sirable where stringent phase noise and small area requirements are needed. The paper is organized as follows. In section 2, open loop and closed-loop transfer functions for differentially-tuned fre￾quency synthesizers are derived and compared to their single￾ended tuned counterparts. Section 3 shows the detailed circuits design, including fully-differential charge pump, high speed 8/9 prescaler and other blocks. Section 4 gives some measure￾ment results, such as phase noise, RMS phase error and ref￾erence spurs at different output frequencies. The last section draws some conclusions. Fig. 1. Simplified block diagram for differentially-tuned frequency synthesizer. * Project supported by the National Natural Science Foundation of China (No. 60876019), the National S&T Major Project of China (No. 2009ZX0131-002-003-02), the Shanghai Rising-Star Program, China (No. 09QA1400300), and the National Scientists and Engineers Service for Enterprise Program, China (No. 2009GJC00046). Ž Corresponding author. Email: zwtang@fudan.edu.cn Received 4 January 2010, revised manuscript received 24 February 2010 c 2010 Chinese Institute of Electronics 075007-1

J.Semicond.2010,31(7) Meng Lingbu et al. ×Kv/s=fn.o (3) PFD+CP The current noise transfer function from the charge pump output to the PLL output can be found as: Hcp(s)=- a。=2πN(0） (4) In,cpup Icp 1+Ho(s) For the loop filter,only taking voltage noise into Divide consideration.Another equation follows: -4ao-lc/2z6)】 -0n.Ice/2Z(s)+Vn.Ipiup N 27 2π Fig.2.Noise model for differentially-tuned frequency synthesizer ×Kv/s=9n.o (5) 2.Loop dynamics analysis The voltage noise transfer function from loop filter to the PLL output can be obtained as: 2.1.Open loop transfer function Figure 1 shows a simplified block diagram for Kv/s differentially-tuned frequency synthesizer,where Icp is He(⊙)=1+HoS (6) the charge pump current,N is the division ratio,Ky is the Comparing the derived transfer functions for differentially- VCO tuning gain,and ZF(s)is the loop filter transfer function. tuned frequency synthesizer with these for single-ended tuned The current of charge pumps Icp decreases to a half in each one[5],it can be found that transfer functions for both architec- branch since the charge pump current is split into two equal tures are all the same. parts for the differentially-tuned frequency synthesizer.The The noise transfer function from charge pump output to relationship between output frequency phase n.and input PLL output can be expressed as: frequency phase 0i can be expressed as: 2πNHs)2 [【a-)22z40-（a-)广2zr间 眼.op=(☑匠pp+1pth (7) LIcp1+H.(s)」 ×Kv/s=6no (1) The noise transfer function from loop filter to PLL output can be expressed: The open loop transfer function for the differentially-tuned frequency synthesizer is: H(S)= n,0= Icp 1 Kv Ze(s). 2。t=(匠pp+n儿+H 「Kv(S)12 (8 en.i 2n N s (2) Although differentially configured,the open loop transfer For the charge pump in the differentially-tuned frequency function is the same as that for the single-ended tuned fre- synthesizer,it has two equal two parts and each part is half that quency synthesizers. in single-ended frequency synthesizer.The output current noise 2.2.Noise transfer function andareequal and thusequa to the charge pump output current noise in the single-ended frequency synthesizer. Figure 2 shows the noise model for differentially-tuned fre- So although configured differentially,the charge pump noise quency synthesizer,where2 and are phase noise from contribution for the differentially-tuned frequency to the PLL reference clock and frequency divider respectively,and output,as shown in Eq.(7),is the same as the that for the single- are charge pump outputs from up and down ended frequency synthesizers. braches respectively,while and are voltage For the loop filter,as will be shown in section 3,the loop filter in the differentially-tuned frequency synthesizer has two noise from up and down loop filters. equal parts.Each part is equal to that for the single-ended fre- Obviously,the noise transfer functions from the divider and VCO to PLL output are the same as those for the single-ended quency synthesizer.So the thermal noise from the resisters in tuned frequency synthesizer.The noise transfer functions from the loop filter doubles.As a result,as Equation(8)indicates, the phase noise contribution from the loop filter to PLL output charge pump and loop filter will be derived.Only taking charge pump current noiseinto consideration,the following is twice that for the single-ended frequency synthesizer. equation holds Figures 3 and 4 show the behavior simulation of settling time and phase noise respectively in this design.The thermal noise from loop filter is effectively suppressed through the PLL closed loop.Its phase noise contribution to PLL output is lower than VCO near the loop bandwidth. 075007-2

J. Semicond. 2010, 31(7) Meng Lingbu et al. Fig. 2. Noise model for differentially-tuned frequency synthesizer. 2. Loop dynamics analysis 2.1. Open loop transfer function Figure 1 shows a simplified block diagram for differentially-tuned frequency synthesizer, where ICP is the charge pump current, N is the division ratio, KV is the VCO tuning gain, and ZF.s/ is the loop filter transfer function. The current of charge pumps ICP decreases to a half in each branch since the charge pump current is split into two equal parts for the differentially-tuned frequency synthesizer. The relationship between output frequency phase  n; o and input frequency phase  n; i can be expressed as: hn; i ￾ n; o N ICP=2 2 ZF.s/ ￾  n; i ￾ n; o N ￾ICP=2 2 ZF.s/i KV=s D n;o: (1) The open loop transfer function for the differentially-tuned frequency synthesizer is: Ho.s/ D n; o n; i D ICP 2 1 N KV s ZF.s/: (2) Although differentially configured, the open loop transfer function is the same as that for the single-ended tuned fre￾quency synthesizers. 2.2. Noise transfer function Figure 2 shows the noise model for differentially-tuned fre￾quency synthesizer, where  2 n; i and  2 n; div are phase noise from reference clock and frequency divider respectively, I 2 n; cpup and I 2 n; cpdn are charge pump output current noise from up and down braches respectively, while V 2 n; lpfup and V 2 n; lpfdn are voltage noise from up and down loop filters. Obviously, the noise transfer functions from the divider and VCO to PLL output are the same as those for the single-ended tuned frequency synthesizer. The noise transfer functions from charge pump and loop filter will be derived. Only taking charge pump current noise I 2 n; cpup into consideration, the following equation holds: ￾n; o N ICP=2 2 C In; cpup ZF.s/ ￾ ￾n; o N ￾ICP=2 2 ZF.s/ KV=s D n; o: (3) The current noise transfer function from the charge pump output to the PLL output can be found as: HCP.s/ D n; o In; cpup D 2N ICP Ho.s/ 1 C Ho.s/: (4) For the loop filter, only taking voltage noise V 2 n; lpfup into consideration. Another equation follows:  ￾n; o N ICP=2 2 ZF.s/ C Vn; lpfup ￾ ￾n; o N ￾ICP=2 2 ZF.s/ KV=s D n; o: (5) The voltage noise transfer function from loop filter to the PLL output can be obtained as: HLPF.s/ D KV=s 1 C Ho.s/: (6) Comparing the derived transfer functions for differentially￾tuned frequency synthesizer with these for single-ended tuned oneŒ5, it can be found that transfer functions for both architec￾tures are all the same. The noise transfer function from charge pump output to PLL output can be expressed as:  2 n; o; cp D .I 2 n; cpup C I 2 n; cpdn/ h 2N ICP Ho.s/ 1 C Ho.s/ i2 : (7) The noise transfer function from loop filter to PLL output can be expressed:  2 n; o; lpf D .V 2 n; lpfup C V 2 n; lpfdn/ h KV.s/ 1 C Ho.s/ i2 : (8) For the charge pump in the differentially-tuned frequency synthesizer, it has two equal two parts and each part is half that in single-ended frequency synthesizer. The output current noise I 2 n; cpup and I 2 n; cpup are equal and thus equal to the charge pump output current noise in the single-ended frequency synthesizer. So although configured differentially, the charge pump noise contribution for the differentially-tuned frequency to the PLL output, as shown in Eq. (7), is the same as the that for the single￾ended frequency synthesizers. For the loop filter, as will be shown in section 3, the loop filter in the differentially-tuned frequency synthesizer has two equal parts. Each part is equal to that for the single-ended fre￾quency synthesizer. So the thermal noise from the resisters in the loop filter doubles. As a result, as Equation (8) indicates, the phase noise contribution from the loop filter to PLL output is twice that for the single-ended frequency synthesizer. Figures 3 and 4 show the behavior simulation of settling time and phase noise respectively in this design. The thermal noise from loop filter is effectively suppressed through the PLL closed loop. Its phase noise contribution to PLL output is lower than VCO near the loop bandwidth. 075007-2

J.Semicond.2010,31(7) Meng Lingbu et al. 1. can be easily integrated.A conventional tri-state deadzone free phase-frequency detector(PFD)is employed here.The charge 1.2 pump with common-mode feedback is also differential and can achieve excellent current match.Programmed P/S counters and 1.0 8/9 prescaler is used for the multi-modulus divider to obtain 兰0.8 the desired division ratio.A retiming circuit is used to lower the phase noise from the divider. 0.6 3.1.Charge pump 0.4 Charge pump with high linearity is desirable in the CP- 0.2 PLL.The nonideal effects such as leakage current and the current mismatch can cause not only the deterioration of the reference spur but also degradation of in-band phase noise 0 10 20 30 Time(μs) in fractional-N mode.Fully-differential charge pump is often prior in that it achieves a higher linearity.Additionally,differ- Fig.3.PLL locking time simulation. ential charge pump can effectively suppress the common-mode noise from the power supply and substrate. A modified fully-differential charge pump from Ref.[8] -60 is shown in Fig.6.The positive and negative branches of the fully-differential charge pump are the left and right cir- -80 cuits respectively.For simplicity,only the positive circuit is considered.Transistors M1,M3,M6,M9 compose a replica -100 PLL circuit.M4 and M7 are switches which control whether the DIVIDER charge pump is open or not.The additional MOS branches 120 CP composed by transistors M5 and M8 and the added capacitance Reference Cs are combined to stabilize the common source nodes A and C.Operational amplifier Al is configured as buffer to ensure 140 M5 and M8 working properly when charge pump is closed. SDM By using an error amplifier A3,the voltage Vopc follows the -160 10 voltage Vop.If (W/L)1=(W/L)2,(W/L)3 =(W/L)4, 109 10p Frequency Offset(Hz) (WL)6 =(W/L)7 and (W/L)9 =(W/L)10,current flow- ing through M3 will be equal to that flowing through M4 and Fig.4.PLL phase noise simulation because the transistor in the two path are matched.At the same time.current flowing through M6 will be equal to that flowing through M7.So the sinking current equals the sourcing current. In this way,current matching characteristics can be obtained regardless of the variation of output controlling voltages All of the transistors except the dummy transistors PFD (M11-M14)work in the saturation region.One notable advan- dnb tage is that transistors working in the saturation region are of smaller gate-to-drain capacitance Ced than transistors working Differential LPF in the linear region;another advantage is that the saturation Differential CP transistors have a faster speed.The operational amplifiers in the charge pump only need a bandwidth comparable with the p/s 89 prescaler loop bandwidth of the PLL so as to respond in time to the vari- ation at the output nodes.What is more,the load of these oper- ational amplifiers is only the parasitic capacitance of the tran- SDM sistors which is quite small.As a result,the four operational amplifiers employed in the charge pump consume only limited Fig.5.Block diagram of the 2-2.4 GHz fractional-N frequency syn- power. thesizer The signals from PFD toggle between VSS and VDD and are not suitable to switch these transistors working in satura- 3.Circuit design tion region directly.Thus a level shift is needed to convert the rail-to-rail signals from PFD output to the targeted analog sig- The presented 2-2.4 GHz differentially-tuned fractional-N nals.Figure 7 illustrates the simplified partial level shift cir- frequency synthesizer is shown in Fig.5.For this differentially- cuits used in the charge pump.After the level shift the analog tuned architecture,the big capacitor C in loop filter is ex- control signals can be obtained.Besides,the switches in the actly half that in single-ended frequency synthesizer so that the level shift are connected to a moderate resistance so as to make loop filters transfer function keep unchanged compared with the complementary control signals UP,UP-more symmetrical that in single-ended architecture.By this way the loop filter so as to effectively reduce the high speed glitchs] 075007-3

J. Semicond. 2010, 31(7) Meng Lingbu et al. Fig. 3. PLL locking time simulation. Fig. 4. PLL phase noise simulation. Fig. 5. Block diagram of the 2–2.4 GHz fractional-N frequency syn￾thesizer. 3. Circuit design The presented 2–2.4 GHz differentially-tuned fractional-N frequency synthesizer is shown in Fig. 5. For this differentially￾tuned architecture, the big capacitor C1 in loop filter is ex￾actly half that in single-ended frequency synthesizer so that the loop filters transfer function keep unchanged compared with that in single-ended architecture. By this way the loop filter can be easily integrated. A conventional tri-state deadzone free phase-frequency detector (PFD) is employed here. The charge pump with common-mode feedback is also differential and can achieve excellent current match. Programmed P/S counters and 8/9 prescaler is used for the multi-modulus divider to obtain the desired division ratio. A retiming circuit is used to lower the phase noise from the divider. 3.1. Charge pump Charge pump with high linearity is desirable in the CP￾PLL. The nonideal effects such as leakage current and the current mismatch can cause not only the deterioration of the reference spur but also degradation of in-band phase noise in fractional-N mode. Fully-differential charge pump is often prior in that it achieves a higher linearity. Additionally, differ￾ential charge pump can effectively suppress the common-mode noise from the power supply and substrate. A modified fully-differential charge pump from Ref. [8] is shown in Fig. 6. The positive and negative branches of the fully-differential charge pump are the left and right cir￾cuits respectively. For simplicity, only the positive circuit is considered. Transistors M1, M3, M6, M9 compose a replica circuit. M4 and M7 are switches which control whether the charge pump is open or not. The additional MOS branches composed by transistors M5 and M8 and the added capacitance Cs are combined to stabilize the common source nodes A and C. Operational amplifier A1 is configured as buffer to ensure M5 and M8 working properly when charge pump is closed. By using an error amplifier A3, the voltage VOPC follows the voltage VOP. If (W =L/1 D .W=L/2, (W=L/3 D .W =L/4, (W =L/6 D .W =L/7 and (W =L/9 D .W =L/10, current flow￾ing through M3 will be equal to that flowing through M4 and because the transistor in the two path are matched. At the same time, current flowing through M6 will be equal to that flowing through M7. So the sinking current equals the sourcing current. In this way, current matching characteristics can be obtained regardless of the variation of output controlling voltages. All of the transistors except the dummy transistors (M11–M14) work in the saturation region. One notable advan￾tage is that transistors working in the saturation region are of smaller gate-to-drain capacitance Cgd than transistors working in the linear region; another advantage is that the saturation transistors have a faster speed. The operational amplifiers in the charge pump only need a bandwidth comparable with the loop bandwidth of the PLL so as to respond in time to the vari￾ation at the output nodes. What is more, the load of these oper￾ational amplifiers is only the parasitic capacitance of the tran￾sistors which is quite small. As a result, the four operational amplifiers employed in the charge pump consume only limited power. The signals from PFD toggle between VSS and VDD and are not suitable to switch these transistors working in satura￾tion region directly. Thus a level shift is needed to convert the rail-to-rail signals from PFD output to the targeted analog sig￾nals. Figure 7 illustrates the simplified partial level shift cir￾cuits used in the charge pump. After the level shift the analog control signals can be obtained. Besides, the switches in the level shift are connected to a moderate resistance so as to make the complementary control signals UP, UP– more symmetrical so as to effectively reduce the high speed glitchŒ8 . 075007-3

J.Semicond.2010,31(7) Meng Lingbu et al. replica differential pair differental pair replica VDD. R dither PE VBIAS VSS Fig.6.Fully-differential charge pump without common-mode feedback. VDD speed.Inside each latch,a differential transistor pair(M5 and M6.M13 and M14.M9 and M10)charges and discharges its output nodes.The gate capacitance of these transistors adds to the load of the latch.Operation speed and power consumption of the flip-flop are determined by the transistors sizes and load resistance.Since the operation speed is decided by the time taken for the current to charge the output nodes,the circuit speed directly depends on the current through the stage.In- creasing the currents would require reduction in load resistance ● to maintain swing and thus increase in NMOS device sizes. CMOS Switch The increase in the device size implies a proportional increase in parasitic capacitances.Therefore,the above two variations cancel out the effect of higher current on speed improvements. VSS Thus for a given process and voltage swing the maximum op- Level Shift eration speed is only limited by the parasitic capacitance.So Fig.7.Level shift and switch all metal interconnects are as short as possible especially the lines between the master outputs and slave inputs.High resis- tivity polysilicon resistors without a silicide layer are used as the load to reduce the size and thus parasitic capacitance.In or- der to tolerate process,voltage,and temperature variation,the input sensitivity of the prescaler leaves a sufficient margin. 3.3.Other blocks To meet the stringent phase noise requirements,LC VCO Fig.8.High speed synchronous 8/9 prescaler diagram. is used for its potential to achieve superior phase noise perfor- mancel91.For the presented frequency synthesizer,the 2-2.4 3.2.Prescaler GHz tune range can result in an excessively high tuning sen- sitivity Kv.In practice,this is undesirable since the voltage- For the high speed prescaler,both synchronous and asyn- controlled nodes introduce substantial noise originating from chronous architectures can be adopted.A synchronous 8/9 preceding block especially the thermal noise from the resis- prescaler]is used in this design and is shown in Fig.8.When tors in the loop filter mentioned in section 2.Also noise on the mod is 0,DFF5 is disabled,the prescaler works in divide-by-8 voltage-controlled nodes appears across the varactors and mod- mode.When mod is high,it works in the divide-by-9 mode. ulates the device junction capacitance,resulting in phase noise Compared to the asynchronous 8/9 prescaler,the NAND logic deterioration.To solve these problems,the targeted frequency can be easily incorporated in the current mode logic (CML) range is split into 64 sub-bands by means of a switched varac- latch. tors array.The varactors are digitally selected and driven by Figure 9 shows the CML D-flip-flop schematic which the loop control voltage.This split is useful to reduce the VCO incorporates the NAND logic.Four NMOS transistors are gain associated with the analog control voltage,thus lower- emerged in the first latch to incorporate the NAND logic.The ing the sensitivity to noise appearing on the voltage-controlled tail current sources are eliminated to increase its operation nodes. 075007-4

J. Semicond. 2010, 31(7) Meng Lingbu et al. Fig. 6. Fully-differential charge pump without common-mode feedback. Fig. 7. Level shift and switch. Fig. 8. High speed synchronous 8/9 prescaler diagram. 3.2. Prescaler For the high speed prescaler, both synchronous and asyn￾chronous architectures can be adopted. A synchronous 8/9 prescalerŒ6 is used in this design and is shown in Fig. 8. When mod is 0, DFF5 is disabled, the prescaler works in divide-by-8 mode. When mod is high, it works in the divide-by-9 mode. Compared to the asynchronous 8/9 prescaler, the NAND logic can be easily incorporated in the current mode logic (CML) latch. Figure 9 shows the CML D-flip-flop schematic which incorporates the NAND logic. Four NMOS transistors are emerged in the first latch to incorporate the NAND logic. The tail current sources are eliminated to increase its operation speed. Inside each latch, a differential transistor pair (M5 and M6, M13 and M14, M9 and M10) charges and discharges its output nodes. The gate capacitance of these transistors adds to the load of the latch. Operation speed and power consumption of the flip-flop are determined by the transistors sizes and load resistance. Since the operation speed is decided by the time taken for the current to charge the output nodes, the circuit speed directly depends on the current through the stage. In￾creasing the currents would require reduction in load resistance to maintain swing and thus increase in NMOS device sizes. The increase in the device size implies a proportional increase in parasitic capacitances. Therefore, the above two variations cancel out the effect of higher current on speed improvements. Thus for a given process and voltage swing the maximum op￾eration speed is only limited by the parasitic capacitance. So all metal interconnects are as short as possible especially the lines between the master outputs and slave inputs. High resis￾tivity polysilicon resistors without a silicide layer are used as the load to reduce the size and thus parasitic capacitance. In or￾der to tolerate process, voltage, and temperature variation, the input sensitivity of the prescaler leaves a sufficient margin. 3.3. Other blocks To meet the stringent phase noise requirements, LC VCO is used for its potential to achieve superior phase noise perfor￾manceŒ9. For the presented frequency synthesizer, the 2–2.4 GHz tune range can result in an excessively high tuning sen￾sitivity KV. In practice, this is undesirable since the voltage￾controlled nodes introduce substantial noise originating from preceding block especially the thermal noise from the resis￾tors in the loop filter mentioned in section 2. Also noise on the voltage-controlled nodes appears across the varactors and mod￾ulates the device junction capacitance, resulting in phase noise deterioration. To solve these problems, the targeted frequency range is split into 64 sub-bands by means of a switched varac￾tors arrayŒ6. The varactors are digitally selected and driven by the loop control voltage. This split is useful to reduce the VCO gain associated with the analog control voltage, thus lower￾ing the sensitivity to noise appearing on the voltage-controlled nodes. 075007-4

J.Semicond.2010,31(7) Meng Lingbu et al. Latch Latch VDD R M13 DI CLK CLK M M2 VSS Fig.9."NAND"embedded CML D-flip-flop. Phase Noise 10,00dB/Ref -10.00dBc/Hz -10.0 -20.0 Loop PFD -30.0 EC/ -40.0 Filter CP -50.0 -60.0 -70.0 -80.0 90.0 DO -100.0 Digital -110.0 120.0 Prescaler -130.0 140.0 150.0 160.0 -170.0 GVN3B Fig.10.Die photograph Fig.11.Measured phase noise at an oscillation frequency of2.26 GHz. Single-stage multiple feed forward SDM is adopted herelio.Fewer output levels of SDM are preferred so as to lower the in-band phase noise deterioration through noise fold- N mode and integer-N mode respectively.The RMS phase ing by quantization noise going through analog blocks with error is less than 0.7 in integer-N mode and less than 1 in non-linearity fractional-N mode across the overall tuning range.Table 1 lists the performance comparison with other frequency synthesizers 4.Experimental results for tuner applications.Comparing with other frequency synthe- sizers for tuners applications,the presented frequency synthe- The frequency synthesizer was fabricated in SMIC 0.18- sizer achieves superior phase noise performance and low power um CMOS technology.The chip microphotograph is shown in consumption. Fig.10.The die area of the frequency synthesizer is about 1.2 Figure 13 shows the measured power spectrum density ×0.8mm2. (PSD)of the oscillation amplitude at 2.3 GHz;the reference Operating at 2.2 GHz,the frequency synthesizer draws 10 spur is-66 dBc.Figure 14 shows the reference spurs at differ- mA from 1.8-V supply.The measured loop bandwidth is ap- ent output frequencies.The reference spur is less than-63 dBc proximately 100 kHz.The measured phase noise plots for the in across the overall tuning range. frequency synthesizer are shown in Fig.11.In-band phase noise at 10 kHz offset is-95 dBc/Hz and at 1 MHz offset the 5.Conclusion measured phase noise is-111 dBc/Hz.The integrated RMS phase error is 0.8.Figure 12 shows the measured RMS phase A fractional-N frequency synthesizer for DTV tuner ap- error integrated from 100 Hz tol00 MHz in both fractional- plications has been presented in this paper.Transfer func- 075007-5

J. Semicond. 2010, 31(7) Meng Lingbu et al. Fig. 9. “NAND” embedded CML D-flip-flop. Fig. 10. Die photograph. Single-stage multiple feed forward SDM is adopted hereŒ10. Fewer output levels of SDM are preferred so as to lower the in-band phase noise deterioration through noise fold￾ing by quantization noise going through analog blocks with non-linearity. 4. Experimental results The frequency synthesizer was fabricated in SMIC 0.18- m CMOS technology. The chip microphotograph is shown in Fig. 10. The die area of the frequency synthesizer is about 1.2 0.8 mm2 . Operating at 2.2 GHz, the frequency synthesizer draws 10 mA from 1.8-V supply. The measured loop bandwidth is ap￾proximately 100 kHz. The measured phase noise plots for the frequency synthesizer are shown in Fig. 11. In-band phase noise at 10 kHz offset is –95 dBc/Hz and at 1 MHz offset the measured phase noise is ￾111 dBc/Hz. The integrated RMS phase error is 0.8ı . Figure 12 shows the measured RMS phase error integrated from 100 Hz to100 MHz in both fractional￾Fig. 11. Measured phase noise at an oscillation frequency of 2.26 GHz. N mode and integer-N mode respectively. The RMS phase error is less than 0.7ı in integer-N mode and less than 1ı in fractional-N mode across the overall tuning range. Table 1 lists the performance comparison with other frequency synthesizers for tuner applications. Comparing with other frequency synthe￾sizers for tuners applications, the presented frequency synthe￾sizer achieves superior phase noise performance and low power consumption. Figure 13 shows the measured power spectrum density (PSD) of the oscillation amplitude at 2.3 GHz; the reference spur is –66 dBc. Figure 14 shows the reference spurs at differ￾ent output frequencies. The reference spur is less than –63 dBc in across the overall tuning range. 5. Conclusion A fractional-N frequency synthesizer for DTV tuner ap￾plications has been presented in this paper. Transfer func- 075007-5

J.Semicond.2010,31(7) Meng Lingbu et al. Table 1.PLL performance comparison. Reference Ref.[11] Ref.[12] Ref.[13] This work Technology 0.13-um CMOS 0.11-um CMOS 0.18-um CMOS 0.18-um CMOS Application DVB-S ISDB-T DVB-T DVB-T Tuning type Single-ended Single-ended Single-ended differential Loop bandwidth (kHz) 1000 100 100 100 Output frequency (GHz) 2.24-4.48 1.5-3.78 1.1-2.2 2-2.4 Phase noise (dBc/Hz) -98@100kHz -88@10kHz -90@10kHz -95@10kHz -100@1MHz -118@1MHz -90@10kHz -111@1MHz RMS phase error(°) 0.8 NA 1.5 0.8 Power consumption(mW) 132 20 NA 18 Chip size (mm2) 0.3 1.9 1.2 1 -62 A-Fractional-N -64 Integer-N 3 -66 1.0 ap) -68 09 0.8 12 -74 0.6 -76 -78 1.9 2.0 2.1 2.2 2.3 2.4 2.5 1.9 2.0 2.12.2 2.3 2.4 2.5 Frequency (GHz) Frequency(GHz) Fig.12.RMS phase error (integrated from 100 Hz to 100 MHz). Fig.14.Reference spurs at different output frequencies. Mkr1 25.000 MHz match performance is superior in terms of reference spurs.8/9 Ref0 dBm Atten 10 dB -66.440dB high speed prescaler is analyzed and the design considerations Samp Log for the CML logic is also presented.Measured results show 1 dB/ that the presented frequency synthesizer could meet the DVB tuner applications. Marker△ References 25.000000MHz [1]Dawkins M,Burdett A P,Cowley N.A single-chip tuner for DVB- gAv -66.440dB 100 T.IEEE J Solid-State Circuits,2003,38(8):1307 WIS2 [2]Saias D,Montaudon F,Andre E,et al.A 0.12 um CMOS DVB- S3 FC T tuner.IEEE Int Solid-State Circuits Conf Tech Dig,Feb 2005: AA s(①： 430 FTun [3]Wu T,Hanumolu P K,Mayaram K,et al.Methods for constant loop bandwidth in LC-VCO PLL frequency synthesizers.IEEE J Solid-State Circuits,2009.44(2):427 Center 2.300 000 GHz Span 60 MHz #Res BW 75 kHz VBW 75 kHz Sweep 40.95 ms (8192 pts) [4]Gardner F M.Charge-pump phase-lock loops.IEEE Trans Cir- cuits Syst.1980,28(11:1849 Fig.13.Measured power spectrum density (PSD)of the oscillation [5]He J.Frequency synthesizer for DVB-T receivers.PhD Disserta- amplitude at 2.3 GHz tion,Fudan University [6]Lu L.Frequency synthesizer for RF receivers.PhD Dissertation, Fudan University tions for the differentially-tuned frequency synthesizer are de- [7]Lu L,Chen J,Yuan L,et al.An 18-mW 1.175-2 GHz frequency rived.The loop filter doubles their phase noise contribution in synthesizre with constant bandwidth for DVB-T tuners.IEEE Trans Microvew Theory Tech,2009:928 differentially-tuned frequency synthesizer,but through proper [8]Cheng S.Design and analysis of an ultrahigh-speed glitch-free loop parameters,loop filter phase noise can be lowered.Cir- fully differential charge pump with minimum output current vari- cuit details are also presented.Complimentary CMOS switches ation and accurate matching.IEEE Trans Circuits Syst II,Express connected with resistance are adopted to enhance the analog Breiefs,2006,53(9):843 loop(PFD+CP)linearity.Test results show that although the [9]Tang Z,He J,Min H.A low-phase-noise 1-GHz LC VCO differ- charge pump design is relatively complicated,the CP current entially tuned by switched step capacitors.IEEE Asia Solid-State 075007-6

J. Semicond. 2010, 31(7) Meng Lingbu et al. Table 1. PLL performance comparison. Reference Ref. [11] Ref. [12] Ref. [13] This work Technology 0.13-m CMOS 0.11-m CMOS 0.18-m CMOS 0.18-m CMOS Application DVB-S ISDB-T DVB-T DVB-T Tuning type Single-ended Single-ended Single-ended differential Loop bandwidth (kHz) 1000 100 100 100 Output frequency (GHz) 2.24–4.48 1.5–3.78 1.1–2.2 2–2.4 Phase noise (dBc/Hz) –98 @ 100 kHz –100 @ 1 MHz –88 @ 10 kHz –118 @ 1 MHz –90 @ 10 kHz –90 @ 10 kHz –95 @ 10 kHz –111 @ 1 MHz RMS phase error (ı / 0.8 NA 1.5 0.8 Power consumption (mW) 132 20 NA 18 Chip size (mm2 / 0.3 1.9 1.2 1 Fig. 12. RMS phase error (integrated from 100 Hz to 100 MHz). Fig. 13. Measured power spectrum density (PSD) of the oscillation amplitude at 2.3 GHz. tions for the differentially-tuned frequency synthesizer are de￾rived. The loop filter doubles their phase noise contribution in differentially-tuned frequency synthesizer, but through proper loop parameters, loop filter phase noise can be lowered. Cir￾cuit details are also presented. Complimentary CMOS switches connected with resistance are adopted to enhance the analog loop (PFD + CP) linearity. Test results show that although the charge pump design is relatively complicated, the CP current Fig. 14. Reference spurs at different output frequencies. match performance is superior in terms of reference spurs. 8/9 high speed prescaler is analyzed and the design considerations for the CML logic is also presented. Measured results show that the presented frequency synthesizer could meet the DVB tuner applications. References [1] Dawkins M, Burdett A P, Cowley N. A single-chip tuner for DVB￾T. IEEE J Solid-State Circuits, 2003, 38(8): 1307 [2] Saias D, Montaudon F, Andre E, et al. A 0.12 m CMOS DVB￾T tuner. IEEE Int Solid-State Circuits Conf Tech Dig, Feb 2005: 430 [3] Wu T, Hanumolu P K, Mayaram K, et al. Methods for constant loop bandwidth in LC-VCO PLL frequency synthesizers. IEEE J Solid-State Circuits, 2009, 44(2): 427 [4] Gardner F M. Charge-pump phase-lock loops. IEEE Trans Cir￾cuits Syst, 1980, 28(11): 1849 [5] He J. Frequency synthesizer for DVB-T receivers. PhD Disserta￾tion, Fudan University [6] Lu L. Frequency synthesizer for RF receivers. PhD Dissertation, Fudan University [7] Lu L, Chen J, Yuan L, et al. An 18-mW 1.175–2 GHz frequency synthesizre with constant bandwidth for DVB-T tuners. IEEE Trans Microvew Theory Tech, 2009: 928 [8] Cheng S. Design and analysis of an ultrahigh-speed glitch-free fully differential charge pump with minimum output current vari￾ation and accurate matching. IEEE Trans Circuits Syst II, Express Breiefs, 2006, 53(9): 843 [9] Tang Z, He J, Min H. A low-phase-noise 1-GHz LC VCO differ￾entially tuned by switched step capacitors. IEEE Asia Solid-State 075007-6

J.Semicond.2010,31(7) Meng Lingbu et al. Circuits Conference Proceedings,Nov 2005:409 cuits Conf Tech Dig,Feb 2006:618 [10]Rhee W,Song B S,Ali A.A 1.1-GHz CMOS fractional-N fre-[12]Marutani M,Anbutsu H,Kondo M,et al.An 18 mW 90 to quency synthesizer with a 3-b third-order delta-sigma modulator. 770 MHz synthesizer with agile autotuning for digital TV-tuners. IEEE J Solid-State Circuits,2000,35:1453 IEEE Int Solid-State Circuits Conf Tech Dig,Feb 2006:192 [11]Maxim A,Poorfard R,Kao J.A sub-1.5 phase-noise ring-[13]Gupta M,Lerstaveesin S,Kang D,etal.A48-to-860 MHzCMOS oscillator-based frequency synthesizer for low-IF single-chip direct-conversion TV tuner.IEEE Int Solid-State Circuits Conf DBS satellitetuner-demodulator SoC.IEEE Int Solid-State Cir- Tech Dig,Feb 2007:206 075007-7

J. Semicond. 2010, 31(7) Meng Lingbu et al. Circuits Conference Proceedings, Nov 2005: 409 [10] Rhee W, Song B S, Ali A. A 1.1-GHz CMOS fractional-N fre￾quency synthesizer with a 3-b third-order delta-sigma modulator. IEEE J Solid- State Circuits, 2000, 35: 1453 [11] Maxim A, Poorfard R, Kao J. A sub-1.5ı phase-noise ring￾oscillator-based frequency synthesizer for low-IF single-chip DBS satellitetuner-demodulator SoC. IEEE Int Solid-State Cir￾cuits Conf Tech Dig, Feb 2006: 618 [12] Marutani M, Anbutsu H, Kondo M, et al. An 18 mW 90 to 770 MHz synthesizer with agile autotuning for digital TV-tuners. IEEE Int Solid-State Circuits Conf Tech Dig, Feb 2006: 192 [13] Gupta M, Lerstaveesin S, Kang D, et al. A 48-to-860 MHz CMOS direct-conversion TV tuner. IEEE Int Solid-State Circuits Conf Tech Dig, Feb 2007: 206 075007-7