Vol.30,No.11 Journal of Semiconductors November 2009 An eighth order channel selection filter for low-IF and zero-IF DVB tuner applications* Zou Liang(邹亮)'，Liao Youchun(廖友春)2，and Tang Zhangwent(唐长文)l,t (I ASIC System State Key Laboratory,Fudan University,Shanghai 201203,China) (2 Ratio Microelectronics Technology Co.Ltd,Shanghai 200433,China) Abstract:An eighth order active-RC filter for low-IF and zero-IF DVB tuner applications is presented,which is implemented in Butterworth biquad structure.An automatic frequency tuning circuit is introduced to compensate the cut-off frequency variation using a 6-bit switched-capacitor array.Switched-resistor arrays are adopted to cover different cut-off frequencies in low-IF and zero-IF modes.Measurement results show that precise cut-off frequencies at 2.5,3.3.5 and 4 MHz in zero-IF mode,5,6,7 and 8 MHz in low-IF mode can be achieved,60 dB frequency attenuation can be obtained at 20 MHz,and the in-band group delay agrees well with the simulation.Two-tone testing shows the in-band IM3 achieves-52 dB and the out-band IM3 achieves-55 dB with-11 dBm input power. This proposed filter circuit,fabricated in a SMIC 0.18 um CMOS process,consumes 4 mA current with 1.8 V power supply. Key words:active-RC filter;Butterworth;frequency tuning;group delay;noise;linearity D0:10.1088/16744926/30/11/115002 EEACC:1270 1.Introduction 2.System requirements The specification of an analog filter can be summarized In digital video broadcasting (DVB)tuner systems, as two parts:the first part is the ACR,which includes the cut- shown in Fig.1,wide bandwidth and high linearity require- off frequency and frequency attenuation;the second part is ments make analog-to-digital converters (ADC)difficult to im- the error vector magnitude(EVM)loss,which includes the in- plement.To obtain a good adjacent channel rejection(ACR) before ADC,a high-order analog filter is adopted to achieve band ripple,group delay,noise and linearity.The in-band rip- good attenuation and an active-RC architecture is selected to ple and group delay determine the quality of the signal transfer function,and the noise and linearity determine the EVM loss achieve high linearity.The cut-off frequency of an integrated caused by the analog filter itself.Here,the critical system re- active-RC filter is determined by on-chip resistors and capaci- tors which may vary greatly with the process,voltage and tem- quirements will be discussed. perature (PVT).Thus,an automatic frequency tuning (AFT) 2.1.Noise and linearity circuit should be engaged to calibrate the cut-off frequency variation. In DVB tuner receivers,noise figure (NF)and linearity are critical performance parameters,which affect the system For DVB-T/H protocols,different signal bandwidths, signal-to-noise ratio(SNR).The definition of sensitivity is: such as 5,6.7 and 8 MHz,have been defined.To cover all these signal bandwidths,a programmable channel selection Pin.min KT +NF 101g B+SNRmin. (1) filter with switched-capacitor arrays and switched-resistor ar- rays is proposed in this paper.In zero-IF mode,the channel To meet the minimum SNR requirement, selection filter covers the cut-off frequencies of 2.5.3,3.5 and 4 MHz.Halving the switched-capacitor value automatically, NF Pin.min KT -101g B-SNRmin. (2) this filter can also be switched to low-IF mode,in which the Linearity can be defined in different forms,such as IIP3, corresponding cut-off frequencies are 5,6,7 and 8 MHz re- PidB,composite second order distortion(CSO)and compos- spectively. ite triple beat distortion(CTB).Because CSO,CTB and PidB This paper also illustrates the system requirements of have a direct relationship with IIP,only IIP will be con- noise and linearity in detail,shows the circuit design,including sidered here.In DVB tuner systems,the adjacent interferences the selection of biquad structures,amplifier design and AFT become a bottleneck of the linearity requirement;DVB-T/H tuning circuit,and proposes critical design insights to mini- protocols clearly show that adjacent channels may be 40 dB mize the non-ideal factors which will affect tuning precision. larger than the desired channel.To assure enough SNR,the Project supported by the National High Technology Research and Development Program of China (No.2007AA01Z282). Corresponding author.Email:zwtang@fudan.edu.cn Received 5 May 2009,revised manuscript received 26 May 2009 2009 Chinese Institute of Electronics 115002-1
Vol. 30, No. 11 Journal of Semiconductors November 2009 An eighth order channel selection filter for low-IF and zero-IF DVB tuner applications∗ Zou Liang(邹亮) 1 , Liao Youchun(廖友春) 2 , and Tang Zhangwen(唐长文) 1, † (1 ASIC & System State Key Laboratory, Fudan University, Shanghai 201203, China) (2 Ratio Microelectronics Technology Co, Ltd, Shanghai 200433, China) Abstract: An eighth order active-RC filter for low-IF and zero-IF DVB tuner applications is presented, which is implemented in Butterworth biquad structure. An automatic frequency tuning circuit is introduced to compensate the cut-off frequency variation using a 6-bit switched-capacitor array. Switched-resistor arrays are adopted to cover different cut-off frequencies in low-IF and zero-IF modes. Measurement results show that precise cut-off frequencies at 2.5, 3, 3.5 and 4 MHz in zero-IF mode, 5, 6, 7 and 8 MHz in low-IF mode can be achieved, 60 dB frequency attenuation can be obtained at 20 MHz, and the in-band group delay agrees well with the simulation. Two-tone testing shows the in-band IM3 achieves –52 dB and the out-band IM3 achieves –55 dB with –11 dBm input power. This proposed filter circuit, fabricated in a SMIC 0.18 µm CMOS process, consumes 4 mA current with 1.8 V power supply. Key words: active-RC filter; Butterworth; frequency tuning; group delay; noise; linearity DOI: 10.1088/1674-4926/30/11/115002 EEACC: 1270 1. Introduction In digital video broadcasting (DVB) tuner systems, shown in Fig. 1, wide bandwidth and high linearity requirements make analog-to-digital converters (ADC) difficult to implement. To obtain a good adjacent channel rejection (ACR) before ADC, a high-order analog filter is adopted to achieve good attenuation and an active-RC architecture is selected to achieve high linearity. The cut-off frequency of an integrated active-RC filter is determined by on-chip resistors and capacitors which may vary greatly with the process, voltage and temperature (PVT). Thus, an automatic frequency tuning (AFT) circuit should be engaged to calibrate the cut-off frequency variation. For DVB-T/H protocols, different signal bandwidths, such as 5, 6, 7 and 8 MHz, have been defined. To cover all these signal bandwidths, a programmable channel selection filter with switched-capacitor arrays and switched-resistor arrays is proposed in this paper. In zero-IF mode, the channel selection filter covers the cut-off frequencies of 2.5, 3, 3.5 and 4 MHz. Halving the switched-capacitor value automatically, this filter can also be switched to low-IF mode, in which the corresponding cut-off frequencies are 5, 6, 7 and 8 MHz respectively. This paper also illustrates the system requirements of noise and linearity in detail, shows the circuit design, including the selection of biquad structures, amplifier design and AFT tuning circuit, and proposes critical design insights to minimize the non-ideal factors which will affect tuning precision. 2. System requirements The specification of an analog filter can be summarized as two parts: the first part is the ACR, which includes the cutoff frequency and frequency attenuation; the second part is the error vector magnitude (EVM) loss, which includes the inband ripple, group delay, noise and linearity. The in-band ripple and group delay determine the quality of the signal transfer function, and the noise and linearity determine the EVM loss caused by the analog filter itself. Here, the critical system requirements will be discussed. 2.1. Noise and linearity In DVB tuner receivers, noise figure (NF) and linearity are critical performance parameters, which affect the system signal-to-noise ratio (SNR). The definition of sensitivity is: Pin, min = KT + NF + 10 lg B + SNRmin. (1) To meet the minimum SNR requirement, NF < Pin, min − KT − 10 lg B − SNRmin. (2) Linearity can be defined in different forms, such as IIP3, P1dB, composite second order distortion (CSO) and composite triple beat distortion (CTB). Because CSO, CTB and P1dB have a direct relationship with IIP3 [1], only IIP3 will be considered here. In DVB tuner systems, the adjacent interferences become a bottleneck of the linearity requirement; DVB-T/H protocols clearly show that adjacent channels may be 40 dB larger than the desired channel. To assure enough SNR, the ∗ Project supported by the National High Technology Research and Development Program of China (No. 2007AA01Z282). † Corresponding author. Email: zwtang@fudan.edu.cn Received 5 May 2009, revised manuscript received 26 May 2009 ⃝c 2009 Chinese Institute of Electronics 115002-1
J.Semicond.30(11) Zou Liang et al. RF front-end Analog baseband VGLNA UpMixer DnMixer ADC Off-chip Band Limit Pre- Filter Digital Filter Amplifier VGA Baseband 90 ADC First LO Second LO (Quadr ature) Fig.1.Architecture of RF tuner. HP. N+1 N+21 N+3 i N+4 PR DVB-T/H DVB-T/H Filter DVB-T/H 174 MHz Fig.2.IIP3 calculation for analog filter. 862MH Fig.3.Pattern L3 in the case of channel N+2 or N+4 for DVB-T/H. product of IM3 must be rigidly constrained.Assume that there The most rigid requirements of adjacent interferences are are two interferential signals Pin in adjacent channels with the same power,and Ps is the power of the desired channel,as given in Table 1,where reference BER is defined as BER shown in Fig.2. 2x 10-4 after Viterbi decoding. The noise and linearity requirements are determined by According to the IIP definition of an analog filter with the minimum and maximal input power separately.In our sys- 0dB gain, IIPs=Pn+t Pin-PIMs tem design,the input power of the channel selection filter is 2 (3) controlled between -35 and-15 dBm by an automatic gain control(AGC)loop.The SNR requirements for digital demod- To meet the minimum SNR. ulation are listed in Table 1.If a 3 dB margin is considered,the Ps -PIM3 SNRmin. (4) SNR requirement should be 26 dB for DVB-T and 20 dB for DVB-H.According to Egs.(2)and(5),the requirements of Substituting Eq.(3)into Eq.(4),the following can be derived: NF and out-band IIP3 of DVB-T protocol can be obtained as follows, IIP3 >Pm-P.+SNRan Pnma PR+SNRmin 2 NFPPR+SNRmin 2 channels are the primary non-linearity contributors,because the adjacent interferences in the N+2 and N+4 channels are -15+22 dBm 14dBm. (7) much larger than the others.But for the modules behind the For DVB-H protocol,the requirements of NF and out-band channel selection filter,such as VGA and ADC.the adjacent IIP can be given. interferences in the N+1 channels are the major non-linearity contributors,because the interferences in the other channels NF<Pin.min -KT-101g B-SNRmin can be attenuated by the channel selection filter.Now,the pat- =(-35+174-69-20)dB=50dB. (8) tern L3 of DVB-T/H protocols21 is chosen to determine the NF and IIP3 of the channel selection filter.This pattern has PR+SNRmin one digital DVB-T/H signal on the channel N+2 and another IIP3 Pin.max 2 digital DVB-T/H signal on the channel N+4 in addition to the desired DVB-T/H signal on the channel N,as shown in Fig.3. 15+42+20 2 dBm 16dBm (9) 115002-2
J. Semicond. 30(11) Zou Liang et al. Fig. 1. Architecture of RF tuner. Fig. 2. IIP3 calculation for analog filter. product of IM3 must be rigidly constrained. Assume that there are two interferential signals Pin in adjacent channels with the same power, and Ps is the power of the desired channel, as shown in Fig. 2. According to the IIP3 definition of an analog filter with 0 dB gain, IIP3 = Pin + Pin − PIM3 2 . (3) To meet the minimum SNR, Ps − PIM3 > SNRmin. (4) Substituting Eq. (3) into Eq. (4), the following can be derived: IIP3 > Pin + Pin − Ps + SNRmin 2 = Pin,max + PR + SNRmin 2 , (5) where Pin − Ps is defined as the protection ratio (PR). For the modules in front of the channel selection filter in DVB tuners, adjacent interferences in the N + 2 and N + 4 channels are the primary non-linearity contributors, because the adjacent interferences in the N + 2 and N + 4 channels are much larger than the others. But for the modules behind the channel selection filter, such as VGA and ADC, the adjacent interferences in the N ± 1 channels are the major non-linearity contributors, because the interferences in the other channels can be attenuated by the channel selection filter. Now, the pattern L3 of DVB-T/H protocols[2] is chosen to determine the NF and IIP3 of the channel selection filter. This pattern has one digital DVB-T/H signal on the channel N + 2 and another digital DVB-T/H signal on the channel N +4 in addition to the desired DVB-T/H signal on the channel N, as shown in Fig. 3. Fig. 3. Pattern L3 in the case of channel N +2 or N +4 for DVB-T/H. The most rigid requirements of adjacent interferences are given in Table 1, where reference BER is defined as BER = 2 × 10−4 after Viterbi decoding. The noise and linearity requirements are determined by the minimum and maximal input power separately. In our system design, the input power of the channel selection filter is controlled between –35 and –15 dBm by an automatic gain control (AGC) loop. The SNR requirements for digital demodulation are listed in Table 1. If a 3 dB margin is considered, the SNR requirement should be 26 dB for DVB-T and 20 dB for DVB-H. According to Eqs. (2) and (5), the requirements of NF and out-band IIP3 of DVB-T protocol can be obtained as follows, NF Pin,max + PR+SNRmin 2 = ( −15 + 32 + 26 2 ) dBm = 14 dBm. (7) For DVB-H protocol, the requirements of NF and out-band IIP3 can be given, NF Pin,max + PR+SNRmin 2 = ( −15 + 42 + 20 2 ) dBm = 16 dBm. (9) 115002-2
Zou Liang et al. November 2009 Table 1.Immunity to pattern L3 and SNR requirements of digital demodulation for DVB-T/H Protocol Mode PR SNR (Portable P1) BER DVB-T 2K/4K/8K 64QAM CR=2/3 GI =All 32 dB 23 dB DVB-H 2K/4K/8K 16QAM CR=2/3 GI All 42 dB 17 dB 6 Table 2.Filter specifications Filter specification Value Supply voltage 1.8V Power consumption +16 dBm Noise figure <44dB Tuning error ±5% M R o-W R C C nAAy (a) (b) Fig.4.(a)Sallen-Key biquad;(b)Tow-Thomas biquad. So,the minimum requirement of NF is 44 dB,and the maxi- between the channel selection filter and Nyquist-rate ADC is mal requirement of out-band IIP;is +16 dBm. given in Ref.[4]. 2.2.Other issues According to the requirements of ACR and anti-aliasing. this filter should achieve 60 dB attenuation at 20 MHz and the The main purpose of the analog channel filter in RF re- precision of the cut-off frequency should be controlled within ceiver is to select the desired signal and provide anti-aliasing +5%.In this paper,an eighth order Butterworth filter is chosen for the following ADC.Channel selection can be achieved in here for the flat pass-band and sharp transition-band frequency either analog or digital domains.The implement in analog do- response,and an AFT tuning circuit is engaged to compensate main increases the dynamic range requirement of analog filter, the cut-off frequency variation.Detailed filter specifications but lowers the ADC's resolution.However.a digital filter can are given in Table 2. conquer the variation of components,the phase and gain error suffered by the analog filter,but requires increased resolution 3.Filter circuit design and dynamic range of ADC.The power of ADC will swiftly 3.1.Biquad selection increase as the resolution requirement increases31,which can be shown as. Sallen-Key and Tow-Thomas are the two most popular biquads in filter design,as shown in Fig.4.Two poles are im- PADC Ecomv x 2N x fs(Nyquist-Rate ADC), (10) plemented in the Sallen-Key biquad,using only one amplifier, but two amplifiers are used in the Tow-Thomas biquad.Com- where Econv is the required power for one bit,2N is the number pared with the Tow-Thomas biquad,the Sallen-Key biquad has of bits,and fs is the sample rate.Detailed power optimization an obvious advantage in power consumption.But,in fact,the 115002-3
Zou Liang et al. November 2009 Table 1. Immunity to pattern L3 and SNR requirements of digital demodulation for DVB-T/H. Protocol Mode PR SNR (Portable P1) BER DVB-T 2K/4K/8K 64QAM CR = 2/3 GI = All 32 dB 23 dB 4 DVB-H 2K/4K/8K 16QAM CR = 2/3 GI = All 42 dB 17 dB 6 Table 2. Filter specifications. Filter specification Value Supply voltage 1.8 V Power consumption +16 dBm Noise figure < 44 dB Tuning error ±5% Fig. 4. (a) Sallen-Key biquad; (b) Tow-Thomas biquad. So, the minimum requirement of NF is 44 dB, and the maximal requirement of out-band IIP3 is +16 dBm. 2.2. Other issues The main purpose of the analog channel filter in RF receiver is to select the desired signal and provide anti-aliasing for the following ADC. Channel selection can be achieved in either analog or digital domains. The implement in analog domain increases the dynamic range requirement of analog filter, but lowers the ADC’s resolution. However, a digital filter can conquer the variation of components, the phase and gain error suffered by the analog filter, but requires increased resolution and dynamic range of ADC. The power of ADC will swiftly increase as the resolution requirement increases[3], which can be shown as, PADC = Econv × 2 N × fS (Nyquist-Rate ADC), (10) where Econv is the required power for one bit, 2N is the number of bits, and fS is the sample rate. Detailed power optimization between the channel selection filter and Nyquist-rate ADC is given in Ref. [4]. According to the requirements of ACR and anti-aliasing, this filter should achieve 60 dB attenuation at 20 MHz and the precision of the cut-off frequency should be controlled within ±5%. In this paper, an eighth order Butterworth filter is chosen here for the flat pass-band and sharp transition-band frequency response, and an AFT tuning circuit is engaged to compensate the cut-off frequency variation. Detailed filter specifications are given in Table 2. 3. Filter circuit design 3.1. Biquad selection Sallen-Key and Tow-Thomas are the two most popular biquads in filter design, as shown in Fig. 4. Two poles are implemented in the Sallen-Key biquad, using only one amplifier, but two amplifiers are used in the Tow-Thomas biquad. Compared with the Tow-Thomas biquad, the Sallen-Key biquad has an obvious advantage in power consumption. But, in fact, the 115002-3
J.Semicond.30(11) Zou Liang et al. Common-Mode Feedback Circuit VDD M13 Re Ce Common-Mode Loop Fig.5.A fully differential two-stage amplifier. AC response Stability response 100 100C 75 (p)OA 155023 ()O 50 25 02300 25 150 125 1 75 2I02.7.59.72cd) 10 10 1010101010心10101010 10101 10炉10101051010710心10 Freq (Hz) Freq (Hz) (a) (b) Fig.6.(a)Bode diagram of differential-mode signal;(b)Bode diagram of common-mode signal Sallen-Key biquad is more sensitive to PVT variation than the located at p =gmi6/Cnito is additionally introduced into the Tow-Thomas biquad,and its performance at high frequencies common-mode loop.The gain of the common-mode circuit is susceptible to parasitic capacitance.Thus,here the Tow- should not be set too large to avoid affecting the stability of Thomas biquad is a better choice for a high-order filter. the common-mode loop.The GBW of the amplifier should be This eighth order Butterworth filter consists of four cas wide enough to conquer the gain peaking around the cut-off caded biquads.The high O biquad is placed in the head of the frequency.The GBW requirement can be shown as[51 filter chain to optimize the noise performance.Here,the capac- itors are designed to be a programmable switched-capacitor ar- GBW≥ geelL+ac0aeoaue. (11) ray with binary-weighting to obtain an adjustable RC constant, where Ac(j@c)is the open loop gain of the amplifier,wc is the which is controlled by 6-bit digital signals.The selection of re- cut-off frequency of the filter,and 6 is the error in the transform sistor and capacitor value is a trade-off between die area and function.The simulation results show the differential-mode power. GBW 464 MHz with phase margin 86,and the common- 3.2.Amplifier design mode GBW 103 MHz with phase margin 60.The power con- sumption is 490 uA for every amplifier. The amplifier in the Tow-Thomas biquad is shown in 3.3.Tuning circuit design Fig.5.A fully differential two-stage amplifier is selected to improve the differential gain and drive the following resistor An accurate cut-off frequency is necessary in the channel load.A common-mode feedback circuit is introduced to sta- selection filter to satisfy both channel selection and ACR.To bilize the common-mode outputs of the fully differential two- meet the +5%frequency variation required by the system,a stage amplifier.The gates of transistors M12 and M15 connect Master-Slave tuning circuit is introduced to adjust the abso- with the amplifier outputs to detect the common-mode voltage. lute precision by relative precision.Every tuning circuit needs Compared with the voltage Vem,the error of common-mode an absolute reference.Commonly,there are only two absolute voltage is fed back through the bias network M16.M3 and M4. references,which are bandgap voltage and crystal frequency and finally works on the voltage Voutp and Voutn.A pole which Here the frequency of the crystal oscillator is chosen to keep 115002-4
J. Semicond. 30(11) Zou Liang et al. Fig. 5. A fully differential two-stage amplifier. Fig. 6. (a) Bode diagram of differential-mode signal; (b) Bode diagram of common-mode signal. Sallen-Key biquad is more sensitive to PVT variation than the Tow-Thomas biquad, and its performance at high frequencies is susceptible to parasitic capacitance. Thus, here the TowThomas biquad is a better choice for a high-order filter. This eighth order Butterworth filter consists of four cascaded biquads. The high Q biquad is placed in the head of the filter chain to optimize the noise performance. Here, the capacitors are designed to be a programmable switched-capacitor array with binary-weighting to obtain an adjustable RC constant, which is controlled by 6-bit digital signals. The selection of resistor and capacitor value is a trade-off between die area and power. 3.2. Amplifier design The amplifier in the Tow-Thomas biquad is shown in Fig. 5. A fully differential two-stage amplifier is selected to improve the differential gain and drive the following resistor load. A common-mode feedback circuit is introduced to stabilize the common-mode outputs of the fully differential twostage amplifier. The gates of transistors M12 and M15 connect with the amplifier outputs to detect the common-mode voltage. Compared with the voltage Vcm, the error of common-mode voltage is fed back through the bias network M16, M3 and M4, and finally works on the voltage Voutp and Voutn. A pole which located at p = gm16/Cn1,tol is additionally introduced into the common-mode loop. The gain of the common-mode circuit should not be set too large to avoid affecting the stability of the common-mode loop. The GBW of the amplifier should be wide enough to conquer the gain peaking around the cut-off frequency. The GBW requirement can be shown as[5] GBW > AC(jωC) δ − 1 [ 1 + AC ( jωC )]ωC , (11) where AC(jωC ) is the open loop gain of the amplifier, ωC is the cut-off frequency of the filter, and δ is the error in the transform function. The simulation results show the differential-mode GBW 464 MHz with phase margin 86◦ , and the commonmode GBW 103 MHz with phase margin 60◦ . The power consumption is 490 µA for every amplifier. 3.3. Tuning circuit design An accurate cut-off frequency is necessary in the channel selection filter to satisfy both channel selection and ACR. To meet the ±5% frequency variation required by the system, a Master–Slave tuning circuit is introduced to adjust the absolute precision by relative precision. Every tuning circuit needs an absolute reference. Commonly, there are only two absolute references, which are bandgap voltage and crystal frequency. Here the frequency of the crystal oscillator is chosen to keep 115002-4
Zou Liang et al. November 2009 VDD MOS CAP Error Amplifier L=6 um =400mV S3 comparator Out comparator b6 o- 0 cap AFT GND switch control Fig.7.Tuning circuit. the same dimension with constant RC.The method of realiz- voltages of input transistors.In Fig.7,if the comparator is ing RC tuning is to adjust the switched-capacitor array.The the same as the error amplifier,the systematic offset will be overall schematic of the proposed tuning circuit is shown in cancelled.The consideration of current mirrors is to minimize Fig.7161. the difference between currents 12 and I during the whole A voltage reference obtained from the bandgap output af- charging process.Here,the cascode transistors are used to im- ter voltage division separately connects the inputs of error am- prove the output resistance for good DC matching.The chan- plifier and comparator.A current reference of /Vref/Rref nel length of the current mirrors is 6 um and the overdrive can be obtained through the feedback of the error amplifier, voltage of MI and M2 transistors is designed to be as large and then a mirror current /2 can be generated to charge the as 400 mV to improve the matching,while there is still a switched-capacitor array to a voltage Vap.Vap and Vef volt- trade-off when sizing MI and M2,because large transistors ages are compared in a comparator.The comparison result en- may deteriorate clock feed-through effects,which will worsen ters into the AFT algorithm to form a feedback loop.By con- dynamic current mismatch.The MOS capacitor is engaged to trolling the digital input signals of the switched-capacitor ar- reduce clock feed-through.When the switched-capacitor array ray,Veap will be equal to Vref after tuning.The process can be is charging.Veap increases at the same time,and the current 12 shown as follows: will vary non-linearly.Thus,the value of Vref cannot be set m=是-袋-g如 too high.Meanwhile,the charging current should be designed (12) carefully to get a reasonable charging time. The detailed timing plan in one comparison step is illus- △t=RefC, (13) trated in Fig.8.The sizes of all the switches are as small as where At is the period multiples of the reference clock.Rref is possible to decrease the charge injection.When the transistor the on-chip poly resistor.The resistor Rref and the capacitor C M5 turns on,the voltage Veap is discharged to GND.The lager in the tuning circuit match the ones in the filter core circuit.So size of the transistor M5 will help to lower the turn-on resistor the constant time RrerC is determined by At after tuning and but increase the charge injection:it is a trade-off.When the maintains relative precision with the constant time of the filter transistor M6 turns on,the current /2 is generated by current core circuit.In other words,the cut-off frequency is tuned to mirrors.An initial time is usually needed for current settling. maintain the relative precision with the frequency of the refer- which will cause dynamic current mismatch.Since the tran- ence clock. sistor M6 is already on before the transistor M5 turns off,the Some useful design considerations are proposed as fol- initial settling is avoided to charge the capacitor C. lows.The amplifier offset,including random offset and sys- A binary-search algorithm is employed in AFT control tematic offset,affects the comparison result.Random offset logic to save calibration time.The clock frequency is 12.5 can be minimized by engaging big sizes and small overdrive MHz.The whole calibration needs six comparison steps, 115002-5
Zou Liang et al. November 2009 Fig. 7. Tuning circuit. the same dimension with constant RC. The method of realizing RC tuning is to adjust the switched-capacitor array. The overall schematic of the proposed tuning circuit is shown in Fig. 7[6] . A voltage reference obtained from the bandgap output after voltage division separately connects the inputs of error amplifier and comparator. A current reference of I1 = Vref/Rref can be obtained through the feedback of the error amplifier, and then a mirror current I2 can be generated to charge the switched-capacitor array to a voltage Vcap. Vcap and Vref voltages are compared in a comparator. The comparison result enters into the AFT algorithm to form a feedback loop. By controlling the digital input signals of the switched-capacitor array, Vcap will be equal to Vref after tuning. The process can be shown as follows: Vcap = Q C = I2∆t C = I1∆t C = Vref RrefC ∆t, (12) ∆t = RrefC, (13) where ∆t is the period multiples of the reference clock. Rref is the on-chip poly resistor. The resistor Rref and the capacitor C in the tuning circuit match the ones in the filter core circuit. So the constant time RrefC is determined by ∆t after tuning and maintains relative precision with the constant time of the filter core circuit. In other words, the cut-off frequency is tuned to maintain the relative precision with the frequency of the reference clock. Some useful design considerations are proposed as follows. The amplifier offset, including random offset and systematic offset, affects the comparison result. Random offset can be minimized by engaging big sizes and small overdrive voltages of input transistors. In Fig. 7, if the comparator is the same as the error amplifier, the systematic offset will be cancelled. The consideration of current mirrors is to minimize the difference between currents I2 and I1 during the whole charging process. Here, the cascode transistors are used to improve the output resistance for good DC matching. The channel length of the current mirrors is 6 µm and the overdrive voltage of M1 and M2 transistors is designed to be as large as 400 mV to improve the matching, while there is still a trade-off when sizing M1 and M2, because large transistors may deteriorate clock feed-through effects, which will worsen dynamic current mismatch. The MOS capacitor is engaged to reduce clock feed-through. When the switched-capacitor array is charging, Vcap increases at the same time, and the current I2 will vary non-linearly. Thus, the value of Vref cannot be set too high. Meanwhile, the charging current should be designed carefully to get a reasonable charging time. The detailed timing plan in one comparison step is illustrated in Fig. 8. The sizes of all the switches are as small as possible to decrease the charge injection. When the transistor M5 turns on, the voltage Vcap is discharged to GND. The lager size of the transistor M5 will help to lower the turn-on resistor but increase the charge injection; it is a trade-off. When the transistor M6 turns on, the current I2 is generated by current mirrors. An initial time is usually needed for current settling, which will cause dynamic current mismatch. Since the transistor M6 is already on before the transistor M5 turns off, the initial settling is avoided to charge the capacitor C. A binary-search algorithm is employed in AFT control logic to save calibration time. The clock frequency is 12.5 MHz. The whole calibration needs six comparison steps, 115002-5
J.Semicond.30(11) Zou Liang et al. k可ΠA凡678可网风风34可凡2A凡 S2 charge charge SI sample reset S3 comparator works -600mV Ve charge injection Out comparator Fig.8.Detailed timing plan in one comparison step. n=4 _n=2. b1 b2 b3 b0 b1 b2 b3 fo 000025MHz 10003.0MHz 11003.5MHz 11104.0MHz Fig.10.Switched-resistor array. To cover the +20%variation of resistors and capacitors over different process corners and to satisfy +5%tuning pre- cision,Cmax/Cmin =2.25/1 and n=6 are chosen,and the quan- tization error is 1.4%.Furthermore,in the same chip,the re- sistor and capacitor mismatch can be controlled within 0.5% n=16 and 0.2%separately with suitable size and excellent layout. Besides RC mismatch,current mismatch is another important contribution,which can be designed to be below 0.5%.All the other contributions such as charge injection and charge sharing should be controlled within 0.4%,thus the total tun- Fig.9.6-bit digital controlled switched-capacitor array. ing error can be controlled under +3%in 4-MHz cut-off fre- taking only 7.68 us. quency mode,which is the calibration reference.Consider that the cut-off frequency will vary within +2%when other cut-off 3.4.Tuning error frequency modes are selected,which will be shown below.Fi- nally,the worst tuning error can be restricted below +5%. Error factors which affect the tuning precision can be summarized as follows:quantization error of the switched- 3.5.Adjustable cut-off frequencies in low-IF and zero-IF capacitor array,resistor and capacitor mismatch between the modes master and slave circuits,current mismatch,offset voltage of the comparator,charge injection of MOS switches,clock feed- In our DVB tuner,system design specifies that the cut-off through,etc. frequency can be changed between 5,6.7 and 8 MHz to cover The programmable switched-capacitor array in Fig.9 is all the DVB-T/H protocols,and then the cut-off frequency also considered as a capacitor digital-to-analog converter(CAP- should be changed between 2.5,3,3.5 and 4 MHz for zero-IF DAC)whose input is a digital signal and output is capacitance. architecture and between 5,6,7 and 8 MHz for low-IF archi- tecture. -Ca+2-)Co. (14) The precise cut-off frequency can be obtained by the tun- ing circuit above.When the tuning circuit finishes,the cut-off Cmin =Cfx, (15) frequency of the filter can be changed between 2.5,3,3.5 and 4 MHz using a switched-resistor array in Fig.10.All these Ccenter =VCmax Cmin (16) cut-off frequencies maintain relative precision with each other The quantization error of CAP-DAC is so that only one cut-off frequency reference should be cho- _Co/2-1 sen to be tuned.Here,the cut-off frequency of 4 MHz is cho- Eg二Ccenter (17) sen to be tuned as the reference.The shunt impedance intro- duced by switch transistors should be considered to obtain pre- where n is the number of digital control bits. cise matching between different cut-off frequencies.When the 115002-6
J. Semicond. 30(11) Zou Liang et al. Fig. 8. Detailed timing plan in one comparison step. Fig. 9. 6-bit digital controlled switched-capacitor array. taking only 7.68 µs. 3.4. Tuning error Error factors which affect the tuning precision can be summarized as follows: quantization error of the switchedcapacitor array, resistor and capacitor mismatch between the master and slave circuits, current mismatch, offset voltage of the comparator, charge injection of MOS switches, clock feedthrough, etc. The programmable switched-capacitor array in Fig. 9 is considered as a capacitor digital-to-analog converter (CAPDAC) whose input is a digital signal and output is capacitance. Cmax = Cfix + ( 2 − 1 2 n−1 ) C0, (14) Cmin = Cfix, (15) Ccenter = √ CmaxCmin. (16) The quantization error of CAP-DAC is Eq = C0/2 n−1 Ccenter , (17) where n is the number of digital control bits. Fig. 10. Switched-resistor array. To cover the ±20% variation of resistors and capacitors over different process corners and to satisfy ±5% tuning precision, Cmax/Cmin = 2.25/1 and n = 6 are chosen, and the quantization error is 1.4%. Furthermore, in the same chip, the resistor and capacitor mismatch can be controlled within 0.5% and 0.2% separately with suitable size and excellent layout. Besides RC mismatch, current mismatch is another important contribution, which can be designed to be below 0.5%. All the other contributions such as charge injection and charge sharing should be controlled within 0.4%, thus the total tuning error can be controlled under ±3% in 4-MHz cut-off frequency mode, which is the calibration reference. Consider that the cut-off frequency will vary within ±2% when other cut-off frequency modes are selected, which will be shown below. Finally, the worst tuning error can be restricted below ±5%. 3.5. Adjustable cut-off frequencies in low-IF and zero-IF modes In our DVB tuner, system design specifies that the cut-off frequency can be changed between 5, 6, 7 and 8 MHz to cover all the DVB-T/H protocols, and then the cut-off frequency also should be changed between 2.5, 3, 3.5 and 4 MHz for zero-IF architecture and between 5, 6, 7 and 8 MHz for low-IF architecture. The precise cut-off frequency can be obtained by the tuning circuit above. When the tuning circuit finishes, the cut-off frequency of the filter can be changed between 2.5, 3, 3.5 and 4 MHz using a switched-resistor array in Fig. 10. All these cut-off frequencies maintain relative precision with each other so that only one cut-off frequency reference should be chosen to be tuned. Here, the cut-off frequency of 4 MHz is chosen to be tuned as the reference. The shunt impedance introduced by switch transistors should be considered to obtain precise matching between different cut-off frequencies. When the 115002-6
Zou Liang et al. November 2009 700 600 400 uning- (su)dno 300 200 100 456 Frequency(GHz) Fig.11.Chip microphotograph Fig.13.Simulated group delay 30 s -20 40 201x)Kelad dnouD -60 -80 4 5 -100 0 Frequency(GHz) 10 Frequency (Hz) Fig.14.Measured group delay Fig.12.Frequency response. Mkr1 508 kH: Rof Atten 10 dB -51.9428 cutoff frequencies 2.5,3,3.5 and 4 MHz are achieved,we can 15MH也 2MHz obtain the other corresponding cut-off frequencies 5.6.7 and 8 MHz respectively by halving the switched-capacitor value automatically Average 100 4.Experimental results 1MHz 2.5MHz The proposed filter circuit was fabricated in SMIC 0.18 um technology.A chip microphotograph is shown in Fig.11, and die area of the filter including both I and Q channels is Swp 1.03 x 0.93 mm2 including 0.3 x 0.25 mm2 for the AFT tun- Center 1.750 MHz S01.907HHE ing circuit.An off-chip buffer is used to convert the differential R5B刚62k州 VBm62地 S#66p189.2ms(601pts) signal into a single-end signal,providing a 50 driver for the Fig.15.Measured in-band IM3. test purpose.6 dB gain is introduced by this off-chip buffer.In Fig.12.60 dB ACR is achieved at 20 MHz in the 8-MHz cut- cut-off frequencies ranging from 2.5 to 8 MHz can be tuned to off frequency mode and frequency attenuation at the stop-band less than +5%.This is enough to satisfy both the requirement below-80 dB.The minimum-3 dB frequencies 1.6 MHz and of ACR and EVM loss.In Figs.13 and 14,precise in-band maximal-3 dB frequencies 15 MHz can be achieved.Perfect group delay is achieved compared with the simulation results. stop-band attenuation will help to alleviate the out-band linear- In Figs.15 and 16,two-tone tests with input power-11 ity requirement of the following VGA(variable gain amplifier) dBm are shown.which indicate that the in-band IM achieves and provide good anti-aliasing performance for the following -52 dB with-11 dBm input power at 2 MHz 1.5 MHz,and ADC. the out-band IM3 achieves-55 dB with-11 dBm input power Lots of measurement results show that the precision of at 16 MHz 28 MHz.So,the out-band IIP3 can be calculated the cut-off frequency 4 MHz,which is chosen as the calibra- as +16.5 dBm,which satisfies the system requirements,and tion reference,can be tuned to less than +3%,and all the other an in-band IIP3 of +15 dBm can be obtained.Finally,the 115002-7
Zou Liang et al. November 2009 Fig. 11. Chip microphotograph. Fig. 12. Frequency response. cutoff frequencies 2.5, 3, 3.5 and 4 MHz are achieved, we can obtain the other corresponding cut-off frequencies 5, 6, 7 and 8 MHz respectively by halving the switched-capacitor value automatically. 4. Experimental results The proposed filter circuit was fabricated in SMIC 0.18 µm technology. A chip microphotograph is shown in Fig. 11, and die area of the filter including both I and Q channels is 1.03 × 0.93 mm2 including 0.3 × 0.25 mm2 for the AFT tuning circuit. An off-chip buffer is used to convert the differential signal into a single-end signal, providing a 50 Ω driver for the test purpose. 6 dB gain is introduced by this off-chip buffer. In Fig. 12, 60 dB ACR is achieved at 20 MHz in the 8-MHz cutoff frequency mode and frequency attenuation at the stop-band below –80 dB. The minimum –3 dB frequencies 1.6 MHz and maximal –3 dB frequencies 15 MHz can be achieved. Perfect stop-band attenuation will help to alleviate the out-band linearity requirement of the following VGA (variable gain amplifier) and provide good anti-aliasing performance for the following ADC. Lots of measurement results show that the precision of the cut-off frequency 4 MHz, which is chosen as the calibration reference, can be tuned to less than ±3%, and all the other Fig. 13. Simulated group delay. Fig. 14. Measured group delay. Fig. 15. Measured in-band IM3. cut-off frequencies ranging from 2.5 to 8 MHz can be tuned to less than ±5%. This is enough to satisfy both the requirement of ACR and EVM loss. In Figs. 13 and 14, precise in-band group delay is achieved compared with the simulation results. In Figs. 15 and 16, two-tone tests with input power –11 dBm are shown, which indicate that the in-band IM3 achieves –52 dB with –11 dBm input power at 2 MHz & 1.5 MHz, and the out-band IM3 achieves –55 dB with –11 dBm input power at 16 MHz & 28 MHz. So, the out-band IIP3 can be calculated as +16.5 dBm, which satisfies the system requirements, and an in-band IIP3 of +15 dBm can be obtained. Finally, the 115002-7
J.Semicond.30(11) Zou Liang et al. Table 3.Summary of the measurement results Parameter Value Technology 0.18 um CMOS process Supply voltage 1.8V Power consumption 4mA×1.8V=7.2mW Area (for both I &O channels) 1.03 x 0.93 mm2 (Filter core) 0.3 x 0.25 mm2 (Tuning circuit) _3 dB frequency 2.5,3.3.5.4MHz 5,6,7,8MHz Pass-band ripple @2.5,3.3.5,4 MHz 60dB Stop-band >80dB In-band group delay variation with different cut-off frequencies 120-300ns In-band IM3 Input power-11 dBm (f-3dB=8 MHz,fsignal =2 MHz 1.5 MHz) -52dB (In-band IIP3 +15 dBm) Out-band IM3 Input power-11 dBm (f-3dB =8 MHz,fsignal =16 MHz 28 -55dB MHz) (Out-band IIP3 +16.5 dBm) Noise figure 41 dB Tuning error f_3B 4 MHz ±3% The other f-3dB ±5% Tuning time 7.68μs Table 4.Performance comparison. Reference Ref.[6] Ref.[7] Ref.[8] This work Technology 0.18 um CMOS 0.35 um SiGe BiCMOS 0.18 um BiCMOS 0.18 um CMOS Application DAB/T-DMB tuner DBS-tuner DVB-T/H tuner Supply(V) 1.8 2.7 1.8 Power consumption(mA) 4.5 13 4.3 Area(mm2) 1.395 0.5 2.86 1.03 Filter orders 8 7 5 8 Cut-off frequency (MHz) 1.58 4-40 1.92 1.6-15 Stop-band attenuation (dB) 65 43 64 80 In-band IIP3 (dBm) +4.6 +10 +11 +15 Hikr4 12.80 MHz Ref -58 dBa Atten 10 dB -77.498c®a 5.Conclusion 4MHz An eighth order active-RC filter with automatic fre- quency tuning for DVB tuner applications is proposed in this paper.The programmable cut-off frequency is tuned using switched-resistor arrays and switched-capacitor arrays,thus it A12MH他3 can cover all the DVB-T/H protocols and is suitable for both 孕MH些8 low-IF and zero-IF architectures.Frequency response mea- surements show +5%tuning precision and 60 dB frequency attenuation at 20 MHz.This will be useful to alleviate the re- quirements of the following VGA and ADC and reduce the ef- Center 15.50 MHz Span 29 MHz R5B酬51h VBH 51 kHz Sweep 42.52 ms (601 pts) fect of out-band blockers.The results of two-tone testing show Fig.16.Measured out-band IM3. -52 dB in-band IM3 and-55 dB out-band IM3 with-11 dBm input power.The proposed filter circuit,fabricated in a SMIC performance of the proposed filter is summarized in Table 3, 0.18 um CMOS process,consumes only 4 mA current with and a performance comparison is given in Table 4. 1.8 V power supply. 115002-8
J. Semicond. 30(11) Zou Liang et al. Table 3. Summary of the measurement results. Parameter Value Technology 0.18 µm CMOS process Supply voltage 1.8 V Power consumption 4 mA × 1.8 V = 7.2 mW Area (for both I & Q channels) 1.03 × 0.93 mm2 (Filter core) 0.3 × 0.25 mm2 (Tuning circuit) –3 dB frequency 2.5, 3, 3.5, 4 MHz, 5, 6, 7, 8 MHz Pass-band ripple @ 2.5, 3, 3.5, 4 MHz @ 5, 6, 7, 8 MHz 60 dB > 80 dB In-band group delay variation with different cut-off frequencies 120–300 ns In-band IM3 @ Input power –11 dBm (f−3dB = 8 MHz, fsignal = 2 MHz & 1.5 MHz) –52 dB (In-band IIP3 +15 dBm) Out-band IM3 @ Input power –11 dBm (f−3dB = 8 MHz, fsignal =16 MHz & 28 MHz) –55 dB (Out-band IIP3 +16.5 dBm) Noise figure 41 dB Tuning error @ f−3dB 4 MHz @ The other f−3dB ±3% ±5% Tuning time 7.68 µs Table 4. Performance comparison. Reference Ref. [6] Ref. [7] Ref. [8] This work Technology 0.18 µm CMOS 0.35 µm SiGe BiCMOS 0.18 µm BiCMOS 0.18 µm CMOS Application DAB/T-DMB tuner DBS-tuner — DVB-T/H tuner Supply (V) 1.8 5 2.7 1.8 Power consumption (mA) 4.5 13 4.3 4 Area (mm2 ) 1.395 0.5 2.86 1.03 Filter orders 8 7 5 8 Cut-off frequency (MHz) 1.58 4–40 1.92 1.6–15 Stop-band attenuation (dB) 65 43 64 80 In-band IIP3 (dBm) +4.6 +10 +11 +15 Fig. 16. Measured out-band IM3. performance of the proposed filter is summarized in Table 3, and a performance comparison is given in Table 4. 5. Conclusion An eighth order active-RC filter with automatic frequency tuning for DVB tuner applications is proposed in this paper. The programmable cut-off frequency is tuned using switched-resistor arrays and switched-capacitor arrays, thus it can cover all the DVB-T/H protocols and is suitable for both low-IF and zero-IF architectures. Frequency response measurements show ±5% tuning precision and 60 dB frequency attenuation at 20 MHz. This will be useful to alleviate the requirements of the following VGA and ADC and reduce the effect of out-band blockers. The results of two-tone testing show –52 dB in-band IM3 and –55 dB out-band IM3 with –11 dBm input power. The proposed filter circuit, fabricated in a SMIC 0.18 µm CMOS process, consumes only 4 mA current with 1.8 V power supply. 115002-8
Zou Liang et al. November 2009 [5]Du D.Li Y.Wang Z.An active-RC complex filter with mixed References signal tuning system for low-IF receiver.IEEE Asia Pacific Conference on Circuits and Systems,2006:1031 [1]Sansen W.Distortion in elementary transistor circuits.IEEE [6]Kim S.Kim B.Jeong M S,et al.A 43 dB ACR low-pass Trans Circuits Syst II:Analog and Digital Signal Processing. filter with automatic tuning for low-IF conversion DAB T- 1999,46:315 DMB tuner IC.IEEE European Solid-State Circuits Confer- [2]EICTA.Mobile and portable DVB-T/H radio access.2007 ence,2005:319 [3]Walden R H.Analog-to-digital converter survey and analysis. [7]Chen Bei,Chen Fangxiong,Ma Heping,et al.A widely tunable IEEE J Sel Areas Commun,1999,17(4):539 continuous-time LPF for a direct conversion DBS tuner.Journal [4]Jussila J,Halonen K.Minimization of power dissipation of of Semiconductors,2009,30(2):025009 analog channel-select filter and Nyquist-rate AD converter in [8]Yoshizawa A.Tsividis Y P.Anti-blocker design techniques UTRA FDD.IEEE International Symposium on Circuits and for MOSFET-C filters for direct conversion receivers.IEEE J Systems,.2004.4:940 Solid-State Circuits,2002,37:357 115002-9
Zou Liang et al. November 2009 References [1] Sansen W. Distortion in elementary transistor circuits. IEEE Trans Circuits Syst II: Analog and Digital Signal Processing, 1999, 46: 315 [2] EICTA. Mobile and portable DVB-T/H radio access. 2007 [3] Walden R H. Analog-to-digital converter survey and analysis. IEEE J Sel Areas Commun, 1999, 17(4): 539 [4] Jussila J, Halonen K. Minimization of power dissipation of analog channel-select filter and Nyquist-rate AD converter in UTRA FDD. IEEE International Symposium on Circuits and Systems, 2004, 4: 940 [5] Du D, Li Y, Wang Z. An active-RC complex filter with mixed signal tuning system for low-IF receiver. IEEE Asia Pacific Conference on Circuits and Systems, 2006: 1031 [6] Kim S, Kim B, Jeong M S, et al. A 43 dB ACR low-pass filter with automatic tuning for low-IF conversion DAB TDMB tuner IC. IEEE European Solid-State Circuits Conference, 2005: 319 [7] Chen Bei, Chen Fangxiong, Ma Heping, et al. A widely tunable continuous-time LPF for a direct conversion DBS tuner. Journal of Semiconductors, 2009, 30(2): 025009 [8] Yoshizawa A, Tsividis Y P. Anti-blocker design techniques for MOSFET-C filters for direct conversion receivers. IEEE J Solid-State Circuits, 2002, 37: 357 115002-9
