第26卷第6期 半导体学报 Vol.26 No.6 2005年6月 CHINESE JOURNAL OF SEMICONDUCTORS June,2005 Analysis and Optimum Design of Differential Inductors Using Distributed Capacitance Model* Jian Hongyan,Tang Zhangwen,He Jie,and Min Hao (State Key Laboratory of ASIC &System,Fudan University,Shanghai 200433,China) Abstract:A distributed capacitance model for monolithic inductors is developed to predict the equivalently parasitical capacitances of the inductor.The ratio of the self-resonant frequency (fsR of the differential-driven symmetric in- ductor to the fse of the single-ended driven inductor is firstly predicted and explained.Compared with a single-ended configuration,experimental data demonstrate that the differential inductor offers a 127%greater maximum quality factor and a broader range of operating frequencies.Two differential inductors with low parasitical capacitance are developed and validated. Key words:distributed capacitance model;self-resonant frequency ratio;quality factor;differential inductor:op- timum design EEACC:2140;2530B;2550F CLC number:TN405 Document code:A Article ID:0253-4177(2005)06-1077-06 erties (e.g.power supply noise rejection).A sym- 1 Introduction metric inductor consumes less chip area as com- pared to single-ended equivalents when used in a A monolithic inductor is an important compo- typical circuit.A symmetric inductor that is excited nent in highly integrated radio frequency circuits differentially (also called a differential inductor) (RF ICs)for wireless communication systems.But can realize a substantially greater factor without al- a monolithic inductor has a low quality factor Q tering the fabrication process[2). due to metal ohmic loss and conductive silicon sub- The distributed capacitance model(DCM)for strate loss.Many researchers found quite a few monolithic inductors,which is for a single-ended methods to improve the Q of the monolithic induc-inductor but not for the differential inductor has tor[].The Q and fsr (self-resonant frequency)are been studied in recent years[s-5]. the two most important parameters of the mono- In this paper,from the view of the parasitical lithic inductor.The lower parasitical capacitance capacitance of the inductor,the reason for a differ- the inductor has,the higher Q and fsr are. ential inductor with both a higher Q and fsr is ana- It should be noted that the differential circuits lyzed and firstly interpreted by DCM.Two differ- (amplifiers,mixers,and oscillators)are commonly ential inductors with the low equivalently parasit- used in monolithic transceiver designs because of ical capacitances (Cmm)between the two terminals their robustness and superior noise rejection prop-are developed and validated. Project supported by the Shanghai Science 8.Technology Committee(No.037062019) Jian Hongyan male.PhD candidate.He is interested in monolithic inductor and antenna optimization,RF circuits design such as LNA.mixer. and VCO,and antenna design for RFID.Email:hyjian@fudan.edu.cn Received 14 November 2004,revised manuscript received 1 February 2005 2005 Chinese Institute of Electronics
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1078 半导体学报 第26卷 2 Cm(-1,+I)Cn,+2) Distributed capacitance model ! Inductors that are driven differentially or sin- C(2.2n-2)Cnm(2n-l,3 gle-ended (See Fig.1)have different equivalent (1,2-1)C2n.2) parasitic capactiances (C).The equivalent capaci- tance of the spiral inductor can be expressed asts] Cen=Cm.m+Cm (1) -】 Cm(2) C1) Cm(2n)Cm(2-1) (a) (b) c (a) C(-1+1)Cl(nn+2) Signal ground m3,2n-2)Cm2-]3) ,2n-IC2n,2 C C(+1) C(n) Cm(叶2元 Fig.1 Planar monolithic inductors with the same track (2-20 C(0 width,space,inner,and outer radius (a)Differential- (b) driven symmetric configuration (DSPI);(b)Single-en- ded-driven symmetric configuration (SSPI);(c)Single- ended spiral configuration (SEPI)1,2.3.4.5,and 6 are current flow direction in inductor,i.e.AC signal C.(n-1n) voltage profile or half-turns serial number;Capacitances C(n C.(n-2.n-1 (H+1,n+2) are the equivalently parasitical capacitance of the mono- m(2,3) C(2n-2.2n-1) lithic inductor. m1.2) (2m-1.2) The DSPI can be regarded as two single-ended pla- Cm(2-1)2 2n.0) nar inductors having same the Cm,whose connec- tion point is signal ground and whose Cm.are in se- (c) ries.The Cmm of the DSPI are partly in series con- nection and partly in parallel as shown in Fig.2 Fig.2 Voltage profile and distributed capacitance (a).The Cmm of the SSPI are partly in series con- model of the n-turn planar inductor (a)DSPI;(b) nection and partly in parallel and its Cm are in par- SSPI:(e)SEPI allel as shown in Fig.2(b).The Cm of the SEPI This paper also applies the same method for the are in series connection and its Cm are in parallel. differential inductors.The fundamental assump- Voltage profiles of three inductors are different as tions of the DCM can be derived from the voltage shown in Fig.2. distribution over the inductor,which is called volt- 2.1 Assumptions and definitions age profile.For the conveniences of calculation and analysis,the following assumptions are made. To accurately quantify the Cmm and Cm,inin- (1)The same layer metal traces of the induc- ductors,the DCM can be used to analytically calcu- tor have the same resistivity o,current,metal track late them rather than qualitatively approximate. width w(at least in the same half-turn),and metal The DCM is validated by the previous papersts. thickness t;
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第6期 Jian Hongyan et al.Analysis and Optimum Design of Differential Inductors Using... 1079 (2)Voltage distribution is proportional to the lengths of the metal tracks; Eu=Cud(Vi+Va+VVw）(6) (3)The kth unit voltage difference between Whatever the structure of the inductor is,the en- the adjacent half-turns is regarded as a constant tire Ee.m,can be figured by adding all the Ee.m and is determined by averaging the beginning volt- (m). age and the ending voltage of the half-turns,re- The two terminal voltages of the DSPI are gardless of the type of the inductor. ,and.respeetively.Hence The length of each half-turn can be defined as l2,...l,lz(n is the half-turn number,sequen- E=古×C.u.V=Cag 1 tial m represents current flow direction in the in- So, ductor),and the total length is defined as l(=l (6) +l2+..+l).The AC signal voltage of one ter- minal of the inductor is Voee,while that of the other where C is the equivalent capacitance between is Ved.By assumptions,AC signal voltage at the the metal track and the substrate of the DSPI. end terminal of the mth half-turn inductor [Vend The signal terminal voltage of the SEPI is V, (m)]can be expressed as and that of the other terminal is 0,hence E。i= ×Clg=Cg Vend (m)= (Vhet-Veod) (2) L tot So, The AC signal voltage at the beginning termi- (7) nal of the mth half-turn inductor [Vbeg (m)]equals Vend (m-1).Vbee (0)=Vbes. where Cmss is the equivalent capacitance between the metal track and the substrate of the SEPI. 2.2 Equivalent capacitance formula According to Eqs.(6)and(7),under the same The lowest layer metal track of the mth half- equivalent-area between the metal track and the turn inductor is equally divided into k units (i substrate,we can get the following equation )According to assumption (2),the voltage of CCa (8) the ith unit is Vi, V,=Vx(m)-t△Vn(d (3) 2.3 Equivalent capacitance Cm.m formula where.(智Vsm）-Vam.There The voltage difference between the ith and jth half-turn can be expressed as fore,the electrical energy stored in the capacitor between the ith unit metal and the substrate can be AVi =Vi-V)= X (Vbes -Vend), expressed as l tot △E.()-2Ci(AV.P 0≤i,j≤n (9) The electrical energy stored in the equivalent =zc兴×[2Wm)-vam]④ capacitance between the metal tracks of the ith half-turn and jth half-turn can be expressed as where Cms represents the capacitance per unit area 2-2 between the mth half-turn and the substrate.The electrical energy stored in the equivalent capaci- tance between the metal tracks of the Lms(m)and Cw(4,+4)() the substrate can be derivedts] -1—(V-Vd)2(10)
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1080 半导体学报 第26卷 where Cm is the unit capacitance between the ith and ith adjacent half-turns of the inductor;W is the metal tracks width w of the inductor when the ith half-turn and ith half-turn are stacked or metal thickness t when the ith half-turn and jth half-turn are in the same layer. 1 Regardless of the structures (stacked,spiral, Fig.3 Die photos of the inductors in 0.35m CMOS symmetric,etc.)and driven modes (differentially processes (a)and one inductor with probes (b) or single-ended),the electrical energy stored in the equivalent capacitance between the metal can be be calculated when the inductance is gotten.Ac- expressed as the sum of the electrical energy stored cording to previous equations,the self-resonant fre- in the equivalent capacitance between the metal quency ratio of the optional two inductors with e- traces at the same layers and at the adjacent layers. quivalent inductance Lo,Lee and the equivalent Different Cmm formulas can be derived from Eq. capacitor Ce,Ce,respectively,can be expressed (10)and ECVv.).We define as Ratio/s= f the Cm of the DSPI as Cm,the Cmm of the (13) SSEI as C,and the Cm of the SEPI as The inductance Lunymmetrie equals Lmmetrie ap- Cm.Thus, proximately,if the current flows in the same direc- Cmnd雌=Cmn雄 tion along each adjacent conductor of the planar in- 2c.2-2)'+ ductors with the same geometric parameters [such as Figs.1(a),(b),and (c)],and the voltage differ- 2c-.2a-i+2u4+2)月 ence between the adjacent turns of the DSPI and SSPI is larger than those of the SEPI,so Cmmssm= (11) Cm.mDsP Cmm.SEI'but 4Cm.DoP Cmsssm Cmmsn,therefore,fsR osn>fsk ser fsR ssn and QDsPI>QsEPI >QsspI.This conclusion and Equation (13)can offer design guidelines for inductor and (12) circuit configurations. The self-resonant frequency ratio (Ratiofsg)of 3 Experiment and discussions the DSPI to the same inductor that is driven single- ended can be expressed as In order to verify accuracy,the inductors have been fabricated in a 0.35um two-poly four-metal 1<Ratio-f世- 4+CmCm5越<2 √1+Cm./Cm.雄 CMOS processes as shown in Fig.3.The prototype (14) chips also include the de-embed layouts to calibrate Figure 4(b)shows that the Ratiofsg decreases with the on-wafer testing wiring and pads.The S pa- the C/C.The Ratio/s can be predicted and rameters are measured by a network analyzer and explained from Eq.(14).Compared with a single- Cascade Microtech Probe Station using coplanar ended configuration,the experimental data demon- ground-signal-ground probes. strate that the differential inductor offers a 127% 3.1 Ratio of self-resonant frequency greater Qax and a much broader range of operating frequencies.In Fig.4(a)Ratiofss (L)/Ratiorsg (L2) The equivalent capacitance of the inductor can =1.55.The pn junction is formed at the interface
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第6期 Jian Hongyan et al.Analysis and Optimum Design of Differential Inductors Using... 1081 between the n-well and p-substrate,and the pn the space of adjacent turns with larger voltage junction capacitor is in series with the oxide capaci- difference as shown in Fig.5(b).According to Eq. tance between the inductor and the silicon sub- (6),the Cm will be reduced if the lowest metal strate,thus the equivalent Cm are greatly reduced, tracks layer of the stacked or 3D inductor has the but the Cmm of both inductors are the same,i.e. voltage which is nearer to the signal ground.Com- Cmm/Cmd is variable,which results in the differ- pared to the conventionally differential inductor ent Ratio The patterned ground shielding made with the same width and turns,two differential in- of the lowest layer metal reduces the substrate loss ductors with low Cmm structures have high Q and more than the patterned n-well floating does, fsk as shown in Fig.6. therefore,Q>Q at a low frequency and Qfsk. (a) O.(max) 15 (7.0.15.9) Qdn(max) (5.75,12.4 10 m/4 (max) 3.5.8.75) (a) (b) Q,.{max） Fig.5 Two differential inductors with low Cmm 1,2. (3.2.7.5) 138入17.0) 3.4.5.and 6 are current in inductor flow direction.i.e. (72) 13.75) AC signal voltage profile.In m,,i represents metal layer number. 10 Frequency/GHz O. 16335.14.2314 7.79.16) (b) 200 12 180H (7.4.14.1) (4,8.9 160 9i19.48 140 (2.4,7.7) 2.35,6.8 2(8.35 9I1) :869 Pwn(11.55入 1204 :(6.6 Q(655 017.25 0 8 12 20 10 Frequency/GHz 0.0010.010.1110100 Ratio Fig.6 Q and fsg of two differential inductors with low Fig.4 (a)Q factor as a function of fregnency;(b)Ra- Cmm La is the inductor in Fig.5(b)and Ls is the in- ductor in Fig.5(a);L and Ls are the conventionally dif- tio/sg as a function of Ratioc=C/Cm ferential inductor with the same width and turns as La 3.2 Optimum design o f differential inductor and L,respectively. The lower the total parasitic capacitance is,the 3.3 Prediction errors higher quality factor the inductor has.Two kinds Table 1 is the prediction errors of the induc- of optimum designs of the DSPI are developed. tors with the DCM.The prediction error of fs& C is reduced by decreasing the voltage differ- with the DCM is less than 10%,demonstrating the ence between the adjacent turns in Fig.5(a) accuracy of the DCM.The DCM would have higher through multilevel interconnects and by increasing accuracy for the different structure inductors if the
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1082 半导体学报 第26卷 current crowding effects are considered in assump- gy and Prof.Li Fuxiao,Shi Jiangwei of the Nanjing tion (2). 55th Research Institute of Information Industrial Department for measurements. Table 1 Prediction errors with DCM R Lsse Error/% 6.4 8.25.67.3 6.7 7.2 References fsk Lidn L2afL2t雄L4Lse Lsan Error/% 8.39.26.49.57.8 8.9 [1]Burghartz J N.Rejaei B.On the design of RF spiral inductors on silicon.IEEE Trans Electron Devices.2003,50(3):718 4 Conclusion [2]Danesh M.Long J R.Differentially driven symmetric micros- trip inductors.IEEE Trans Microw Theory Tech.2002,50 (1):332 The DCMs of inductors are developed to accu- 3 Wu C H.Tang CC.Liu S I.Analysis of monolithic spiral in- rately quantify the Cmm and the Cm,of the symmet- ductors using the distributed capacitance model.IEEE J Solid- ric and single-ended inductor.The Cm:of the dif- State Circuits.2003.38(6):1040 ferential inductor is only a quarter of the Cm:of the 4 Zolfaghari A.Chan A,Razavi B.Stacked inductors and trans- single-ended inductor,therefore,the differential in- formers in CMOS technology.IEEE J Solid-State Circuits. 2001,36(4):620 ductor has higher a Q and fs&.The ratio of the [5 Tang CC.Wu C H,Liu S I.Miniature 3-D inductors in stand- fsR din to the fsk se are firstly predicted and ex- ard CMOS process.IEEE J Solid-State Circuits.2002.37(4): plained.Two optimum differential-inductors with 471 low Cmm are developed and validated. [6 Tang Zhangwen.LC voltage-controlled oscillators.PhD Dis- sertation,Fudan University,2004 7 Maget J.Varactors and inductors for integrated RF circuits in Acknowledgments The authors would like to standard MOS technologies.PhD Dissertation.University of thank Prof.Sun Lingling,Dr.Hu Jiang of Hang- Bundeswehr.Neubiberg,Germany.2002 zhou University of Electronic Science &Technolo- 用分布电容模型分析和优化差分电感* 营洪彦唐长文何捷闵昊 (复旦大学专用集成电路与系统国家重点实验室，上海200433) 摘要：建立了预测片上等效寄生电容的片上电感分布电容模型.预测和解释了差分电感的自激振荡频率的差异， 实测数据显示，与单端驱动模式下的相同对称电感相比，差分驱动模式电感提高最大品质因数127%，具有更大的 工作频率范围.设计和验证了低寄生电容的差分电感. 关键词：分布电容模型；自激振荡频率比；品质因素；差分电感；优化设计 EEACC:2140;2530B:2550F 中图分类号：TN405 文献标识码：A 文章编号：0253-4177(2005)06-1077-06 *上海市科委资助项目（批准号：037062019） 营洪彦男，博士研究生，研究方向为片上电感和片上天线的优化设计，射频电路设计（例如低噪声放大器、混频器和压控振荡器等），射频识 别天线设计.Email:hyjian(@fudan.edu,cn 2004-11-14收到，2005-02-01定稿 ©2005中国电子学会
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