复旦大学：微电子工程教学资源（参考论文）Design and noise analysis of a fully-differential charge pump for phase-locked loops

Vol.30,No.10 Journal of Semiconductors October 2009 Design and noise analysis of a fully-differential charge pump for phase-locked loops* Gong Zhichao(宫志超)'，Lu Lei(卢磊)'，Liao Youchun(廖友春)2，and Tang Zhangwen(唐长文)l,t (1 ASIC System State Key Laboratory,Fudan University,Shanghai 201203,China) (2 Ratio Microelectronics Technology Co,Ld,Shanghai 200433,China) Abstract:A fully-differential charge pump(FDCP)with perfect current matching and low output current noise is realized for phase-locked loops (PLLs).An easily stable common-mode feedback (CMFB)circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1-2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18 um process.The measured output reference spur is-64 dBc to-69 dBc.The in-band and out-band phase noise is-95 dBc/Hz at 3 kHz frequency offset and-123 dBc/Hz at 1 MHz frequency offset respectively. Key words:fully-differential charge pump;mismatch;noise;common-mode feedback;phase-locked loop D0I:10.1088/1674-4926/30/10/105013 EEACC:1205 1.Introduction posed CMFB circuit is presented.The PLL architecture and FDCP circuit are described.A noise analysis for the charge Charge-pump (CP)based phase-lock loops (PLLs)are pump is presented. commonly used in modern communication systems.They have a wide frequency capture range and zero static phase er- ror.In practice,PLL performance deteriorates due to non-ideal 2.PLL architecture and FDCP circuit CP effects.Mismatch between charging and discharging cur- Figure 1 shows the fourth-order PLL architecture and the rents introduces a steady state phase error as well as reference spurs-31.Spurs may cause other channels to interfere with FDCP Loop filter the desired channel in a wide-band system.Also,CP current Icp/2 R noise contributes to PLL phase noise which directly affects transceiver performance.Thus,current mismatch and current UP noise are two major considerations in CP design. PFD Current mismatch comes from device mismatch, DN channel-length modulation,and parasitic capacitors.Many techniques have been employed to deal with these non-ideal Icp/2 effects.A replica technique in Ref.[4]can suppress channel- length modulation.Compensation techniques are employed to deal with clock feed-through and charge injection in Refs. Divider [5,6].Little attention has been paid to CP current noise in previous papers.However,CP noise is an important contri- bution to PLL phase noise,which is a significant design spec- ification in PLL design.Thus,it should be analyzed and sim- fdiv ulated carefully.Furthermore,a fully-differential structure is immune to environmental noise and the power supply ripple UP so that a fully-differential CP is preferred in a PLL.How- DN ever,a fully-differential change pump (FDCP)needs a stable common-mode feedback (CMFB)circuit which should con- tribute as little current noise and current mismatch as possible. In this paper,a perfect current matching FDCP with a pro- Fig.1.Fourth-order PLL and timing diagram when locked. Project supported by the National High Technology Research and Development Program of China(No.2007AA012282)and the National Natural Science Foundation of China (No.60876019). Corresponding author.Email:zwtang@fudan.edu.cn Received 4 April 2009,revised manuscript received 18 May 2009 C2009 Chinese Institute of Electronics 105013-1

Vol. 30, No. 10 Journal of Semiconductors October 2009 Design and noise analysis of a fully-differential charge pump for phase-locked loops∗ Gong Zhichao(宫志超) 1 , Lu Lei(卢磊) 1 , Liao Youchun(廖友春) 2 , and Tang Zhangwen(唐长文) 1, † (1 ASIC & System State Key Laboratory, Fudan University, Shanghai 201203, China) (2 Ratio Microelectronics Technology Co, Ltd, Shanghai 200433, China) Abstract: A fully-differential charge pump (FDCP) with perfect current matching and low output current noise is realized for phase-locked loops (PLLs). An easily stable common-mode feedback (CMFB) circuit which can handle high input voltage swing is proposed. Current mismatch and current noise contribution from the CMFB circuit is minimized. In order to optimize PLL phase noise, the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle. The calculation result agrees well with the simulation. Based on the noise analysis, many methods to lower output current noise of the FDCP are discussed. The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18 µm process. The measured output reference spur is –64 dBc to –69 dBc. The in-band and out-band phase noise is –95 dBc/Hz at 3 kHz frequency offset and –123 dBc/Hz at 1 MHz frequency offset respectively. Key words: fully-differential charge pump; mismatch; noise; common-mode feedback; phase-locked loop DOI: 10.1088/1674-4926/30/10/105013 EEACC: 1205 1. Introduction Charge-pump (CP) based phase-lock loops (PLLs) are commonly used in modern communication systems. They have a wide frequency capture range and zero static phase er￾ror. In practice, PLL performance deteriorates due to non-ideal CP effects. Mismatch between charging and discharging cur￾rents introduces a steady state phase error as well as reference spurs[1−3]. Spurs may cause other channels to interfere with the desired channel in a wide-band system. Also, CP current noise contributes to PLL phase noise which directly affects transceiver performance. Thus, current mismatch and current noise are two major considerations in CP design. Current mismatch comes from device mismatch, channel-length modulation, and parasitic capacitors. Many techniques have been employed to deal with these non-ideal effects. A replica technique in Ref. [4] can suppress channel￾length modulation. Compensation techniques are employed to deal with clock feed-through and charge injection in Refs. [5, 6]. Little attention has been paid to CP current noise in previous papers. However, CP noise is an important contri￾bution to PLL phase noise, which is a significant design spec￾ification in PLL design. Thus, it should be analyzed and sim￾ulated carefully. Furthermore, a fully-differential structure is immune to environmental noise and the power supply ripple so that a fully-differential CP is preferred in a PLL. How￾ever, a fully-differential change pump (FDCP) needs a stable common-mode feedback (CMFB) circuit which should con￾tribute as little current noise and current mismatch as possible. In this paper, a perfect current matching FDCP with a pro￾posed CMFB circuit is presented. The PLL architecture and FDCP circuit are described. A noise analysis for the charge pump is presented. 2. PLL architecture and FDCP circuit Figure 1 shows the fourth-order PLL architecture and the Fig. 1. Fourth-order PLL and timing diagram when locked. ∗ Project supported by the National High Technology Research and Development Program of China (No. 2007AA01Z282) and the National Natural Science Foundation of China (No. 60876019). † Corresponding author. Email: zwtang@fudan.edu.cn Received 4 April 2009, revised manuscript received 18 May 2009 ⃝c 2009 Chinese Institute of Electronics 105013-1

Gong Zhichao et al. October 2009 differ ential pair bias differential pair replica dither common- source M18 22 8eew过5 UPB M13M5 M6M14 OUTH OUTN 14M ON-M15 M小48w VN Fig.2.Differential CP circuit. timing diagram when the PLL is locked.The PLL employs a third-order passive filter which is configured differentially. 50 40 lup,IpN are the charging and discharging currents of the FDCP 30 respectively.r is the phase-frequency detector(PFD)reset de- lay which is designed to avoid the dead zonel7.T is the period 10 38:nA. 34 of the reference clock.The simplified open-loop transfer func- tion of the fourth-order PLL is -10 IcpKvCo 1+s/z Ho ()=2N(C+C+C)+sp2)(1+) -20… -30· 1) 40 where -50 1 Wz= RC1’ p2≈R1(C2+C3 00.216 1.512 Single-ended voltage (V) wp3≈RC2C3/C2+C3) (2) Fig.3.Simulated DC current mismatch. The FDCP comprises a differential CP circuit,a control on.Transistors MI-M8 are added to compensate the gate- signal generating circuit,and a CMFB circuit.The differential drain overlap capacitance of transistors M9-M16151.Their CP circuit in Fig.2 consists of two differential pairs,two repli- sources are floating,avoiding the extra DC current.When cur- cas and a current bias.Since charging and discharging currents rents are being switched,voltages at common-source nodes are switched in the differential pairs and do not need to be A.B.C and D dither,which will cause a low speed glitch in turned off,the working speed can be very high.Operational charging and discharging currents.If a large common-source amplifiers Al and A2 ensure equal voltages in nodes OUTP capacitor is added between A,B,C or D and ground or power, and P.OUTN and N respectively.Thus,voltages at common- the low speed glitch can be suppressedls1.However,common- source nodes A,B,C and D will remain unchanged before and source capacitors are not necessary in a fully-differential struc- after current switching.Two replicas and amplifiers A3 and ture.Low speed glitches of charging and discharging currents A4 are used to compensate channel-length modulation,which cancel each other if the time r is longer than the low speed makes the charging current perfectly match the discharging glitch lasting time.Thus,low speed glitches cannot affect the current!4).The simulated DC current mismatch is shown in PLL settling or introduce spurs.The differential output cur- Fig.3.The DC mismatch current is less than 50 nA from 0.216 rent with or without common-source capacitors is shown in to 1.512 V when charging and discharging currents are 50 uA. Fig.4.Low speed glitches in common-source nodes cannot af- Resistors R and R2 as well as capacitors Ci and C2 are added fect the differential output current.Current glitches are caused to filter out the high frequency noise of amplifiers A3 and A4. by the gate-drain overlap capacitance of transistors MI-M16 If the switching transistors M9-M16 work in the deep when charging or discharging current is switching.Further- triode region when turned on,half the charge in the MOS ca- more,common-source capacitors may increase the noise con- pacitance injects to output nodes,which can cause large cur- tribution from transistors M9-M16. rent glitches and results in serious mismatch.If they work in The control signal of transistors M9-M16 should be care- the saturation region when turned on,only the charge in the fully designed to ensure working in the saturation region when gate-drain overlap capacitance injects to output nodes.Thus, turned on.The control signal generating circuit in Fig.5 con- transistors M9-M16 are in the saturation region when turned sists of two buffers,two switching arrays,and two capacitors. 105013-2

Gong Zhichao et al. October 2009 Fig. 2. Differential CP circuit. timing diagram when the PLL is locked. The PLL employs a third-order passive filter which is configured differentially. IUP, IDN are the charging and discharging currents of the FDCP respectively. τ is the phase-frequency detector (PFD) reset de￾lay which is designed to avoid the dead zone[7] . T is the period of the reference clock. The simplified open-loop transfer func￾tion of the fourth-order PLL is H0 (s) = ICPKVCO 2πN (C1 + C2 + C3) 1 + s/ωz s 2 ( 1 + s / ωp2) (1 + s / ωp3), (1) where ωz = 1 R1C1 , ωp2 ≈ 1 R1 (C2 + C3) , ωp3 ≈ 1 R3C2C3/(C2 + C3) . (2) The FDCP comprises a differential CP circuit, a control signal generating circuit, and a CMFB circuit. The differential CP circuit in Fig. 2 consists of two differential pairs, two repli￾cas and a current bias. Since charging and discharging currents are switched in the differential pairs and do not need to be turned off, the working speed can be very high. Operational amplifiers A1 and A2 ensure equal voltages in nodes OUTP and P, OUTN and N respectively. Thus, voltages at common￾source nodes A, B, C and D will remain unchanged before and after current switching. Two replicas and amplifiers A3 and A4 are used to compensate channel-length modulation, which makes the charging current perfectly match the discharging current[4]. The simulated DC current mismatch is shown in Fig. 3. The DC mismatch current is less than 50 nA from 0.216 to 1.512 V when charging and discharging currents are 50 µA. Resistors R1 and R2 as well as capacitors C1 and C2 are added to filter out the high frequency noise of amplifiers A3 and A4. If the switching transistors M9–M16 work in the deep triode region when turned on, half the charge in the MOS ca￾pacitance injects to output nodes, which can cause large cur￾rent glitches and results in serious mismatch. If they work in the saturation region when turned on, only the charge in the gate-drain overlap capacitance injects to output nodes. Thus, transistors M9–M16 are in the saturation region when turned Fig. 3. Simulated DC current mismatch. on. Transistors M1–M8 are added to compensate the gate– drain overlap capacitance of transistors M9–M16[5]. Their sources are floating, avoiding the extra DC current. When cur￾rents are being switched, voltages at common-source nodes A, B, C and D dither, which will cause a low speed glitch in charging and discharging currents. If a large common-source capacitor is added between A, B, C or D and ground or power, the low speed glitch can be suppressed[5]. However, common￾source capacitors are not necessary in a fully-differential struc￾ture. Low speed glitches of charging and discharging currents cancel each other if the time τ is longer than the low speed glitch lasting time. Thus, low speed glitches cannot affect the PLL settling or introduce spurs. The differential output cur￾rent with or without common-source capacitors is shown in Fig. 4. Low speed glitches in common-source nodes cannot af￾fect the differential output current. Current glitches are caused by the gate-drain overlap capacitance of transistors M1–M16 when charging or discharging current is switching. Further￾more, common-source capacitors may increase the noise con￾tribution from transistors M9–M16. The control signal of transistors M9–M16 should be care￾fully designed to ensure working in the saturation region when turned on. The control signal generating circuit in Fig. 5 con￾sists of two buffers, two switching arrays, and two capacitors. 105013-2

J.Semicond.30(10) Gong Zhichao et al. 400T 200 with 2 pF common-souroe capacitors gain 300 without common-source capacitors 150 ....... ---phase 200 100 100 0 50 -100 200 50 300. 224 22.6 22.823.023.223.4 23.6 1 10 1001k10k100k1M10M Time(ns) Frequency (Hz) Fig.4.Differential output current with or without common-source Fig.7.Simulated CMFB loop bode diagram. capacitors. loop,two resistors and two capacitors to detect the common- mode voltage.Thus,the CMFB circuit will not affect the loop filter and can handle input voltage swing from ground to powerl6).The operation principle of the CMFB circuit is that the output common-mode voltage is detected and compared with a reference voltage VCM.The voltage difference is con- verted into an error current by a transconductance amplifier N DN DNBDNB (TA).The error current is fed back into output nodes OUTP and OUTN to adjust the common-mode voltage.The TA uses only 1 LA static current in each output branch.Furthermore, output-stage transistors have a large length,so the DC current Fig.5.Control signal generating circuit. mismatch introduced by the CMFB circuit can be minimized. OUTPI OUTN The dominant pole of the CMFB loop at nodes OUTP and OUTN is determined by the loop filter.Thus,the frequency amp amp characteristic of the CMFB circuit is like that of a single-stage amplifier.A simulated bode diagram of the CMFB circuit is VCM shown in Fig.7.The loop bandwidth is about 70 kHz,the phase margin is about 90. The FDCP is divided into twenty-five sub-FDCPs.Each sub-FDCP is composed of two 2 uA differential pairs and two 2 uA replicas.Thus,device matching between differen- tial pairs and replicas can be improved.Another advantage of this arrangement is that it is easy to adjust the CP current. VCM M3 OUTN 3.Noise analysis A charge pump is a linear time-varying system.The out- M M7 9 put current noise of the FDCP comes from the differential CP circuit and the CMFB circuit.The output current noise of the Fig.6.CMFB circuit. differential CP circuit can be deduced with the sampling prin- ciple. The buffers are simple one-stage amplifiers consuming 50 uA Firstly,the continuous output current noise must be cal- each.The switches are made of complementary MOS transis- culated.The noise from current bias is common-mode noise tors which can suppress clock feed-through and charge injec- which can be neglected.The differential noise power equals tion so that control signals can change smoothly.Complemen- twice the noise power of a single-ended circuit.For simplicity, tary switches can also ensure equal rising and falling times. only the left-hand side of the differential CP circuit is consid- The switching arrays are controlled by the PFD. ered.The replica can be modeled as an amplifier.In the differ- The easily stable CMFB circuit shown in Fig.6 is pro- ential pairs,the NMOS transistors work the same as PMOS posed.It has characteristics of low noise and introducing ultra- transistors.Thus,for brevity of analysis,only PMOS tran- small DC current mismatch.It employs two rail-to-rail ampli- sistors are considered.The noise contribution from switching fiers whose bandwidths are much larger than that of CMFB transistors M9-M16 is ultra-small and can be neglected 105013-3

J. Semicond. 30(10) Gong Zhichao et al. Fig. 4. Differential output current with or without common-source capacitors. Fig. 5. Control signal generating circuit. Fig. 6. CMFB circuit. The buffers are simple one-stage amplifiers consuming 50 µA each. The switches are made of complementary MOS transis￾tors which can suppress clock feed-through and charge injec￾tion so that control signals can change smoothly. Complemen￾tary switches can also ensure equal rising and falling times. The switching arrays are controlled by the PFD. The easily stable CMFB circuit shown in Fig. 6 is pro￾posed. It has characteristics of low noise and introducing ultra￾small DC current mismatch. It employs two rail-to-rail ampli- fiers whose bandwidths are much larger than that of CMFB Fig. 7. Simulated CMFB loop bode diagram. loop, two resistors and two capacitors to detect the common￾mode voltage. Thus, the CMFB circuit will not affect the loop filter and can handle input voltage swing from ground to power[6]. The operation principle of the CMFB circuit is that the output common-mode voltage is detected and compared with a reference voltage VCM. The voltage difference is con￾verted into an error current by a transconductance amplifier (TA). The error current is fed back into output nodes OUTP and OUTN to adjust the common-mode voltage. The TA uses only 1 µA static current in each output branch. Furthermore, output-stage transistors have a large length, so the DC current mismatch introduced by the CMFB circuit can be minimized. The dominant pole of the CMFB loop at nodes OUTP and OUTN is determined by the loop filter. Thus, the frequency characteristic of the CMFB circuit is like that of a single-stage amplifier. A simulated bode diagram of the CMFB circuit is shown in Fig. 7. The loop bandwidth is about 70 kHz, the phase margin is about 90 ◦ . The FDCP is divided into twenty-five sub-FDCPs. Each sub-FDCP is composed of two 2 µA differential pairs and two 2 µA replicas. Thus, device matching between differen￾tial pairs and replicas can be improved. Another advantage of this arrangement is that it is easy to adjust the CP current. 3. Noise analysis A charge pump is a linear time-varying system. The out￾put current noise of the FDCP comes from the differential CP circuit and the CMFB circuit. The output current noise of the differential CP circuit can be deduced with the sampling prin￾ciple. Firstly, the continuous output current noise must be cal￾culated. The noise from current bias is common-mode noise which can be neglected. The differential noise power equals twice the noise power of a single-ended circuit. For simplicity, only the left-hand side of the differential CP circuit is consid￾ered. The replica can be modeled as an amplifier. In the differ￾ential pairs, the NMOS transistors work the same as PMOS transistors. Thus, for brevity of analysis, only PMOS tran￾sistors are considered. The noise contribution from switching transistors M9–M16 is ultra-small and can be neglected 105013-3

Gong Zhichao et al. October 2009 A3 AA ●P Fig.8.Small-signal noise equivalent circuit for noise analysis because M9-M16 are cascode transistors.The small-signal -225 。calculated circuit for noise analysis is shown in Fig. :.... 一simulated 235 are the equivalent resistance,transconductance and noise of (ZH/Vap) the replica circuit,respectively.Gand A3 are the gain and in- 245 ,二g00oo的9ne0e0mo4 replica put equivalent noise of amplifier A3.are the noise M17-M20 of resister R and transistor M17 255 The continuous output current noise can be obtained from Fig.8 and simplified as 265 2100 10k 100k 10M nc,out Frequency (Hz) Fig.9.Calculated and simulated output current noise of the differen tial CP circuit. 1/sC1 8m.M9 R1+1/sC1 .M17 8m.M9 gds.M9 gds.M17 the noise contribution to the continuous output current noise (3) from the thermal noise of transistor M17. After the PLL is locked.is sampled out every T sec- Figure 9 shows the calculated and simulated output cur- onds.Each sample lasts for a period ofr.The spectrum of the rent noise of the differential CP circuit and noise contribu- sampling function is tion from different circuit components.The calculation re- s=) sin(πtnlT) sult agrees well with the simulation.In frequencies below n=0,±1，±2，..· (4) n 1 kHz the dominant noise contribution comes from both the So. replica and transistors M17-M20.In frequencies above 1 kHz the dominant noise contribution only comes from transistors = sin(πt/T) (5) M17-M20.The noise contribution from the replica decreases Sampled output current noise can be calculated through con- rapidly between 100 Hz and 100 kHz because the bandwidth volution betweenand f).In the convolution,the num- of the replica loop with a dominant pole at node RP (or RN) is less than 1 kHz.The non-dominant pole about at 2 MHz ber of sampling function harmonics which should be consid- comes from Ri and Ci (or R2 and C2). ered is related to the bandwidth of the noise.The bandwidth of The current noise from the CMFB circuit is not sampled. the noise contribution from the replica,resister RI and flicker Only transistors M6-M9 in Fig.6 contribute noise.The noise noise of transistor M17 is much smaller than 1/T,so only the from other parts is common-mode noise.Thus,the output cur- DC component of the sampling function needs to be consid- rent noise of the CMFB circuit is ered.The bandwidth of the noise contribution from the thermal noise of transistor M17 is almost unlimited,so all sampling (8) function harmonics need to be considered.Thus,the sampled output current noise can be obtained as whereandare current noise of transistors M6 and a=S02(p++Mn+e2孟Mm (6) M7 respectively. Figure 10 shows the simulated output current noise of where the differential CP circuit with and without common-source -2-别 (7) capacitors.It can be seen that the noise contribution from the CMFB circuit can be neglected.The simulation reveals that large common-source capacitors deteriorate noise perfor- put current noise from the replica and resister Ri respectively. mance greatly,especially at low frequencies.The reason for this is that switching transistors M9-M16 become the main isthe noise contribution to the continuous ouput cur noise contribution due to the complicated time-varying char- rent noise from the flicker noise of transistor M17.is acteristics of the differential CP circuit. 105013-4

Gong Zhichao et al. October 2009 Fig. 8. Small-signal noise equivalent circuit for noise analysis. because M9–M16 are cascode transistors. The small-signal circuit for noise analysis is shown in Fig. 8. Rrpl, gmrpl, v 2 n,rpl are the equivalent resistance, transconductance and noise of the replica circuit, respectively. G and v 2 n, A3 are the gain and in￾put equivalent noise of amplifier A3. v 2 n,r1, i 2 n, M17 are the noise of resister R1 and transistor M17. The continuous output current noise can be obtained from Fig. 8 and simplified as i 2 nc, out ≈     v 2 n, rpl + v 2 n, A3    gmrpl [ Rrpl||( 1 / sCrpl)]    2 + v 2 n, r1   ×      1/sC1 R1 + 1/sC1      2 g 2 m,m17 + i 2 n, M17         gm, M9 gm, M9 + gds, M9 + gds, M17       2 . (3) After the PLL is locked, i 2 nc, out is sampled out every T sec￾onds. Each sample lasts for a period of τ. The spectrum of the sampling function is S ( f = n T ) = sin(πτn/T) πn , n = 0, ±1, ±2, . . . (4) So, S(0) = τ T , S ( ±1 T ) = sin(πτ/T) π , . . . (5) Sampled output current noise can be calculated through con￾volution between i 2 nc,out and S(f). In the convolution, the num￾ber of sampling function harmonics which should be consid￾ered is related to the bandwidth of the noise. The bandwidth of the noise contribution from the replica, resister R1 and flicker noise of transistor M17 is much smaller than 1/T, so only the DC component of the sampling function needs to be consid￾ered. The bandwidth of the noise contribution from the thermal noise of transistor M17 is almost unlimited, so all sampling function harmonics need to be considered. Thus, the sampled output current noise can be obtained as i 2 n, out = S(0)2 ( i 2 n, rpl + i 2 n, r1 + i1/ f, M172 ) + e 2 i 2 th, M17, (6) where e 2 = ∑∞ n=−∞ S ( f = n T )2 , (7) i 2 n,rpl and i 2 n,r1 are the noise contribution to the continuous out￾put current noise from the replica and resister R1 respectively. i 2 1/ f, M17 is the noise contribution to the continuous output cur￾rent noise from the flicker noise of transistor M17. i 2 th, M17 is Fig. 9. Calculated and simulated output current noise of the differen￾tial CP circuit. the noise contribution to the continuous output current noise from the thermal noise of transistor M17. Figure 9 shows the calculated and simulated output cur￾rent noise of the differential CP circuit and noise contribu￾tion from different circuit components. The calculation re￾sult agrees well with the simulation. In frequencies below 1 kHz the dominant noise contribution comes from both the replica and transistors M17–M20. In frequencies above 1 kHz the dominant noise contribution only comes from transistors M17–M20. The noise contribution from the replica decreases rapidly between 100 Hz and 100 kHz because the bandwidth of the replica loop with a dominant pole at node RP (or RN) is less than 1 kHz. The non-dominant pole about at 2 MHz comes from R1 and C1 (or R2 and C2). The current noise from the CMFB circuit is not sampled. Only transistors M6–M9 in Fig. 6 contribute noise. The noise from other parts is common-mode noise. Thus, the output cur￾rent noise of the CMFB circuit is i 2 n, CMFB = 2 ( i 2 n, M6 + i 2 n, M7) , (8) where i 2 n, M6 and i 2 n, M7 are current noise of transistors M6 and M7 respectively. Figure 10 shows the simulated output current noise of the differential CP circuit with and without common-source capacitors. It can be seen that the noise contribution from the CMFB circuit can be neglected. The simulation reveals that large common-source capacitors deteriorate noise perfor￾mance greatly, especially at low frequencies. The reason for this is that switching transistors M9–M16 become the main noise contribution due to the complicated time-varying char￾acteristics of the differential CP circuit. 105013-4

J.Semicond.30(10) Gong Zhichao et al. -220m Mkr1 25.0 MHz with 2 pF common-source capacitors Ref 0 dBm Atten 10 dB -67.97dB without common-source capacitors Samp 225 CMFB nose e dB/ 230 235 Marker 25.000000MHz -67.970dB 240 53 -245 b 25900 1k 10k 100k 1M10M Frequency (Hz) Lente 1.9008GHz Span 60 MH2 Fig.10.Simulated output current noise of the differential CP circuit Res BH 568 kHz VBH 560 KHz Sweep 1 ms (601 pts) with and without common-source capacitors. Fig.12.Measured PLL spectrum. 70 Measured p) -100 110 Re 130 270m Fig.11.Die photograph 140 1M Based on the previous analysis,methods for improving 15900 10K 100k Frequency offset(Hz) the noise performance can be discussed.Firstly,the noise con- tribution from the CMFB circuit should be minimized.The Fig.13.Measured and calculated PLL phase noise. size of transistors M6-M9 in Fig.6 should be larger to de- 15 crease flicker noise.Each output branch uses only 1 uA current T.216 to decrease thermal noise.Thus,the output current noise of the 14 1213 CMFB circuit is much smaller than that of the differential CP circuit.Secondly,to lower the noise contribution from repli- (ZH9) 1.21 1.3 10 20.. 30 cas,the bandwidth of the replica loop is decreased by increas- ing the size of capacitors Cpl and Crr.In addition,the replica 12 current is increased to reduce its noise contribution.Thirdly, to lower the flicker noise of transistors M17-M20,their de- vice sizes are increased.Fourthly,though noise contribution 1.1 from amplifiers A3 and A4 can be neglected at low frequency, AFC Analog high frequency noise should be filtered out by resistor RI and 10 10 20 30 capacitor CI (or R2 and C2).Resistors Ri and R2 themselves Time(us) also generate noise at low frequencies,so they cannot be too Fig.14.Measured PLL settling time. large butions from different components in the frequency synthe- 4.Experimental results sizer.The calculated phase noise agrees well with the mea- sured result.Components which are the dominant contribu- The fully-differential charge pump is used in a 1-2 GHz tors of phase noise in the low frequency range are the refer- frequency synthesizer,which was fabricated in a SMIC 0.18 ence.the FDCP,and the VCO successively.The FDCP has a um CMOS 1P6M mixed-signal process.The power supply low phase noise contribution.The in-band and out-band phase is 1.8 V.The FDCP consumes 1.6 mW.A die photograph is noise is-95 dBc/Hz at 3 kHz offset and-123 dBc/Hz at 1 MHz shown in Fig.11.The die area of the FDCP is about 270 x frequency offset respectively.The measured PLL settling dia- 470 um2.Figure 12 shows the measured PLL spectrum.The gram is shown in Fig.14.The PLL settling time is composed measured output reference spur is-64 to-69 dBc. of the automatic frequency control (AFC)settling time and Figure 13 shows the measured PLL phase noise.It shows the analog settling time.The PLL loop is locked quickly after the measured and calculated phase noise and noise contri- AFC operation. 105013-5

J. Semicond. 30(10) Gong Zhichao et al. Fig. 10. Simulated output current noise of the differential CP circuit with and without common-source capacitors. Fig. 11. Die photograph. Based on the previous analysis, methods for improving the noise performance can be discussed. Firstly, the noise con￾tribution from the CMFB circuit should be minimized. The size of transistors M6–M9 in Fig. 6 should be larger to de￾crease flicker noise. Each output branch uses only 1 µA current to decrease thermal noise. Thus, the output current noise of the CMFB circuit is much smaller than that of the differential CP circuit. Secondly, to lower the noise contribution from repli￾cas, the bandwidth of the replica loop is decreased by increas￾ing the size of capacitors Crpl and Crpr. In addition, the replica current is increased to reduce its noise contribution. Thirdly, to lower the flicker noise of transistors M17–M20, their de￾vice sizes are increased. Fourthly, though noise contribution from amplifiers A3 and A4 can be neglected at low frequency, high frequency noise should be filtered out by resistor R1 and capacitor C1 (or R2 and C2). Resistors R1 and R2 themselves also generate noise at low frequencies, so they cannot be too large. 4. Experimental results The fully-differential charge pump is used in a 1–2 GHz frequency synthesizer, which was fabricated in a SMIC 0.18 µm CMOS 1P6M mixed-signal process. The power supply is 1.8 V. The FDCP consumes 1.6 mW. A die photograph is shown in Fig. 11. The die area of the FDCP is about 270 × 470 µm2 . Figure 12 shows the measured PLL spectrum. The measured output reference spur is –64 to –69 dBc. Figure 13 shows the measured PLL phase noise. It shows the measured and calculated phase noise and noise contri￾Fig. 12. Measured PLL spectrum. Fig. 13. Measured and calculated PLL phase noise. Fig. 14. Measured PLL settling time. butions from different components in the frequency synthe￾sizer. The calculated phase noise agrees well with the mea￾sured result. Components which are the dominant contribu￾tors of phase noise in the low frequency range are the refer￾ence, the FDCP, and the VCO successively. The FDCP has a low phase noise contribution. The in-band and out-band phase noise is –95 dBc/Hz at 3 kHz offset and –123 dBc/Hz at 1 MHz frequency offset respectively. The measured PLL settling dia￾gram is shown in Fig. 14. The PLL settling time is composed of the automatic frequency control (AFC) settling time and the analog settling time. The PLL loop is locked quickly after AFC operation. 105013-5

Gong Zhichao et al. October 2009 5.Conclusion [2]Herzel F,Fischer G,Gustat H.An integrated CMOS RF syn- thesizer for 802.11a wireless LAN.IEEE J Solid-State Circuits. A perfect matching low current noise fully-differential 2003,38(10):1767 charge pump with an easily stable CMFB circuit is presented. [3]Pellerano S,Levantino S,Samori C,et al.A 13.5-MW 5-GHz Mismatch and noise of the charge pump are two major fac- frequency synthesizer with dynamic-Logic frequency divider. tors affecting PLL performance.High DC current matching IEEE J Solid-State Circuits.2004.39(2):378 between charging and discharging currents is achieved with a [4]Lee JS.Keel M S.Lim S I,et al.Charge pump with perfect replica circuit.Current glitches are suppressed with compen- current matching characteristics in phase-locked loops.Elec- sation transistors.The output current noise of the FDCP is an- tron Lett,2000.36(23):1907 alyzed in detail and the noise performance is optimized.The [5]Cheng S,Tong H,Silva-Martinez J,et al.Design and analysis FDCP is realized in a PLL with SMIC 0.18 um CMOS tech- of an ultrahigh-speed glitch-free fully differential charge pump nology and reaches reference spur levels of-64 to-69 dBc. with minimum output current variation and accurate matching. IEEE Trans Circuits SystⅡ，2006.53(9)：843 References [6]Yang Zhenyu,Tang Zhangwen,Min Hao.A high-performance fully differential charge pump for frequency synthesizer ap- [1]Razavi B.Challenges in the design of frequency synthesiz- plications.Chinese Journal of Semiconductors,2007,28(12): ers for wireless applications.IEEE Custom Integrated Circuits 1993 Conf.1997:395 [7]Gardner F M.Phase lock techniques.Wiley-Interscience,2005 105013-6

Gong Zhichao et al. October 2009 5. Conclusion A perfect matching low current noise fully-differential charge pump with an easily stable CMFB circuit is presented. Mismatch and noise of the charge pump are two major fac￾tors affecting PLL performance. High DC current matching between charging and discharging currents is achieved with a replica circuit. Current glitches are suppressed with compen￾sation transistors. The output current noise of the FDCP is an￾alyzed in detail and the noise performance is optimized. The FDCP is realized in a PLL with SMIC 0.18 µm CMOS tech￾nology and reaches reference spur levels of –64 to –69 dBc. References [1] Razavi B. Challenges in the design of frequency synthesiz￾ers for wireless applications. IEEE Custom Integrated Circuits Conf, 1997: 395 [2] Herzel F, Fischer G, Gustat H. An integrated CMOS RF syn￾thesizer for 802.11a wireless LAN. IEEE J Solid-State Circuits, 2003, 38(10): 1767 [3] Pellerano S, Levantino S, Samori C, et al. A 13.5-MW 5-GHz frequency synthesizer with dynamic-Logic frequency divider. IEEE J Solid-State Circuits, 2004, 39(2): 378 [4] Lee J S, Keel M S, Lim S I, et al. Charge pump with perfect current matching characteristics in phase-locked loops. Elec￾tron Lett, 2000, 36(23): 1907 [5] Cheng S, Tong H, Silva-Martinez J, et al. Design and analysis of an ultrahigh-speed glitch-free fully differential charge pump with minimum output current variation and accurate matching. IEEE Trans Circuits Syst II, 2006, 53(9): 843 [6] Yang Zhenyu, Tang Zhangwen, Min Hao. A high-performance fully differential charge pump for frequency synthesizer ap￾plications. Chinese Journal of Semiconductors, 2007, 28(12): 1993 [7] Gardner F M. Phase lock techniques. Wiley-Interscience, 2005 105013-6