A Fully Differential Charge Pump with Accurate Current Matching and Rail-to-Rail Common-Mode Feedback Circuit Zhenyu Yang,Zhangwen Tang,and Hao Min State Key Laboratory of ASIC System,Fudan University Shanghai,China Email:zyyang@fudan.edu.cn Abstract-A fully differential charge pump is proposed in this paper.It adopts the replica technique to eliminate the effect of II.CONVENTIONAL FULLY DIFFERENTIAL CHARGE PUMP channel-length modulation,and the charging and discharging Compared with the single-end charge pump,the fully currents can match well in a wide output range.A rail-to-rail differential cascode charge pump2 which is shown in Fig.1 common-mode feedback circuit is employed to ensure the large has larger output swing,better current matching characteristic swing of the charge pump unrestricted.The charge pump is and weaker effect of clock feedthrough. designed and fabricated in SMIC 0.18um CMOS process.The measured reference spur-level is about -73dBc and the in-band M-M2o form the cascode current mirrors to increase the phase noise is nearly-90dBc/Hz@1KHz.The power dissipation output impedance so that the current variation is less sensitive of the charge pump is only ImW. to the output voltage.M2~M24 are source-switches for the charge pump,which can minimize the turn-on and turn-off I.INTRODUCTION time.M2s~-M3o are used for replica biasing to give the same bias condition when the charge pump is tumned on.Capacitors Frequency synthesizers have been widely used in modern Ci and C2 are added to reduce the charge coupling to the gate. RF communication systems.The typical frequency synthesizer But,there are two drawbacks:(1)the cascode transistors M7. includes PFD,Charge pump,Loop filter,VCO and Divider. Ms and Mi3,Mi4 limit the output swing of the charge pump, Recently,the fully differential charge pump circuit has been which is not appropriate for the low supply voltage widely used in order to improve the spur performance,but the application.(2)as V-Vel becomes larger,the matching differential current matching characteristic in conventional characteristic of differential charging and discharging currents fully differential charge pumps2 will be worse because of will be worse. the effect of channel-length modulation.This paper presents a new fully differential charge pump circuit,which adopts the To illustrate this,let us define the output voltages as follows: replica technique to improve the current matching characteristic,without reducing the output swing. V V The contents of this paper are as follows.Section II Vop=Vom + (1) 2 analyses the drawbacks of conventional fully differential charge pumps.Section III describes the novel charge pump in detail.The microphotograph of the chip and the experimental where Vem is the desired common-mode voltage and Vairr is the differential-mode voltage.When the value of Vai isn't results are all presented in section IV,followed by the conclusions in section V. equal to zero,the values ofp Id Ip2 and Idn2 will change due to the effect of channel-length modulation.We can Vad charge pump assume for simplicity that: up2↓ Ipl=Im-△l,1h1=1m+△M (2) Lup2=Icm +Al,I4n2=Iom-Al 3 where Al 0 and Icm is the current when the output voltage is equal to Vem.So the mismatch of single-ended charging and M2止 discharging currents is: Ip1-11=-2△/，Ip2-1h2=2△M (3) s言 loop filter Fig.1 Conventional fully differential cascode charge pump circuit And the differential charging and discharging currents mismatch is: △=(Lp1-1h1)-(Ip2-1h2)=4AM (4) 978-1-4244-1684-4/08/$25.00©2008EEE 448
A Fully Differential Charge Pump with Accurate Current Matching and Rail-to-Rail Common-Mode Feedback Circuit Zhenyu Yang, Zhangwen Tang, and Hao Min State Key Laboratory of ASIC & System, Fudan University Shanghai, China Email: zyyang@fudan.edu.cn Abstract—A fully differential charge pump is proposed in this paper. It adopts the replica technique to eliminate the effect of channel-length modulation, and the charging and discharging currents can match well in a wide output range. A rail-to-rail common-mode feedback circuit is employed to ensure the large swing of the charge pump unrestricted. The charge pump is designed and fabricated in SMIC 0.18µm CMOS process. The measured reference spur-level is about -73dBc and the in-band phase noise is nearly -90dBc/Hz@1KHz. The power dissipation of the charge pump is only 1mW. I. INTRODUCTION Frequency synthesizers have been widely used in modern RF communication systems. The typical frequency synthesizer includes PFD, Charge pump, Loop filter, VCO and Divider. Recently, the fully differential charge pump circuit has been widely used in order to improve the spur performance, but the differential current matching characteristic in conventional fully differential charge pumps[1~2] will be worse because of the effect of channel-length modulation. This paper presents a new fully differential charge pump circuit, which adopts the replica technique to improve the current matching characteristic, without reducing the output swing. The contents of this paper are as follows. Section II analyses the drawbacks of conventional fully differential charge pumps. Section III describes the novel charge pump in detail. The microphotograph of the chip and the experimental results are all presented in section IV, followed by the conclusions in section V. Fig.1 Conventional fully differential cascode charge pump circuit II. CONVENTIONAL FULLY DIFFERENTIAL CHARGE PUMP Compared with the single-end charge pump, the fully differential cascode charge pump[2] which is shown in Fig. 1 has larger output swing, better current matching characteristic and weaker effect of clock feedthrough. M1~M20 form the cascode current mirrors to increase the output impedance so that the current variation is less sensitive to the output voltage. M21~M24 are source-switches for the charge pump, which can minimize the turn-on and turn-off time. M25~M30 are used for replica biasing to give the same bias condition when the charge pump is turned on. Capacitors C1 and C2 are added to reduce the charge coupling to the gate. But, there are two drawbacks: (1) the cascode transistors M7, M8 and M13, M14 limit the output swing of the charge pump, which is not appropriate for the low supply voltage application. (2) as |Vcp-Vcn| becomes larger, the matching characteristic of differential charging and discharging currents will be worse. To illustrate this, let us define the output voltages as follows: , 2 2 diff diff cp cm cp cm V V VV VV =+ =− (1) where Vcm is the desired common-mode voltage and Vdiff is the differential-mode voltage. When the value of Vdiff isn’t equal to zero, the values of Iup1ǃIdn1ǃIup2 and Idn2 will change due to the effect of channel-length modulation. We can assume for simplicity that: 1 1 2 2 , , up cm dn cm up cm dn cm I I II I I I I II I I = −Δ = +Δ = +Δ = −Δ (2) where ǻI > 0 and Icm is the current when the output voltage is equal to Vcm. So the mismatch of single-ended charging and discharging currents is: 11 2 2 2 , 2 up dn up dn I I II I I − =− Δ − = Δ (3) And the differential charging and discharging currents mismatch is: 11 2 2 ( )( ) 4 up dn up dn Δ= − − − =− Δ II II I (4) 978-1-4244-1684-4/08/$25.00 ©2008 IEEE 448
Comparing (3)and (4),the effect of channel-length modulation will reduce the matching characteristic of differential charging and discharging currents and increase the level of reference spurs. MI. PROPOSED CHARGE PUMP AND CMFB CIRCUIT A.Proposed charge pump circuit To overcome the two drawbacks analyzed above,a fully differential charge pump with replica method to achieve better M mismatch suppression is designed in this paper.As shown in evel shift level shi升 Fig.2.The rail-to-rail opamp Al and A2 presented in [3]have enough DC gain to ensure Vep and Ven to be equal.The Fig.3 The opamp Al(A2)with rail-to-rail input range structure of the opamp Al(A2)is shown in Fig.3. Where Irpiis the current when the output voltage is equal When"up”and“dn”are the logic low level,.the switches to Vlis the current variations in replica branches.For are closed,then the currents in charge pump branches(lupi, simplicity,define the variations of ldn and Idn2 are both Al,and lup2)and the currents in replica branches(Ip,Ip2)will satisfy the variations of In and In2 are both Alrplica,when the CMFB the relationship that: circuit is stable,we can induce that VaVpn.Therefore. Impl=Ipl =Im,Iop2 Ip2=In2 (5) In=Ian,ln2=l2,△Npia≈△M (8) Assuming So the differential charging and discharging currents mismatch will satisfy that 'p=',='m+ g,==-g (6) 2 2 △=(Lpl-lhi)-(p2-lh2） (9) =(n1-lhi)-(Un2-lh2)=0 When the value of Vair isn't equal to zero,the values of Ip,Idl,Iu2,Idne and the values of Ip,In,Ip2,In2 will change The current variations of conventional and proposed fully due to the effect of channel-length modulation.the differential charge pumps due to the effect of channel-length expressions are: modulation are shown in Table I.Because the match between PMOS and NMOS current sources has been converted to the match between two NMOS current sources,the proposed Lwp=Ip=In=Iroplicn +Alreplico charge pump can make the currents match better,and depress h=1n+△M the reference spurs in frequency synthesizer. (7) Table I Comparison of conventional and proposed charge pumps Vep>Vcn (apl-ldhl） replica charge pump Vdd charge pump replica Lup2-ldn2） conventional -△ △I △I -△I -4△I proposed △I -AI △I -△I ≈0 p1. B.Rail-to-rail CMFB circuit CMEB To ensure the large swing of the proposed charge pump unrestricted by CMFB circuit,a rail-to-rail input range CMFB circuit shown in Fig.4 is presented in this paper.Vp and Vh can be chosen as the input sampling signals of CMFB circuit in order not to change the value of zeros and poles in the loop filter.The buffer amplifiers A3 and A4 copy Vp and Vn to Vpl and VhI.The common-mode voltage Vem could be got through the RC sampling network,then the voltage Va,which is the loop filter loop filter comparative result of Vem and desired common-mode reference voltage Ve feeds back to the charge pump to tune the loop.Because the amplifiers A3 and A4 are rail-to-rail Fig.2 Proposed fully differential charge pump circuit structure,the output swing of the charge pump won't be limited by CMFB circuit as [5].Moreover,the noise from the CMFB circuit is common mode to the charge pump,so it has little impact on the phase noise of the frequency synthesizer. 449
Comparing (3) and (4), the effect of channel-length modulation will reduce the matching characteristic of differential charging and discharging currents and increase the level of reference spurs. III. PROPOSED CHARGE PUMP AND CMFB CIRCUIT A. Proposed charge pump circuit To overcome the two drawbacks analyzed above, a fully differential charge pump with replica method to achieve better mismatch suppression is designed in this paper. As shown in Fig. 2. The rail-to-rail opamp A1 and A2 presented in [3] have enough DC gain to ensure Vcp and Vcn to be equal. The structure of the opamp A1 (A2) is shown in Fig.3. When “up” and “dn” are the logic low level, the switches are closed, then the currents in charge pump branches(Iup1, Iup2) and the currents in replica branches(Ip1, Ip2) will satisfy the relationship that:[4] 111 2 2 2 , up p n up p n I III I I =≡ =≡ (5) Assuming , 2 2 diff diff p cp cm n cn cm V V VV V VV V ==+ ==− (6) When the value of Vdiff isn’t equal to zero, the values of Iup1, Idn1, Iup2, Idn2 and the values of Ip1, In1, Ip2, In2 will change due to the effect of channel-length modulation. the expressions are: 1 11 1 222 2 up p n replica replica dn cm up p n replica replica dn cm I III I II I I III I II I = = = +Δ = +Δ = = = −Δ = −Δ (7) Fig.2 Proposed fully differential charge pump circuit Fig.3 The opamp A1(A2) with rail-to-rail input range Where Ireplica is the current when the output voltage is equal to Vcm. ǻIreplica is the current variations in replica branches. For simplicity, define the variations of Idn1 and Idn2 are both ǻI, and the variations of In1 and In2 are both ǻIreplica, when the CMFB circuit is stable, we can induce that Vfb §Vbn. Therefore, 1 12 2 , , n dn n dn replica II II I I ≈ ≈ Δ ≈Δ (8) So the differential charging and discharging currents mismatch will satisfy that 11 2 2 11 2 2 ( - )-( - ) ( - )-( - ) 0 Δ = = ≈ up dn up dn n dn n dn II II II II (9) The current variations of conventional and proposed fully differential charge pumps due to the effect of channel-length modulation are shown in Table I. Because the match between PMOS and NMOS current sources has been converted to the match between two NMOS current sources, the proposed charge pump can make the currents match better, and depress the reference spurs in frequency synthesizer. Table I Comparison of conventional and proposed charge pumps Vcp>Vcn Iup1 Iup2 Idn1 Idn2 (Iup1-Idn1)- (Iup2- Idn2) conventional -ǻI ǻI ǻI -ǻI -4ǻI proposed ǻI -ǻI ǻI -ǻI §0 B. Rail-to-rail CMFB circuit To ensure the large swing of the proposed charge pump unrestricted by CMFB circuit, a rail-to-rail input range CMFB circuit shown in Fig. 4 is presented in this paper. Vp and Vn can be chosen as the input sampling signals of CMFB circuit in order not to change the value of zeros and poles in the loop filter. The buffer amplifiers A3 and A4 copy Vp and Vn to Vp1 and Vn1. The common-mode voltage Vcm could be got through the RC sampling network, then the voltage Vfb, which is the comparative result of Vcm and desired common-mode reference voltage Vref, feeds back to the charge pump to tune the loop. Because the amplifiers A3 and A4 are rail-to-rail structure, the output swing of the charge pump won’t be limited by CMFB circuit as [5]. Moreover, the noise from the CMFB circuit is common mode to the charge pump, so it has little impact on the phase noise of the frequency synthesizer. 449
R A A5 Loop Filter Fig.4 Rail-to-rail input range CMFB circuit Divide AFC VCO IV.EXPERIMENTAL RESULTS Fig.6 Microphotograph of the frequency synthesizer The whole integer-N frequency synthesizer which includes the proposed fully differential charge pump circuit is shown in Fig.5.A switched-capacitors bank LC tank voltage-controlled Locking state oscillator (VCO)with a fast adaptive frequency calibration (AFC)is used in this design,and after the divide by two,a commonly used 4/5 prescaler,operating at the high frequency of VCO,is made as the source-coupled logic(ECL)type.The p1.25V programmable counter is used as a conventional CMOS pulse swallow type All the circuits have been designed and fabricated in SMIC 0.18um CMOS mixed-signal process.Fig.6 shows the microphotograph of the monolithic integer-N frequency Vep 0.25V synthesizer.The area of the charge pump is about 450μm×280μm,and the power dissipation is ImW. The spur and phase noise performance of the frequency synthesizer is tested by Agilent E4445A (3-26.5GHz)PSA Series Spectrum Analyzer.The division value of the divider 52o0r4045Ag can be changed in order to make Vp-Vel largest.The Fig.7 The waveforms of control voltages Vep and Ven in locking state waveforms of the control voltage Vp and V in locking state are shown in Fig.7,the locking time is smaller than 60us,so the CMFB circuit shown in Fig.4 won't increase the response 3 Agilcnt15:38:21May18,2087 time of the PLL loop.The measured reference spur is shown Mkr1 12.50 MHz in Fig.8.When Vep=1.25V and Ven 0.25V,the spur-level Ref a dBm Atten 10 dB -73.09d8 which is-73dBc should be in the worst case. L09 Furthermore,when the output frequency is 1.05GHz,the 10 dB/ phase noise test result is shown in Fig.9.It can be seen that the in-band noise is nearly -90dBc/Hz@1KHz.and the RMS phase error (10Hz~10MHz)is about 1.8 degree. AFC gAv H1 S2 S3 FS AL 11.175GHz e(f): PFD Loop Co FTun Marker△而l Filter 12.500000MHz -73.00dB 12.5MHz Center 1.000 08 GHz pan 30 MHz Res BW 270 kHz VBW 270 kHz Sweep 1.092 ms (8192 pts) P/S rescaler Fig.8 The measured reference spur-level when V1.25V and Vo=0.25V Counter NNT 4047 Fig.5 The block diagram of the frequency synthesizer 450
Fig.4 Rail-to-rail input range CMFB circuit IV. EXPERIMENTAL RESULTS The whole integer-N frequency synthesizer which includes the proposed fully differential charge pump circuit is shown in Fig. 5. A switched-capacitors bank LC tank voltage-controlled oscillator (VCO) with a fast adaptive frequency calibration (AFC)[6] is used in this design, and after the divide by two, a commonly used 4/5 prescaler, operating at the high frequency of VCO, is made as the source-coupled logic (ECL) type. The programmable counter is used as a conventional CMOS pulse swallow type. All the circuits have been designed and fabricated in SMIC 0.18µm CMOS mixed-signal process. Fig.6 shows the microphotograph of the monolithic integer-N frequency synthesizer. The area of the charge pump is about 450µm×280µm, and the power dissipation is 1mW. The spur and phase noise performance of the frequency synthesizer is tested by Agilent E4445A (3~26.5GHz) PSA Series Spectrum Analyzer. The division value of the divider can be changed in order to make |Vcp-Vcn| largest. The waveforms of the control voltage Vcp and Vcn in locking state are shown in Fig.7, the locking time is smaller than 60µs, so the CMFB circuit shown in Fig.4 won’t increase the response time of the PLL loop. The measured reference spur is shown in Fig.8. When Vcp§1.25V and Vcn§0.25V, the spur-level which is -73dBc should be in the worst case. Furthermore, when the output frequency is 1.05GHz, the phase noise test result is shown in Fig.9. It can be seen that the in-band noise is nearly -90dBc/Hz@1KHz, and the RMS phase error (10Hz~10MHz) is about 1.8 degree. Fig.5 The block diagram of the frequency synthesizer Fig.6 Microphotograph of the frequency synthesizer Fig.7 The waveforms of control voltages Vcp and Vcn in locking state Fig.8 The measured reference spur-level when Vcp§1.25V and Vcn§0.25V 450
time is smaller than 60us.So the charge pump is suitable to be Carrier Freg 1.05 GHz Signal Track Off DANL OFf Trig Fr Log Plot used in high-performance frequency synthesizers. REFERENCES -3.69 dBm Atten 0.00 dB [1]Mike Keaveney,Patrick Walsh,Mike Tuthill,Colin Lyden,and Bill Hunt,"A 10us Fast Switching PLL Synthesizer for a GSM/EDGE Base-Station."IEEE International Solid-State Circuits Conference, February 2004. [2] A.Maxim."Low-voltage CMOS charge-pump PLL architecture for low jitter operation,"Proceedings of the 28h European Solid-State Circuit,September 2002. 1H2 requency Offset [3]Minsheng Wang,Terry L.Mayhugh,Sherif H.K.Embabi,and Edgar Marker Trace X Axis Value Sanchez-Sinencio,"Constant-gm Rail-to-Rail CMOS Op-Amp Input Stage with Overlapped Transition Regions,"IEEE J.Solid-State Circuit,vol.34,pp.148-156,February 1999. [4 J.-S.Lee and M.-S.Keel,"Charge pump with perfect current matching characteristics in phase-locked loops,"Electron.Lett.,vol.36,pp.1907- 1908,November 2000. Fig.9 The measured phase noise of the integer-N frequency synthesizer at [5] Zhinian Shu.Ka Lok Lee,and Bosco H.Leung."A 2.4GHz Ring- 1.05GHz Oscillator-Based CMOS Frequency Synthesizer With a Fractiona Divider Dual-PLL Architecture,"IEEE J.Solid-State Circuit,vol.39, Table II gives the measurement results compared with Ppp.452-462,March2004. recently published works,it can be seen that compared to [6 Han-il Lee,Je-Kwang Cho,Kun-Seok Lee,In-Chul Hwang,Tae-Won those with a third-order loop filter,such as [7~8]and [9],this Ahn,Kyung-Suc Nah,and Byeong-Ha Park,"A E-A fractional-N work performs a competitively low spur,and compared to frequency synthesizer using a wide-band integrated VCO and a fast those with a second-order loop filter such as [10]and [11],the AFC technique for GSM/GPRS/WCDMA applications,"IEEE J.Solid- State Circuit,vol.39,pp.1164-1169,July 2004. proposed charge pump can make a great improvement in the [7] Keliu Shu,Edgar Sanchez-Sinencio,Jose Silva-Martinez,and Sherif H spur performance.Also,the frequency synthesizer which K.Embabi."A 2.4-GHz monolithic fractional-N frequency synthesizer adopts the proposed charge pump structure can achieve a good with robust phase-switching prescaler and loop capacitance multiplier,' in-band phase noise performance. IEEE J.Solid-State Circuits,vol.38,pp.866-874,June 2003. [8]C.M.Hung and K.K.O,"A fully integrated 1.5-V 5.5-GHz CMOS V.CONCLUSIONS phase-locked loop,"IEEE J.Solid-State Circuits,vol.37,pp.521-525. April 2002. In this paper,based on the analysis of the drawbacks of the [9 S.Pellerano,S.Laventino,C.Samori,and A.Lacaita,"A 13.5-mW 5. conventional charge pump circuit which is used in integer-N GHz frequency synthesizer with dynamic-logic frequency divider," frequency synthesizers,a fully differential charge pump with IEEE J.Solid-State Circuits,vol.39,pp.378-383,February 2004. better suppression of output currents mismatch is proposed. [10]F.Herzel,G.Fischer,and P.Weger,"An integrated CMOS RF The replica technique is adopted to eliminate the effect of synthesizer for 802.11a wireless LAN,"IEEE J.Solid-State Circuits. channel-length modulation,and a rail-to-rail common-mode vol.38,pp.1767-1770,0 ctober2003. feedback circuit is introduced in order to ensure the large [11]Chun-Yi Kuo,Jung-Yu Chang.and Shen-Iuan Liu,"A spur-reduction swing of the charge pump unrestricted.The experimental technique for a 5-GHz frequency synthesizer,"IEEE Transactions on results show that the worst spur-level is about-73dBc,the in- Circuits and Systems-I:Regular Papers,vol.53,pp.526-533,March 2006. band phase noise is nearly-90dBc/Hz@1KHz,and the locking Table II Comparison of measured reference spurs and phase noise Reference Phase noise Process Bandwidth Spur-level Loop filter Supply Clock (dBc/Hz) voltage [] 0.35μm 40(50)MHz 250KHz -57dBc 3-order -86@10KHz 2V [8] 0.25μm 43MHz 80KHz <-69dBc 3-order -75@40KHz 1.5V [9] 0.25um 10MHz 25KHz -70dBc 3-order -63@10KHz 2.5V [10] 0.25um 4MHz 90KHz -45dBc 2-order -77@10KHz 2.5V [11] 0.18μm 20MHz 60KHZ -74dBc 2-order -79@10KHz 1.8V This work 0.18um 12.5MHz 60KHz -73dBc 2-order -90@1KHz 1.8V 451
Fig.9 The measured phase noise of the integer-N frequency synthesizer at 1.05GHz Table II gives the measurement results compared with recently published works, it can be seen that compared to those with a third-order loop filter, such as [7~8] and [9], this work performs a competitively low spur, and compared to those with a second-order loop filter such as [10] and [11], the proposed charge pump can make a great improvement in the spur performance. Also, the frequency synthesizer which adopts the proposed charge pump structure can achieve a good in-band phase noise performance. V. CONCLUSIONS In this paper, based on the analysis of the drawbacks of the conventional charge pump circuit which is used in integer-N frequency synthesizers, a fully differential charge pump with better suppression of output currents mismatch is proposed. The replica technique is adopted to eliminate the effect of channel-length modulation, and a rail-to-rail common-mode feedback circuit is introduced in order to ensure the large swing of the charge pump unrestricted. The experimental results show that the worst spur-level is about -73dBc, the inband phase noise is nearly -90dBc/Hz@1KHz, and the locking time is smaller than 60µs. So the charge pump is suitable to be used in high-performance frequency synthesizers. REFERENCES [1] Mike Keaveney, Patrick Walsh, Mike Tuthill, Colin Lyden, and Bill Hunt, “A 10µs Fast Switching PLL Synthesizer for a GSM/EDGE Base-Station,” IEEE International Solid-State Circuits Conference, February 2004. [2] A.Maxim. “Low–voltage CMOS charge–pump PLL architecture for low jitter operation,” Proceedings of the 28th European Solid-State Circuit, September 2002. [3] Minsheng Wang, Terry L. Mayhugh, Sherif H. K. Embabi, and Edgar Sanchez-Sinencio, “Constant-gm Rail-to-Rail CMOS Op-Amp Input Stage with Overlapped Transition Regions,” IEEE J. Solid-State Circuit, vol. 34, pp.148-156, February 1999. [4] J.-S. Lee and M.-S. Keel, “Charge pump with perfect current matching characteristics in phase-locked loops,” Electron. Lett., vol. 36, pp.1907- 1908, November 2000. [5] Zhinian Shu, Ka Lok Lee, and Bosco H. Leung, “A 2.4GHz RingOscillator-Based CMOS Frequency Synthesizer With a Fractional Divider Dual-PLL Architecture,” IEEE J. Solid-State Circuit, vol. 39, pp.452- 462, March 2004. [6] Han-il Lee, Je-Kwang Cho, Kun-Seok Lee, In-Chul Hwang, Tae-Won Ahn, Kyung-Suc Nah, and Byeong-Ha Park, “A Ȉ-ǻ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications,” IEEE J. SolidState Circuit, vol. 39, pp.1164-1169, July 2004. [7] Keliu Shu, Edgar Sanchez-Sinencio, Jose Silva-Martinez, and Sherif H. K. Embabi, “A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier,” IEEE J. Solid-State Circuits, vol. 38, pp.866-874, June 2003. [8] C. M. Hung and K. K. O, “A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop,” IEEE J. Solid-State Circuits, vol. 37, pp. 521-525, April 2002. [9] S. Pellerano, S. Laventino, C. Samori, and A. Lacaita, “A 13.5-mW 5- GHz frequency synthesizer with dynamic-logic frequency divider,” IEEE J. Solid-State Circuits, vol. 39, pp. 378-383, February 2004. [10] F. Herzel, G. Fischer, and P. Weger, “An integrated CMOS RF synthesizer for 802.11a wireless LAN,” IEEE J. Solid-State Circuits, vol. 38, pp. 1767-1770, October 2003. [11] Chun-Yi Kuo, Jung-Yu Chang, and Shen-Iuan Liu, “A spur-reduction technique for a 5-GHz frequency synthesizer,” IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 53, pp. 526-533, March 2006. Table II Comparison of measured reference spurs and phase noise Process Reference Clock Bandwidth Spur-level Loop filter Phase noise (dBc/Hz) Supply voltage [7] 0.35µm 40(50)MHz 250KHz -57dBc 3-order -86@10KHz 2V [8] 0.25µm 43MHz 80KHz <-69dBc 3-order -75@40KHz 1.5V [9] 0.25µm 10MHz 25KHz -70dBc 3-order -63@10KHz 2.5V [10] 0.25µm 4MHz 90KHz -45dBc 2-order -77@10KHz 2.5V [11] 0.18µm 20MHz 60KHz -74dBc 2-order -79@10KHz 1.8V This work 0.18µm 12.5MHz 60KHz -73dBc 2-order -90@1KHz 1.8V 451