9-5 IEEE Asian Solid-State Circuits Conference November 3-5,2008/Fukuoka,Japan A 12th Order Active-RC Filter with Automatic Frequency Tuning for dVB Tuner applications Liang Zou',Kefeng Han',Youchun Liao',Hao Min'and Zhangwen Tang'* ASIC System State Key Laboratory,Fudan University,Shanghai 201203,China Ratio Microelectronics Technology Co.,Ltd,Shanghai 200433,China Abstract-A 12th order active-RC filter for DVB Tuner RF front-end applications with automatic frequency tuning (AFT)is VGLNA UpMixer 一OnMixer presented in this paper.The filter is implemented in D Butterworth biquad structure.The AFT circuit is introduced to compensate the frequency variation by a 7-bits switched- Pre VGA capacitor array.The measurement results indicate that the precision of tuning circuit can be controlled less than +2.3%,the in-band group delay variation is 70ns,and the in-band IM3 achieves -60dB with-27dbm input power.This proposed filter 0 circuit,fabricated in a SMIC 0.18um CMOS process,consumes First LO 6mA current with 1.8V power supply. Quadrature)」 Figure 1 Architecture of RF Tuner Receiver I.INTRODUCTION The main purpose of the analog channel filter in RF Section II illustrates the design of filter core circuit. receiver is to select the desired signal,and provides anti- Section III shows the implement of tuning circuit in detail,and aliasing for the following ADC.Channel selection can be proposed critical design insights to minimize the non-ideal implemented in either analog or digital domain.The factors which will affect the precision of tuning.Section IV implement in analog domain increases the requirement of gives some measurement results,such as frequency response, analog filter's dynamic range,but lower the ADC's resolution. group delay and in-band IM3 The implement in digital domain can conquer the variation of components,the phase and gain error in analog filter,but FILTER CORE CIRCUIT DESIGN requires increased resolution and dynamic range of ADC.The power of ADC will swiftly increase as the increased resolution In our tuner receiver,system design specifies the cut-off frequency 11MHz,and requires the filter to achieve 60dB requirement,which can be shown as (1). ACR@22MHz.A 12th order Butterworth filter is chosen here Pic=Em2Is(Nyquist-Rate ADC) 1) for the flat pass-band and sharp transition-band frequency response.The Two-Thomas biquad is adopted to implement where Eeonv is the required power for one bit,2N is the the Butterworth function as shown in Fig.2. number of bits,and fs is the sample rate [1]. In RF tuner system,wide bandwidth and high linearity R2 requirements make the ADC difficult to implement.To lower the power of ADC and obtain a good adjacent channel rejection (ACR)before ADC,here the high orders analog filter is adopted to achieve good attenuation,and the active- Vinp o- Voutn RC architecture is selected to achieve high linearity.The cut- off frequency of integrated active-RC filter is determined by Voutp on-chip resistor and capacitor which may vary much with process and temperature.So automatic frequency tuning (AFT) circuit should be engaged to calibrate the frequency variation. The total tuner receiver architecture is shown in Fig.1. R2 M Figure 2 Biquad Integrator Corresponding author.Email:zwtang@fudan.edu.cn 978-1-4244-2605-8/08/$25.00©20081EEE 281
A 12th Order Active-RC Filter with Automatic Frequency Tuning for DVB Tuner Applications Liang Zou1 , Kefeng Han1 , Youchun Liao2 , Hao Min1 and Zhangwen Tang1 * 1 ASIC & System State Key Laboratory, Fudan University, Shanghai 201203, China 2 Ratio Microelectronics Technology Co., Ltd, Shanghai 200433, China Abstract²$ th RUGHU DFWLYH5& ILOWHU IRU '9% 7XQHU DSSOLFDWLRQV ZLWK DXWRPDWLF IUHTXHQF\ WXQLQJ $)7 LV SUHVHQWHG LQ WKLV SDSHU 7KH ILOWHU LV LPSOHPHQWHG LQ %XWWHUZRUWKELTXDGVWUXFWXUH7KH$)7FLUFXLWLVLQWURGXFHGWR FRPSHQVDWH WKH IUHTXHQF\ YDULDWLRQ E\ D ELWV VZLWFKHG FDSDFLWRU DUUD\ 7KH PHDVXUHPHQW UHVXOWV LQGLFDWH WKDW WKH SUHFLVLRQRIWXQLQJFLUFXLWFDQEHFRQWUROOHGOHVVWKDQWKH LQEDQG JURXS GHOD\ YDULDWLRQ LV QV DQG WKH LQEDQG ,0 DFKLHYHV G% ZLWK GEP LQSXW SRZHU 7KLV SURSRVHG ILOWHU FLUFXLWIDEULFDWHGLQD60,&ȝP&026SURFHVVFRQVXPHV P$FXUUHQWZLWK9SRZHUVXSSO\ I. INTRODUCTION The main purpose of the analog channel filter in RF receiver is to select the desired signal, and provides antialiasing for the following ADC. Channel selection can be implemented in either analog or digital domain. The implement in analog domain increases the requirement of DQDORJILOWHU¶VG\QDPLFUDQJHEXWORZHUWKH$'&¶VUHVROXWLRQ The implement in digital domain can conquer the variation of components, the phase and gain error in analog filter, but requires increased resolution and dynamic range of ADC. The power of ADC will swiftly increase as the increased resolution requirement, which can be shown as (1), < < 2N PE f ADC conv S (Nyquist-Rate ADC) (1) where Econv is the required power for one bit, 2N is the number of bits, and fS is the sample rate [1]. In RF tuner system, wide bandwidth and high linearity requirements make the ADC difficult to implement. To lower the power of ADC and obtain a good adjacent channel rejection (ACR) before ADC, here the high orders analog filter is adopted to achieve good attenuation, and the activeRC architecture is selected to achieve high linearity. The cutoff frequency of integrated active-RC filter is determined by on-chip resistor and capacitor which may vary much with process and temperature. So automatic frequency tuning (AFT) circuit should be engaged to calibrate the frequency variation. The total tuner receiver architecture is shown in Fig. 1. Figure 1 Architecture of RF Tuner Receiver Section II illustrates the design of filter core circuit. Section III shows the implement of tuning circuit in detail, and proposed critical design insights to minimize the non-ideal factors which will affect the precision of tuning. Section IV gives some measurement results, such as frequency response, group delay and in-band IM3. II. FILTER CORE CIRCUIT DESIGN In our tuner receiver, system design specifies the cut-off frequency 11MHz, and requires the filter to achieve 60dB ACR@ 22MHz. A 12th order Butterworth filter is chosen here for the flat pass-band and sharp transition-band frequency response. The Two-Thomas biquad is adopted to implement the Butterworth function as shown in Fig. 2. Figure 2 Biquad Integrator *Corresponding author. Email: zwtang@fudan.edu.cn 978-1-4244-2605-8/08/$25.00 ©2008 IEEE 281 IEEE Asian Solid-State Circuits Conference November 3-5, 2008 / Fukuoka, Japan 9-5
There are some equations in Two-Thomas biquad,which can compensation to achieve 75 degree phase margin.Common- be shown as follows. mode feedback circuit is designed to stable the common-mode =R.R.CC: ,Q= C operation point of output,a pole which located at p=gm6/Cnl.to (2) is additionally introduced to the common-mode loop as shown in Fig.4.The gain of common-mode circuit can not be set too where Ao is the DC gain of integrator,o is the cut-off large to affect the stability of common-mode loop.The GBW frequency,Q is the quality of integrator. of amplifier should be wide enough to conquer gain peaking around cut-off frequency.Requirement of GBW can be shown Assume R2=R4.C=C2,Equ.(2)can be rewritten as as[4: 1 = (3) Ac(jo R R GBW≥ -1 [1+Ac(jo:)]o2 (4) From(3).Q and Ao are determined by the ratio of resistors, where the AcjoL)is the open loop gain of amplifier,oL is the and both Q and co can be tuned independently [2]. cut-off frequency of filter,8 is the error between ideal This 12 order Butterworth filter consists of six cascaded transform function and non-ideal transform function.Another, biquads,the high Q biquad is placed in the end of filter chain the Slew Rate,equivalent input noise and THD should be to maximize linearity performance.Here,the capacitor is considered in amplifier design. designed to be a programmable switched-capacitor array with IIL.TUNING CIRCUIT DESIGN binary-weighted to obtain adjustable RC constant,which is controlled by 7-bits digital signals,as shown in Fig.3. A.Tuning Circuit .n=16. .几8 Accurate cut-off frequency is necessary in filter to satisfy b5 both the channel selection and adjacent channel rejection.To meet +3%frequency variation of system requirement,a Master-Slave tuning circuit is introduced here to adjust the absolute precision by relative precision.Every tuning circuit needs an absolute reference.Commonly,there are only two absolute references which are Bandgap voltage and crystal frequency.Here the frequency of crystal oscillator is chosen to keep the same dimension with the RC constant.The mean to realize the RC tuning is carried out by adjusting the switched- capacitor array [5].The overall schematic of proposed tuning circuit is illustrated in Fig.5. 32 n=2 VDD →MOS CAP Error Amplifier M3 Figure 3 7-bits Digital Controlled Switched-capacitor Array ￥ comparator Sources of MOS-Switches are connected with the input Out_comparator nodes of the OTAs to reduce the nonlinearity of switches,but the parasitic capacitor at input nodes increased,which cause the phase lag [3].Layout of switched-capacitor array should cap be considered carefully to assure the monotony GND VDD M7 M9 M10 M T Vcm switch control Voutp Ibias 西12M13 Figure 5 Tuning Circuit Rc C n First,a voltage reference is obtained from Bandgap output after voltage dividing,separately connects with the inputs of error amplifier and comparator.A current reference can be D= 9m16 got as I=VreRrer through the feedback of error amplifier,and then a mirror current can be generated to charge the switched- Figure 4 Fully Differential Two-stage Amplifier capacitor array to get a voltage Veap.Veap and Vrer can be compared by a comparator,the comparison result enter into Amplifier in Tow-Thomas biquad is shown in Fig.4.It's a the AFT algorithm to form a feedback loop.By controlling fully differential two-stage amplifier,two-stage structure is the digital input signal of switched-capacitor,Veap will equal used to improve the differential gain.Rcand Cc acts as miller to the Vrer after tuning.The process can be shown as follows, 282
There are some equations in Two-Thomas biquad, which can be shown as follows, 2 0 2412 1 Z R RCC , 1 1 2 4 2 R C Q R R C , 2 0 3 R A R (2) where Ao is the DC gain of integrator, Ȧo is the cut-off frequency, Q is the quality of integrator. Assume R2=R4, C1=C2, Equ. (2) can be rewritten as, 2 0 2 1 1 R C Z , 1 2 R Q R , 2 0 3 R A R (3) From (3), Q and A0 are determined by the ratio of resistors, and both Q and Ȧ can be tuned independently [2]. This 12th order Butterworth filter consists of six cascaded biquads, the high Q biquad is placed in the end of filter chain to maximize linearity performance. Here, the capacitor is designed to be a programmable switched-capacitor array with binary-weighted to obtain adjustable RC constant, which is controlled by 7-bits digital signals, as shown in Fig. 3. &IL[ & & & & & & & & & & & & & & & & & & Figure 3 7-bits Digital Controlled Switched-capacitor Array Sources of MOS-Switches are connected with the input nodes of the OTAs to reduce the nonlinearity of switches, but the parasitic capacitor at input nodes increased, which cause the phase lag [3]. Layout of switched-capacitor array should be considered carefully to assure the monotony. P Q WRO J S & Figure 4 Fully Differential Two-stage Amplifier $PSOLILHULQ7RZ7KRPDVELTXDGLVVKRZQLQ)LJ,W¶VD fully differential two-stage amplifier, two-stage structure is used to improve the differential gain. RC and CC acts as miller compensation to achieve 75 degree phase margin. Commonmode feedback circuit is designed to stable the common-mode operation point of output, a pole which located at p=gm16/Cn1,tol is additionally introduced to the common-mode loop as shown in Fig. 4. The gain of common-mode circuit can not be set too large to affect the stability of common-mode loop. The GBW of amplifier should be wide enough to conquer gain peaking around cut-off frequency. Requirement of GBW can be shown as [4]: ( ) 1 [1 ( )] Z Z Z G t C L C LL A j GBW A j (4) where the AC(jȦL) is the open loop gain of amplifier, ȦL is the cut-off frequency of filter, į is the error between ideal transform function and non-ideal transform function. Another, the Slew Rate, equivalent input noise and THD should be considered in amplifier design. III. TUNING CIRCUIT DESIGN A. Tuning Circuit Accurate cut-off frequency is necessary in filter to satisfy both the channel selection and adjacent channel rejection. To meet ±3% frequency variation of system requirement, a Master-Slave tuning circuit is introduced here to adjust the absolute precision by relative precision. Every tuning circuit needs an absolute reference. Commonly, there are only two absolute references which are Bandgap voltage and crystal frequency. Here the frequency of crystal oscillator is chosen to keep the same dimension with the RC constant. The mean to realize the RC tuning is carried out by adjusting the switchedcapacitor array [5]. The overall schematic of proposed tuning circuit is illustrated in Fig. 5. , , 9FDS 5UHI 9UHI & Figure 5 Tuning Circuit First, a voltage reference is obtained from Bandgap output after voltage dividing, separately connects with the inputs of error amplifier and comparator. A current reference can be got as I1=Vref/Rref through the feedback of error amplifier, and then a mirror current can be generated to charge the switchedcapacitor array to get a voltage Vcap. Vcap and Vref can be compared by a comparator, the comparison result enter into the AFT algorithm to form a feedback loop. By controlling the digital input signal of switched-capacitor, Vcap will equal to the Vref after tuning. The process can be shown as follows, 282
_A2_I2△1_I△1_ chip,resistor mismatch between master and slave circuit can (5) C RC be controlled within 0.5%with suitable size and excellent layout,and the capacitor mismatch can be controlled under △ 0.2%.Besides RC mismatch,current mismatch is another (6 RC important contribution,which can be designed to below 0.5%. All the other contributions should be controlled within 1%. After tuning,Veap is equal to Vre namely, thus the total tuning error can be controlled under 3%.To minimize these tuning errors,some useful design (7) considerations are proposed as follows. Amplifier offset,including random offset and systematic Substituting(7)into (6), offset,affects the comparison result.The random offset can △t=ReC (8) be minimized by engaging big size and small overdrive where At is the multiples of crystal oscillator's period,Rer voltage of input transistors [6].In Fig.5,if comparator is is the on-chip poly resistor,which keeps the relative precision implemented by the same with the error amplifier, with the resistors in filter core circuit,and the capacitor C in symmetrically layout,the systematic offset voltage will be tuning circuit is equal to the capacitor in filter core.So the cancelled.Assuming AV is the offset voltage of amplifier constant time RreC is determined by At after tuning,and the between positive input and negative input in Fig.5,the RrerC keeps the relative precision with the constant time of following equation can be got by (6), filter core circuit.In another word,the cut-off frequency is △ tuned to keeps the relative precision with the frequency of (13) crystal oscillator.The tuning control logic is implemented by binary search algorithm to save calibration time.Here the crystal frequency is chosen to be 25MHz,and the detailed After tuning,Vcap=Vrer+AV=Vrep timing plan in one comparison step is illustrated in Fig.6.The whole calibration needs seven comparison steps,consumes →△1=RnC (14) only 8.96us. From(14),the systematic offset voltage can be cancelled cK可T2345LT10A314可T2可 The main consideration of current bias design is to 82 charge charoe minimize the difference between current I2 and I during the s1 whole charging process.Here,the cascode transistors are s3 rese comparator works applied to improve the output resistance for a good DC match Also,the lengths of current mirrors are chosen to be 6um and Vref=600m Vcap the overdrive voltages of MI and M2 are designed to be large Out_comparatorcharge injection as 600mV to improve the match.While there is still trade-off when sizing Ml and M2,because large transistors may Figure 6 Timing Plan deteriorate clock feed-through effects.and then worsen B.Tuning Error dynamic current mismatch.MOS CAP in Fig.5 is engaged to Error factors which affect the precision of tuning can be reduce clock feed-through.When switched-capacitor array is charging,Veap increases as the time,and current I2 will vary summarized as follows:quantization error of switched- nonlinearity.So,the value of Vrer can't be set too high.Also capacitor array,resistor and capacitor mismatch between the value of charging current should be designed carefully to master and slave circuit,current mismatch,offset voltage of get a reasonable charging time. amplifier,charge injection of MOS switches,and clock feed- In tuning circuit as shown in Fig.5,three MOS switches through,etc. are introduced.The sizes of all the switches are chosen to be The programmable switched-capacitor array in Fig.3 is as small as possible to decrease charge injection which is considered as a capacitor DAC whose input is digital and shown in Fig.6.When SI turns on,Veap is pulled down to output is capacitance. GND.the lager W/L of SI will help to lower the turn-on 1 Cmas=C+(2 26)Co (9) resistor but increase charge injection,it's also a trade-off. When S2 turns on,the bias current I2 starts to charge the (10) switched-capacitor array.There usually needs an initial time for current bias settling,which will cause dynamic current Coomr =CmsCmin (11)mismatch.In our timing design,the initial settling current is To cover the +20%variation of resistors and capacitors avoided to charge the capacitor array as shown in Fig.6. over different process corners,here we choose IV.EXPERIMENTAL RESULTS CC=2.25/1,the quantization error of CAP-DAC is, /2-1 The proposed filter circuit was implemented in SMIC E= (12)0.18um technology.The chip micrograph is shown in Fig.7, and the active area of filter including both I and Q channel is where n is the number of digital control bits 1.4mmx0.9mm.As shown in Fig.8,flat pass-band response is To satisfy 3%tuning precision,here n=7 is chosen to obtained with less than 0.5dB in-band ripple,and 60dB ACR achieve 0.65%quantization error.Commonly,in the same is achieved at 22MHz. 283
' 2 1 ' ' ' ref cap ref Q It It V V t C C C RC (5) cap ref ref V t V RC ' (6) After tuning, Vcap is equal to Vref, namely, 1 cap ref V V (7) Substituting (7) into (6), ' ref t RC (8) where ǻWLVWKHPXOWLSOHVRIFU\VWDORVFLOODWRU¶VSHULRG5ref is the on-chip poly resistor, which keeps the relative precision ZLWKWKH UHVLVWRUVLQ ILOWHUFRUHFLUFXLWDQGWKHFDSDFLWRU&LQ tuning circuit is equal to the capacitor in filter core. So the FRQVWDQWWLPH5ref&LV GHWHUPLQHG E\ǻW DIWHUWXQLQJDQGWKH 5ref& NHHSV WKH UHODWLYH SUHFLVLRQ ZLWK WKH FRQVWDQW WLPH RI ILOWHU FRUH FLUFXLW ,Q DQRWKHU ZRUG WKH FXWRII IUHTXHQF\ LV WXQHG WR NHHSV WKH UHODWLYH SUHFLVLRQ ZLWK WKH IUHTXHQF\ RI FU\VWDORVFLOODWRU7KHWXQLQJFRQWUROORJLFLVLPSOHPHQWHGE\ binary search algorithm to save calibration time. Here the FU\VWDO IUHTXHQF\ LV FKRVHQ WR EH 0+] DQG WKH GHWDLOHG WLPLQJSODQLQRQHFRPSDULVRQVWHSLVLOOXVWUDWHGLQ)LJ7KH ZKROH FDOLEUDWLRQ QHHGV VHYHQ FRPSDULVRQ VWHSV FRQVXPHV only 8.96ȝs. )LJXUH7LPLQJ3ODQ B. Tuning Error Error factors which affect the precision of tuning can be VXPPDUL]HG DV IROORZV TXDQWL]DWLRQ HUURU RI VZLWFKHG FDSDFLWRU DUUD\ UHVLVWRU DQG FDSDFLWRU PLVPDWFK EHWZHHQ PDVWHU DQG VODYHFLUFXLWFXUUHQWPLVPDWFK RIIVHW YROWDJH RI DPSOLILHUFKDUJHLQMHFWLRQRI026VZLWFKHVDQGFORFNIHHG through, etc. 7KH SURJUDPPDEOH VZLWFKHGFDSDFLWRU DUUD\ LQ )LJ LV FRQVLGHUHG DV D FDSDFLWRU '$& ZKRVH LQSXW LV GLJLWDO DQG output is capacitance. max 0 6 1 (2 ) 2 CC C fix (9) C C min fix (10) max min @ ,Q )LJ LI FRPSDUDWRU LV LPSOHPHQWHG E\ WKH VDPH ZLWK WKH HUURU DPSOLILHU symmetrically layout, the systematic offset voltage will be FDQFHOOHG $VVXPLQJ ǻV is the offset voltage of amplifier EHWZHHQ SRVLWLYH LQSXW DQG QHJDWLYH LQSXW LQ )LJ WKH following equation can be got by (6), ' ' cap ref ref V t V R C ' After tuning, V¶ cap= Vref + ǻV=V¶ ref, ref ' t RC (14) )URP WKHV\VWHPDWLFRIIVHWYROWDJHFDQEHFDQFHOOHG 7KH PDLQ FRQVLGHUDWLRQ RI FXUUHQW ELDV GHVLJQ LV WR PLQLPL]HWKHGLIIHUHQFHEHWZHHQFXUUHQW ,2DQG ,1GXULQJWKH ZKROH FKDUJLQJ SURFHVV +HUH WKH FDVFRGH WUDQVLVWRUV DUH DSSOLHGWRLPSURYHWKHRXWSXWUHVLVWDQFHIRUDJRRG'&PDWFK Also, the lengths of current mirrors are chosen to be 6ȝPDQG WKHRYHUGULYHYROWDJHVRI0DQG0DUHGHVLJQHGWREHODUJH DVP9WRLPSURYHWKHPDWFK:KLOHWKHUHLVVWLOOWUDGHRII ZKHQ VL]LQJ 0 DQG 0 EHFDXVH ODUJH WUDQVLVWRUV PD\ GHWHULRUDWH FORFN IHHGWKURXJK HIIHFWV DQG WKHQ ZRUVHQ G\QDPLFFXUUHQWPLVPDWFK026&$3LQ)LJLVHQJDJHGWR UHGXFHFORFNIHHGWKURXJK:KHQVZLWFKHGFDSDFLWRUDUUD\LV charging, VcapLQFUHDVHVDVWKHWLPHDQGFXUUHQW ,2 will vary nonlinearity. So, the value of VrefFDQ¶WEHVHWWRRKLJK$OVR WKHYDOXHRIFKDUJLQJFXUUHQWVKRXOGEHGHVLJQHGFDUHIXOO\WR get a reasonable charging time. ,QWXQLQJFLUFXLWDV VKRZQLQ )LJ WKUHH026 VZLWFKHV DUHLQWURGXFHG7KHVL]HVRIDOOWKHVZLWFKHVDUHFKRVHQWREH DV VPDOO DV SRVVLEOH WR GHFUHDVH FKDUJH LQMHFWLRQ ZKLFK LV VKRZQ LQ )LJ :KHQ 6 WXUQV RQ 9cap LV SXOOHG GRZQ WR *1' WKH ODJHU :/ RI 6 ZLOO KHOS WR ORZHU WKH WXUQRQ UHVLVWRU EXW LQFUHDVH FKDUJH LQMHFWLRQ LW¶V DOVR D WUDGHRII When S2 turns on, the bias current I2 starts to charge the VZLWFKHGFDSDFLWRU DUUD\ 7KHUH XVXDOO\ QHHGV DQ LQLWLDO WLPH IRU FXUUHQW ELDV VHWWOLQJ ZKLFK ZLOO FDXVH G\QDPLF FXUUHQW PLVPDWFK ,Q RXUWLPLQJ GHVLJQWKHLQLWLDO VHWWOLQJ FXUUHQWLV DYRLGHGWRFKDUJHWKHFDSDFLWRUDUUD\DVVKRZQLQ)LJ IV. E;3(5,0(17$/5(68/76 7KH SURSRVHG ILOWHU FLUFXLW ZDV LPSOHPHQWHG LQ 60,& 0.18ȝPWHFKQRORJ\7KHFKLSPLFURJUDSKLV VKRZQLQ)LJ DQGWKHDFWLYHDUHDRIILOWHULQFOXGLQJERWK,DQG4FKDQQHOLV PPî PP$VVKRZQLQ)LJIODWSDVVEDQGUHVSRQVHLV REWDLQHGZLWKOHVVWKDQG%LQEDQGULSSOHDQGG%$&5 LVDFKLHYHGDW0+] 283
Lots of measurement results show the cut-off frequency can be calibrated to less than 2.3%.As shown in Fig.9,70ns in-band group delay is achieved.Two-tone test is given in Fig 10,which indicates that the in-band IM3 achieves -60.5dB with-27dBm input power.The performance of proposed filter is summarized at Table 1. 12 Order Active Table 1 Summary of the Measurement Results RC Technology CMOS 0.18 um Filter Supply Voltage 1.8V ■■■■■■ Power Consumption 6mA×1.8V=10.8mW Figure 7 Chip Micrograph Area 1.4mm×0.9mm (for both I&O) -3dB Frequency 11 MHz Pass-band Ripple 60dB In-band Group Delay Variation 70 ns Befo宿 -60.5dB Tuning In-band IM3@input power-27dBm Tuning Error ±2.3% Tuning Time 8.96us V. CONCLUSION A 12th order active-RC filter with automatic frequency tuning is proposed in this paper.The tuning circuit is analyzed Frequency(Hz) in detail,and the measurement result indicates the tuning error Figure 8 Frequency Response can be controlled under+2.3%.This LPF is applied to a TV tuner receiver to implement channel selection and ACR.The 0.0 result of two-tone test is given,which shows -60.5dB in-band 250.0 IM3 with-27dBm input power.In-band group delay variation is 70ns,which is acceptable in tuner system specification.The 0.0 proposed filter circuit,fabricates in a SMIC 0.18um CMOS 150.0 process,consumes only 6mA current with 1.8V power supply. 10.0 0.00 ACKNOWLEDGMENTS 0.600 The authors would like to thank Lee Yang at SMIC, Shanghai,China for providing chip fabrication.The work -50,c0 was partly supported by Chinese National Programs for High -100.0 Technology Research and Development with Grant No. 2007AA01Z282. 10,0 200.0 REFERENCES Figure9 Measured Group Delay [1]Jarkko Jussila,Kari Halonen,"Minimization of power dissipation of analog channel-select filter and Nyquist-rate AD converter in UTRA -184 Atten 18 dB FDD,"IEEE International Symposium on Circuits and Systems,vol.4, pp.940-943,May2004. dB/ [2]Rolf Schaumann,Mac E.Van Valkenburg."Design of Analog Filters". Oxford University Press,2001 ] Jarkko Jussila,"Analog Baseband Circuits for WCDMA Direct- Conversion Receivers",P.H.D Dissertation,Helsinki University of Technology,2003. [4]DingKun Du,Yongming Li,Zhihua Wang,"An Active-RC Complex Filter with Mixed Signal Tuning System for Low-IF Receiver,"IEEE Asia Pacific Conference on Circuits and Systems,pp.1031-1034, December 2006. [5]Seyeob Kim,Bonkee Kim,Min-Su Jeong.Jung-Hwan Lee,Youngho FET Cho,Tae Wook Kim,Bo-Eun Kim,"A 43dB ACR low-pass filter with automatic tuning for low-IF conversion DAB T-DMB tuner IC,"/EEE Center 3.808 88 MHz Span 50 kHa European Solid-State Circuits Conference,pp.319-322,September Res BW 108 H2 VBH 108 Hz Smeep 841 ms (601 pts) 2005 Figure 10 Measured IM3 [6]Willy M.C.Sansen,"Analog Design Essentials",Springer,2006. 284
Figure 7 Chip Micrograph Figure 8 Frequency Response Figure 9 Measured Group Delay Figure 10 Measured IM3 Lots of measurement results show the cut-off frequency can be calibrated to less than 2.3%. As shown in Fig. 9, 70ns in-band group delay is achieved. Two-tone test is given in Fig. 10, which indicates that the in-band IM3 achieves -60.5dB with -27dBm input power. The performance of proposed filter is summarized at Table 1. Table 1 Summary of the Measurement Results Technology CMOS 0.18 ȝm Supply Voltage 1.8 V Power Consumption 6mA×1.8V=10.8mW Area 1.4 mm×0.9 mm (for both I&Q) -3dB Frequency 11 MHz Pass-band Ripple 60 dB In-band Group Delay Variation 70 ns In-band IM3@input power -27dBm -60.5 dB Tuning Error ± 2.3% Tuning Time 8.96 ȝs V. CONCLUSION A 12th order active-RC filter with automatic frequency tuning is proposed in this paper. The tuning circuit is analyzed in detail, and the measurement result indicates the tuning error can be controlled under ± 2.3%. This LPF is applied to a TV tuner receiver to implement channel selection and ACR. The result of two-tone test is given, which shows -60.5dB in-band IM3 with -27dBm input power. In-band group delay variation is 70ns, which is acceptable in tuner system specification. The proposed filter circuit, fabricates in a SMIC 0.18ȝm CMOS process, consumes only 6mA current with 1.8V power supply. ACKNOWLEDGMENTS The authors would like to thank Lee Yang at SMIC, Shanghai, China for providing chip fabrication. The work was partly supported by Chinese National Programs for High Technology Research and Development with Grant No. 2007AA01Z282. REFERENCES [1] -DUNNR -XVVLOD .DUL +DORQHQ ³0LQLPL]DWLRQ RI SRZHU GLVVLSDWLRQ RI analog channel-select filter and Nyquist-rate AD converter in UTRA )''´IEEE International Symposium on Circuits and Systems, vol. 4, pp. 940-943, May 2004. [2] Rolf Schaumann, Mac E. Van Valkenburg,³'HVLJQRI$QDORJ)LOWHUV´ Oxford University Press, 2001. [3] -DUNNR -XVVLOD ³$QDORJ %DVHEDQG &LUFXLWV IRU :&'0$ 'LUHFW &RQYHUVLRQ 5HFHLYHUV´ 3+' 'LVVHUWDWLRQ Helsinki University of Technology, 2003. [4] 'LQJ.XQ 'X <RQJPLQJ /L =KLKXD:DQJ ³$Q $FWLYH5& &RPSOH[ )LOWHUZLWK0L[HG 6LJQDO7XQLQJ 6\VWHP IRU/RZ,)5HFHLYHU´IEEE Asia Pacific Conference on Circuits and Systems, pp. 1031-1034, December 2006. [5] Seyeob Kim, Bonkee Kim, Min-Su Jeong, Jung-Hwan Lee,Youngho &KR7DH:RRN.LP%R(XQ.LP³$G%$&5ORZSDVVILOWHUZLWK DXWRPDWLFWXQLQJIRUORZ,)FRQYHUVLRQ'$%7'0%WXQHU,&´IEEE European Solid-State Circuits Conference, pp. 319-322, September 2005 [6] :LOO\0&6DQVHQ³$QDORJ'HVLJQ(VVHQWLDOV´Springer, 2006. 284