RMO4B-4 A Fully Integrated 1.175-to-2GHz Frequency Synthesizer with Constant Bandwidth for DVB-T Applications Lei Lu,Lu Yuan,Hao Min and Zhangwen Tang* ASIC System State Key Laboratory,Fudan University,Shanghai,China,201203 Abstract-A fully integrated 1.175 to 2GHz differentially AFC tuned frequency synthesizer aimed for DVB-T tuners is implemented in 0.18-um CMOS.Techniques are proposed to CP make the loop bandwidth constant across the whole output frequency range to maintain phase noise optimization and loop stability.It exhibits in-band phase noise of-97.6dBc/Hz 51 1 at 10kHz offset and integrated phase error of 0.63 from 2 PED 100Hz to 10MHz.The chip draws 10mA from a 1.8V supply while occupying 2.6mm'die area. Index Terms-Frequency synthesizer,wideband,tuning gain(Kyco),constant bandwidth,phase noise. VCO Programmable Divider I.INTRODUCTION sda+ ,◆N=94-160 c reset The dual-conversion architecture of digital video broadcasting-terrestrial (DVB-T)tuners which receive Fig.1. Diagram of wideband frequency synthesizer with signals in the 48-862MHz frequency range,demands the differential tuning. use of a wideband frequency synthesizer as the first local oscillator (LO)[1].The wideband frequency synthesizer II.DESIGN CONSIDERATIONS should meet stringent phase noise requirement over the whole frequency range from 1.175GHz to 2GHz without A.Bandwidth sacrificing loop stability.To cover such a wideband frequency range,switching capacitor array is usually used Because the synthesizer is a closed-loop system,its loop in LC voltage-controlled-oscillator (VCO)to extend the bandwidth,which describes the rate of system response tuning range with low VCO tuning gain (Kyco),which and indicates whether it is stable,is an important avoids degrading the phase noise performance [2]. parameter and about 1/20 of the reference frequency.On However,the loop bandwidth(BW).which determines the the other hand,phase noise optimization requires a certain phase noise optimization and loop response characteristics, bandwidth with respect to the given charge pump and will change due to the variation of division ratio and VCO circuits.For every different output frequency,the tuning gain of multi-band VCO [3]. loop bandwidth must be constant to minimize phase noise The block diagram of the wideband frequency variation and guarantee loop stability over a wideband synthesizer is shown in Fig.1,which is completely frequency range.Usually open-loop cut-off frequency is integrated including a phase-frequency detector (PFD),a selected as the loop bandwidth by designers,however,for rail-to-rail differential charge pump (CP),a passive loop third or higher order loop there is no intuitive expression filter (LPF),an wideband LC-VCO,a programmable about it.Loop gain is a good indication of low-pass corner divider,an automatic frequency control (AFC)block and frequency for the open-loop transfer function and is an I2C controller.In order to suppress noise from defined as bandwidth.For typical third-order PLL,loop substrate and power supply,charge pump,LPF and LC- gain can be expressed as [4] VCO are all differentially configured. This paper is organized as follows:Section II shows BW IcK,coR bslckrcoR (b>10) (1) 2πWb+1 2πN some wideband issues;Section III presents the proposed solutions;Section IV describes the experimental results. where Icp is the sink or source current of charge pump, Finally,some conclusions are drawn in Section V. Kvco is the VCO tuning gain,N is the division ratio,R is the loop filter resistor and b is the ratio of Cl over C2.To Corresponding author.Email:zwtang@fudan.edu.cn keep the bandwidth constant without changing the 978-1-4244-1808-4/978-1-4244-1809-1/08/S25.00©2008EEE 303 2008 IEEE Radio Frequency Integrated Circuits Symposium
A Fully Integrated 1.175-to-2GHz Frequency Synthesizer with Constant Bandwidth for DVB-T Applications Lei Lu, Lu Yuan, Hao Min and Zhangwen Tang* ASIC & System State Key Laboratory, Fudan University, Shanghai, China, 201203 Abstract — A fully integrated 1.175 to 2GHz differentially tuned frequency synthesizer aimed for DVB-T tuners is implemented in 0.18-ȝm CMOS. Techniques are proposed to make the loop bandwidth constant across the whole output frequency range to maintain phase noise optimization and loop stability. It exhibits in-band phase noise of -97.6dBc/Hz at 10kHz offset and integrated phase error of 0.63° from 100Hz to 10MHz. The chip draws 10mA from a 1.8V supply while occupying 2.6mm2 die area. Index Terms — Frequency synthesizer, wideband, tuning gain (KVCO), constant bandwidth, phase noise. I. INTRODUCTION The dual-conversion architecture of digital video broadcasting-terrestrial (DVB-T) tuners which receive signals in the 48-862MHz frequency range, demands the use of a wideband frequency synthesizer as the first local oscillator (LO) [1]. The wideband frequency synthesizer should meet stringent phase noise requirement over the whole frequency range from 1.175GHz to 2GHz without sacrificing loop stability. To cover such a wideband frequency range, switching capacitor array is usually used in LC voltage-controlled-oscillator (VCO) to extend the tuning range with low VCO tuning gain (KVCO), which avoids degrading the phase noise performance [2]. However, the loop bandwidth (BW), which determines the phase noise optimization and loop response characteristics, will change due to the variation of division ratio and tuning gain of multi-band VCO [3]. The block diagram of the wideband frequency synthesizer is shown in Fig. 1, which is completely integrated including a phase-frequency detector (PFD), a rail-to-rail differential charge pump (CP), a passive loop filter (LPF), an wideband LC-VCO, a programmable divider, an automatic frequency control (AFC) block and an I2C controller. In order to suppress noise from substrate and power supply, charge pump, LPF and LCVCO are all differentially configured. This paper is organized as follows: Section II shows some wideband issues; Section III presents the proposed solutions; Section IV describes the experimental results. Finally, some conclusions are drawn in Section V. * Corresponding author. Email: zwtang@fudan.edu.cn Vref s1 s2 s2 s1 CP VCO PFD AFC Vref s1 s1 /2 R1 R1 C1/2 C2/2 Programmable Divider fref I 2 C sda scl reset N=94~160 fout 25MHz 1.175~ 2GHz Fig. 1. Diagram of wideband frequency synthesizer with differential tuning. II. DESIGN CONSIDERATIONS A. Bandwidth Because the synthesizer is a closed-loop system, its loop bandwidth, which describes the rate of system response and indicates whether it is stable, is an important parameter and about 1/20 of the reference frequency. On the other hand, phase noise optimization requires a certain bandwidth with respect to the given charge pump and VCO circuits. For every different output frequency, the loop bandwidth must be constant to minimize phase noise variation and guarantee loop stability over a wideband frequency range. Usually open-loop cut-off frequency is selected as the loop bandwidth by designers, however, for third or higher order loop there is no intuitive expression about it. Loop gain is a good indication of low-pass corner frequency for the open-loop transfer function and is defined as bandwidth. For typical third-order PLL, loop gain can be expressed as [4] 1 1 ( 10) 2 12 CP VCO CP VCO IK R b IK R BW b S S Nb N |! (1) where ICP is the sink or source current of charge pump, KVCO is the VCO tuning gain, N is the division ratio, R1 is the loop filter resistor and b is the ratio of C1 over C2. To keep the bandwidth constant without changing the 978-1-4244-1808-4/978-1-4244-1809-1/08/$25.00 © 2008 IEEE 2008 IEEE Radio Frequency Integrated Circuits Symposium RMO4B-4 303
position of poles and zeros when N varies,a simple way is 4nH is used.Such a large VCO gain variation alters the to make Icp match N and hold Kvco. bandwidth greatly,so the phase noise performance will deteriorate and the loop will tumn into instability.Secondly Binary weghied band frequency difference may increase the complexity of Cr the method of AFC.which will be described in the next section. (a) 10 2 mx320MHz/V F-V curve 16 =8 co min aractor array (a) 22 10 -67MH2 kso-100MHz/Vi Kmin40MHZ/V 严28 F-V curve 0.4 0.6 0.8 1.2 14 Tuning Voltage(V) (b) Fig.2.Conventional topology (a)Switching capacitor array and one varactor unit (b)F-V curve with large variations of 1.4 VCO tuning gain and band step. B.VCO Tuning Gain Frequency synthesizers for RF receivers usually employ .4 0.6 0.8 1.2 an LC voltage-controlled oscillator (VCO).The targeted Tuning Voltage(V) 800MHz frequency range requires an oscillation gain of (b) 500MHz/V,with which a 1.6V tuning range is allowed for Fig.3. Proposed topology (a)Size changeable capacitor and the charge pump.Such a high Kvco may worsen the phase varactor array (b)F-V curve with constant VCO tuning gain and noise performance.To cover a wideband frequency range band step. with low Kvco,switching capacitor array is usually adopted,which is shown in Fig.2(a).Varactor Cy is tuned III.SOLUTIONS by the control voltage to change the output frequency continuously,while a binary weighted capacitor array is A.Wideband VCO controlled digitally to shift the output frequency band discretely,where 4bit is used for example. To minimize the variations of both the analog tuning Although the switching capacitor topology is useful to gain Kvco and band step for wideband applications,a extend the output frequency range while maintaining a proposed architecture is shown in Fig.3(a).The idea is to lower Kyco,it has two disadvantages.Firstly,equal make both the size of capacitors and varactors changeable. capacitor is switched in or out of the bank whenever a Instead of using one fixed analog varactor and a binary lower or higher band is required.Due to the nonlinearity weighted capacitor array,a number of capacitors and of frequency to capacitance,Kyco will change by a factor varactors with different values are adopted.At lower of 8 when the output frequency doubles by reducing the frequency band the gain Kyco is low,so a majority of tank capacitance to a quarter [5].The simulated F-V varactor units are connected to the analog control voltage, curve is shown in Fig.2(b),where a tank inductance of and other varactor units are connected to the power supply 304
position of poles and zeros when N varies, a simple way is to make ICP match N and hold KVCO. (a) 0.4 0.6 0.8 1 1.2 1.4 1 1.2 1.4 1.6 1.8 2 2.2 x 109 Tuning Voltage(V) Frequency(Hz) F-V curve (b) Fig. 2. Conventional topology (a) Switching capacitor array and one varactor unit (b) F-V curve with large variations of VCO tuning gain and band step. B. VCO Tuning Gain Frequency synthesizers for RF receivers usually employ an LC voltage-controlled oscillator (VCO). The targeted 800MHz frequency range requires an oscillation gain of 500MHz/V, with which a 1.6V tuning range is allowed for the charge pump. Such a high KVCO may worsen the phase noise performance. To cover a wideband frequency range with low KVCO, switching capacitor array is usually adopted, which is shown in Fig. 2(a). Varactor CV is tuned by the control voltage to change the output frequency continuously, while a binary weighted capacitor array is controlled digitally to shift the output frequency band discretely, where 4bit is used for example. Although the switching capacitor topology is useful to extend the output frequency range while maintaining a lower KVCO, it has two disadvantages. Firstly, equal capacitor is switched in or out of the bank whenever a lower or higher band is required. Due to the nonlinearity of frequency to capacitance, KVCO will change by a factor of 8 when the output frequency doubles by reducing the tank capacitance to a quarter [5]. The simulated F-V curve is shown in Fig. 2(b), where a tank inductance of 4nH is used. Such a large VCO gain variation alters the bandwidth greatly, so the phase noise performance will deteriorate and the loop will turn into instability. Secondly, band frequency difference may increase the complexity of the method of AFC, which will be described in the next section. (a) 0.4 0.6 0.8 1 1.2 1.4 1 1.2 1.4 1.6 1.8 2 2.2 x 109 Tuning Voltage(V) Frequency(Hz) F-V curve (b) Fig. 3. Proposed topology (a) Size changeable capacitor and varactor array (b) F-V curve with constant VCO tuning gain and band step. III. SOLUTIONS A. Wideband VCO To minimize the variations of both the analog tuning gain KVCO and band step for wideband applications, a proposed architecture is shown in Fig. 3(a). The idea is to make both the size of capacitors and varactors changeable. Instead of using one fixed analog varactor and a binary weighted capacitor array, a number of capacitors and varactors with different values are adopted. At lower frequency band the gain KVCO is low, so a majority of varactor units are connected to the analog control voltage, and other varactor units are connected to the power supply 304
or ground to get minimum fixed capacitance.On the C.Charge Pump contrary,at higher frequency band only a minority of varactor units are switched in.On the other hand,to The frequency synthesizer alters its output frequency by changing division ratio N.So when N varies,the loop obtain equal frequency band step,the fixed capacitors are also made changeable. bandwidth changes and the loop characteristics are In this frequency synthesizer,a digital controlled affected.Charge pump current Icp can be programmed to match the division ratio.Some current banks can be in capacitor array (DCCA)divides the whole tuning range into 16 sub-bands to keep a relatively low analog tuning parallel with the major current sources and sinks to gain,while an extra digital controlled varactor array calibrate the total charging and discharging current.By (DCVA)is inserted to equalize the tuning sensitivity. compensating Icp,the term Icp/N can be a constant. Assuming a(i=1,2,,15)the capacitor ratio of DCCA units and Bi (i=1,2,,15)the varactor ratio of DCVA IV.EXPERIMENTAL RESULTS units,total capacitance CoLn across the tank at the center frequency of the n sub-band can be expressed as A prototype is implemented and measured in 0.18-um CMOS process.The measured phase noise at oscillation (Cp+C+(B+Bs)Cr+Cr) (n=1) frequency of 1.6GHz is plotted in Fig.4 and compared to Cp+1+a+…an)C,+(Bn+…As)Crm the simulation result.The spot phase noise is-97.6dBc/Hz +1+R+…B.)Crom (n=2,…,15) (2) at 10kHz offset and -124.2dBc/Hz at 1MHz offset.The Cp+0+a+as)C,+1+月+…Bs)Cran=16) integrated phase error from 100Hz to 10MHz is 0.63 rms. The measured and simulated curves agree very well from where Cp is the parasitic capacitance and Cy.min is the 100Hz to 10MHz.Phase noise contributions of all blocks minimum capacitance of the varactor.Note that n=1 is the are also depicted for simulation results.Charge pump highest frequency band.Similarly,the tuning gain Kvco.n dominates at in-band and out-of-band phase noise is of the n sub-band can be calculated as mainly determined by VCO.Phase noise plots at frequency offset of 10kHz and IMHz are shown in Fig.5. 1 The curves have a flat characteristic across the whole (n=1) 4、LC output range,where the error is below IdB.It is also (3) shown that the closed-loop has an average measured 1+B+…BC (n=2,…,16 bandwidth of 90kHz and the error is within +10%. 60 where oCv/ovmune is the slope of C-V curve for varactor Cy at center frequency.Therefore,by setting ai and Bi -70 properly,the Kvco and band step variations can be greatly -80 i信ūaion, 11.111d reduced.The simulated F-V curve of the proposed 11111川 1入11I1 ↓110 11 90 architecture is shown in Fig.3(b).During the frequency range from IGHz to 2GHz,the frequency band step is -100 nnm 67MHz uniformly and Kvco is 100MHz/V for each band. -110 -120 B.AFC -130 Due to the nonlinearity of the C-V curve of the varactor, .140 Kvco of each frequency band can only be made equal in 1元加T、- P the middle of the tuning range.During a single F-V curve, .150 the slope near the middle is linear and maximal.The AFC 10 103 10 10 10 10 Frequency(Hz) algorithm senses the VCO output center frequency of each band and compares it to the targeted value which is Fig.4. Comparisons of simulation and measured phase noise determined by the division ration.The band of which the at the oscillation frequency of 1.6GHz. center frequency is closest to the targeted value will be selected.As long as the overlapping ratio between two The measured closed-loop output frequency is shown in adjacent bands exceeds 50%,all output frequency points Fig.6,including 71 points of division ratio from 93 to 163. can fall near the middle of the tuning range and have The tuning gain varies from 70MHz/V to 90MHz/V,of rather linear tuning gains.In this way,the tuning gain which the variation is only +12.5%in such a wide variations can be minimized further. frequency range of 825MHz.Due to the AFC operation, 305
or ground to get minimum fixed capacitance. On the contrary, at higher frequency band only a minority of varactor units are switched in. On the other hand, to obtain equal frequency band step, the fixed capacitors are also made changeable. In this frequency synthesizer, a digital controlled capacitor array (DCCA) divides the whole tuning range into 16 sub-bands to keep a relatively low analog tuning gain, while an extra digital controlled varactor array (DCVA) is inserted to equalize the tuning sensitivity. Assuming Įi (i=1, 2, ···, 15) the capacitor ratio of DCCA units and ȕi (i=1, 2, ···, 15) the varactor ratio of DCVA units, total capacitance Ctot,n across the tank at the center frequency of the nth sub-band can be expressed as 1 15 ,min (0.9) 1 1 15 ,min , 1 1 (0.9) 1 15 1 15 (0. ( ) ( 1) (1 ) ( ) (1 ) ( 2, ,15) (1 ) (1 ) Pf V V P nf n V tot n n V PfV CC C C n C CC C C n CCC E E DD E E E E DD EE 9) ( 16) n ° ° ® ° ° ¯ (2) where CP is the parasitic capacitance and CV,min is the minimum capacitance of the varactor. Note that n=1 is the highest frequency band. Similarly, the tuning gain KVCO,n of the nth sub-band can be calculated as 3 , , 1 1 3 , 1 ( 1) 4 1 ( 2, ,16) 4 tune tune V tot n tune V center VCO n n V tot n tune V center C n LC V K C n LC V S E E S w ° w °° ® ° w ° w °¯ (3) where CV/Vtune is the slope of C-V curve for varactor CV at center frequency. Therefore, by setting Įi and ȕi properly, the KVCO and band step variations can be greatly reduced. The simulated F-V curve of the proposed architecture is shown in Fig. 3(b). During the frequency range from 1GHz to 2GHz, the frequency band step is 67MHz uniformly and KVCO is 100MHz/V for each band. B. AFC Due to the nonlinearity of the C-V curve of the varactor, KVCO of each frequency band can only be made equal in the middle of the tuning range. During a single F-V curve, the slope near the middle is linear and maximal. The AFC algorithm senses the VCO output center frequency of each band and compares it to the targeted value which is determined by the division ration. The band of which the center frequency is closest to the targeted value will be selected. As long as the overlapping ratio between two adjacent bands exceeds 50%, all output frequency points can fall near the middle of the tuning range and have rather linear tuning gains. In this way, the tuning gain variations can be minimized further. C. Charge Pump The frequency synthesizer alters its output frequency by changing division ratio N. So when N varies, the loop bandwidth changes and the loop characteristics are affected. Charge pump current ICP can be programmed to match the division ratio. Some current banks can be in parallel with the major current sources and sinks to calibrate the total charging and discharging current. By compensating ICP, the term ICP/N can be a constant. IV. EXPERIMENTAL RESULTS A prototype is implemented and measured in 0.18-ȝm CMOS process. The measured phase noise at oscillation frequency of 1.6GHz is plotted in Fig. 4 and compared to the simulation result. The spot phase noise is –97.6dBc/Hz at 10kHz offset and -124.2dBc/Hz at 1MHz offset. The integrated phase error from 100Hz to 10MHz is 0.63° rms. The measured and simulated curves agree very well from 100Hz to 10MHz. Phase noise contributions of all blocks are also depicted for simulation results. Charge pump dominates at in-band and out-of-band phase noise is mainly determined by VCO. Phase noise plots at frequency offset of 10kHz and 1MHz are shown in Fig. 5. The curves have a flat characteristic across the whole output range, where the error is below 1dB. It is also shown that the closed-loop has an average measured bandwidth of 90kHz and the error is within ±10%. 102 103 104 105 106 107 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 Frequency (Hz) Phase Noise (dBc/Hz) Fig. 4. Comparisons of simulation and measured phase noise at the oscillation frequency of 1.6GHz. The measured closed-loop output frequency is shown in Fig. 6, including 71 points of division ratio from 93 to 163. The tuning gain varies from 70MHz/V to 90MHz/V, of which the variation is only ±12.5% in such a wide frequency range of 825MHz. Due to the AFC operation, 305
the control voltages of all output frequency fall between TABLE I.PERFORMANCE COMPARISONS 0.55V to 0.95V.which are in the linear gain region. Ref. [6 [ This Work The die micrograph is shown in Fig.7,which also Output includes measured performance summary.Table I 2.24-4.48GHz 1.1-2.2GHz 1.175-2GHz Frequency presents a performance comparison with other frequency synthesizers recently reported for DVB applications. VCO type Ring Three LC Single LC Phase noise -98@100kHz 97.6@10kHz 90@10kHz 90 130 (dBc/Hz) -100@1MHz -124.2@1MHz RMS phase -95 120 0.8 1.5° 0.63 error -100 @10kHz offseb 8 Power 132mW N.A. 18mw -105 100 0.13-m 0.18-μm 0.18-um Technology 男 +90 CMOS CMOS CMOS -110 115 80 V.CONCLUSIONS .120 @iMHz offset Constant bandwidth is essential in phase noise -125 、 -160 optimization and loop stability for frequency synthesizers .130 50 Some techniques are presented to maintain the bandwidth 12 1.4 1.6 1.8 2 over a wideband frequency Output Frequency(Hz) range.A 1.175-2GHz x10 synthesizer has been fabricated and validated in 0.18-um Fig.5 Measured phase noise and bandwidth CMOS process.It acquires flat phase noise characteristics across the whole tuning range with a power consumption utout frequer of 18mW from a 1.8V supply. 0M01 ACKNOWLEDGEMENT 1.8 0110 The authors would like to thank SMIC and Chrontel for 1 0111 1000 1001 their help.The work was partly supported by Chinese 1.6 National Programs for High Technology Research and 16 Development with Grant No.2007AA01Z282. 1101 110 1111 REFERENCES AFC operation region [1]D.Saias,et al.,"A 0.12um CMOS DVB-T Tuner,"/SSCC .1 -0.8 -0.6 -04-0.200.20.4 0.6 0.8 Dig.Tech.Papers,pp.430-431.Feb.2005 Differential Control Voltage (V) [2]S.Levantino,et al.,"Frequency dependence on bias current Fig.6. Measured tuning curves of 16 sub-bands in 5-GHz CMOS VCOs:impact on tuning range and flicker noise upconversion,"IEEE J.Solid-State Circuits,vol.37 pp.1003-1011,Aug.2002. [3) John G.Maneatis,et al.,"Self-biased high-bandwidth low- jitter 1-to-4096 multiplier clock generator PLL."/EEE J. Solid-State Circuits,vol.38,pp.1795-1803,Nov.2003. [4]Floyd M.Gardner,Phaselock Techniques,Third Ed.,New York:Wiley,2005 [5]D.Hauspie,E-Ch.Park and J.Craninckx,"Wideband VCO with simultaneous switching of frequency band,active core, and varactor size,"IEEEJ.Solid-State Circuits,vol.42,pp. 1472-1480,July2007. 8mC 125 MHz [6 A.Maxim,R.Poorfard and J.Kao,"A sub-1.5rms Phase 18V 175-2GH Noise Ring-Oscillator-Based Frequency Synthesizer for Bandwicth Low-IF Single-Chip DBS Satellite Tuner-Demodulator (BoHz) -124.21MHz Chip Area 2.6mm RMS Phase SoC,"ISSCC Dig.Tech.Papers,pp.618-619,Feb.2006. 103H2-10MHz 063 18 mV [7]M.Gupta,S.Lerstaveesin,D.Kang,et al.,"A 48-to- 860MHz CMOS Direct-Conversion TV,"ISSCC Dig.Tech. Fig.7.Die micrograph and performance summary Papers,pp.206-207,Feb.2007. 306
the control voltages of all output frequency fall between 0.55V to 0.95V, which are in the linear gain region. The die micrograph is shown in Fig. 7, which also includes measured performance summary. Table I presents a performance comparison with other frequency synthesizers recently reported for DVB applications. 1.2 1.4 1.6 1.8 2 x 109 -130 -125 -120 -115 -110 -105 -100 -95 -90 Output Frequency (Hz) Phase Noise (dBc/Hz) Fig. 5. Measured phase noise and bandwidth. -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 Differential Control Voltage (V) Frequency (GHz) Closed-loop output frequency band 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Fig. 6. Measured tuning curves of 16 sub-bands. Fig. 7. Die micrograph and performance summary. TABLE I. PERFORMANCE COMPARISONS Ref. [6] [7] This Work Output Frequency 2.24-4.48GHz 1.1-2.2GHz 1.175-2GHz VCO type Ring Three LC Single LC Phase noise (dBc/Hz) -98@100kHz -100@1MHz -90@10kHz -97.6@10kHz -124.2@1MHz RMS phase error 0.8° 1.5° 0.63° Power 132mW N.A. 18mW Technology 0.13-ȝm CMOS 0.18-ȝm CMOS 0.18-ȝm CMOS V. CONCLUSIONS Constant bandwidth is essential in phase noise optimization and loop stability for frequency synthesizers. Some techniques are presented to maintain the bandwidth over a wideband frequency range. A 1.175-2GHz synthesizer has been fabricated and validated in 0.18-ȝm CMOS process. It acquires flat phase noise characteristics across the whole tuning range with a power consumption of 18mW from a 1.8V supply. ACKNOWLEDGEMENT The authors would like to thank SMIC and Chrontel for their help. The work was partly supported by Chinese National Programs for High Technology Research and Development with Grant No. 2007AA01Z282. REFERENCES [1] D. Saias, et al., “A 0.12ȝm CMOS DVB-T Tuner,” ISSCC Dig. Tech. Papers, pp. 430-431, Feb. 2005. [2] S. Levantino, et al., “Frequency dependence on bias current in 5-GHz CMOS VCOs: impact on tuning range and flicker noise upconversion,” IEEE J. Solid-State Circuits, vol. 37, pp. 1003-1011, Aug. 2002. [3] John G. Maneatis, et al., “Self-biased high-bandwidth lowjitter 1-to-4096 multiplier clock generator PLL,” IEEE J. Solid-State Circuits, vol. 38, pp. 1795-1803, Nov. 2003. [4] Floyd M. Gardner, Phaselock Techniques, Third Ed., New York: Wiley, 2005. [5] D. Hauspie, E-Ch. Park and J. Craninckx, “Wideband VCO with simultaneous switching of frequency band, active core, and varactor size,” IEEE J. Solid-State Circuits, vol. 42, pp. 1472-1480, July 2007. [6] A. Maxim, R. Poorfard and J. Kao, “A sub-1.5°rms PhaseNoise Ring-Oscillator-Based Frequency Synthesizer for Low-IF Single-Chip DBS Satellite Tuner-Demodulator SoC,” ISSCC Dig. Tech. Papers, pp. 618-619, Feb. 2006. [7] M. Gupta, S. Lerstaveesin, D. Kang, et al., “A 48-to- 860MHz CMOS Direct-Conversion TV,” ISSCC Dig. Tech. Papers, pp. 206-207, Feb. 2007. 306