复旦大学：微电子工程教学资源（参考论文）A Wideband CMOS Variable Gain Low Noise Amplifier Based on Single-to-Differential Stage for TV Tuner Applications

16-4 IEEE Asian Solid-State Circuits Conference November 3-5,2008/Fukuoka,Japan A Wideband CMOS Variable Gain Low Noise Amplifier Based on Single-to-Differential Stage for TV Tuner Applications Kefeng Han',Liang Zou',Youchun Liao2,Hao Min'and Zhangwen Tang'' ASIC System State Key Laboratory,Fudan University,Shanghai 201203,China 2 Ratio Microelectronics Technology Co.,Ltd,Shanghai 200433,China Abstract-A wideband CMOS variable gain low noise 75Q RF Front-end amplifier (VGLNA)used for TV tuner is presented.A Up Mixer Down Mixer single-to-differential (S2D)circuit other than an off-chip balun is applied for high gain mode and a resistive attenuator is for five steps (6dB per step)attenuation in low gain mode.The performance of S2D,especially the noise factor is analyzed.The Band-Limited LNA chip is implemented in a 0.18-um 1P6M mixed-signal CMOS Filter (using S2D) process.Measurements show that in the 50-860MHz frequency range,the VGLNA achieves 15dB maximum gain,31dB LO1 LO2 variable gain range,a minimum 3.8dB noise figure and 2.6dBm IIP3 at 15dB gain while consumes 5.7mA from a 1.8V supply. PLL Q Index Terms-LNA,S2D,Attenuator,Wideband,Tuner,Balun Fig.1 A fully integrated tuner architecture using S2D I.INTRODUCTION Although many efforts have been exerted,implementation This paper is arranged as follows:the performances of S2D of fully integrated chip for TV tuner application is still a great are analyzed in section II;we then turn to attenuator design in challenge,to the standard of DVB-C (50M-860MHz)for section Il;the architecture of LNA is given in section IV; example.Recent works on wideband LNA [1-2]based on section V shows the chip implementation and measurements; off-chip balun have shown good performances,such as low the last section is for conclusion. NF,high linearity and excellent input matching.However, the off-chip balun adds extra cost,loss and much PCB size; II.SINGLE-TO-DIFFERENTIAL STAGE meanwhile,an on-chip passive balun may account for large die area and not be acceptable for low frequency and A.Introduction of S2D Stage wideband applications. Thus,a single-to-differential stage (S2D)[3-6]is adopted in order to replace the balun for less area and cost without RL1之RFout R2 degrade the performances.Ref [3]has made S2D a part of the CG RF front-end,however,an off-chip inductor is applied and performance analysis of the S2D is not given.In [6],a CS balun-LNA is presented with excellent performances for less M2 gain and phase error,but it can not maintain the performances RFin at 50MHz and in high input levels situation;a capacitive lB attenuator is employed in [9],but it needs an extra circuit for input matching and the scheme requires one Gm-stage for each attenuation.In this paper,a fully integrated wideband LNA based on S2D with resistive attenuator for TV tuner Fig.2 A well-known schematic of single-to-differential circuit applications is implemented. A double-conversion low-IF (DLIF)DVB-C tuner RF A traditional well-known S2D circuit is shown in Fig.2.In architecture is shown in Fig.1.The LNA based on S2D stage this circuit,M is configured as a common gate(CG)stage for is used as a replacement of traditional scheme which employs positive amplifier with its load RL,the CG stage also differential LNA with an off-chip balun. provides input impedance matching over a wide range of frequency;M2 together with R_2 is as a common source(CS) stage to offer a same amplitude but anti-phase output signal This work is partly supported by Chinese National 863 Programs for High compared to the CG stage.The output differential signal Technology Research and Development with Grant No.2007AA01Z282. could be sent to the following stage such as an up-conversion Corresponding author.Email:zwtang@fudan.edu.cn 978-1-4244-2605-8/08/$25.00©2008IEEE 457

Abstract²$ ZLGHEDQG &026 YDULDEOH JDLQ ORZ QRLVH DPSOLILHU 9*/1$ XVHG IRU 79 WXQHU LV SUHVHQWHG $ VLQJOHWRGLIIHUHQWLDO6'FLUFXLWRWKHUWKDQDQRIIFKLSEDOXQ LV DSSOLHG IRUKLJK JDLQPRGH DQGDUHVLVWLYH DWWHQXDWRULV IRU ILYH VWHSV G% SHU VWHS DWWHQXDWLRQ LQ ORZ JDLQ PRGH 7KH SHUIRUPDQFHRI6'HVSHFLDOO\WKHQRLVHIDFWRULVDQDO\]HG7KH FKLS LV LPSOHPHQWHG LQ D ȝP 30 PL[HGVLJQDO &026 SURFHVV0HDVXUHPHQWVVKRZWKDWLQWKH0+]IUHTXHQF\ UDQJH WKH 9*/1$ DFKLHYHV G% PD[LPXP JDLQ G% YDULDEOHJDLQUDQJHDPLQLPXPG%QRLVHILJXUHDQGG%P ,,3DWG%JDLQZKLOHFRQVXPHVP$IURPD9VXSSO\ ,QGH[7HUPV²/1$6'$WWHQXDWRU:LGHEDQG7XQHU%DOXQ I. INTRODUCTION Although many efforts have been exerted, implementation of fully integrated chip for TV tuner application is still a great challenge, to the standard of DVB-C (50M-860MHz) for example. Recent works on wideband LNA [1-2] based on off-chip balun have shown good performances, such as low NF, high linearity and excellent input matching. However, the off-chip balun adds extra cost, loss and much PCB size; meanwhile, an on-chip passive balun may account for large die area and not be acceptable for low frequency and wideband applications. Thus, a single-to-differential stage (S2D) [3-6] is adopted in order to replace the balun for less area and cost without degrade the performances. Ref [3] has made S2D a part of the RF front-end, however, an off-chip inductor is applied and performance analysis of the S2D is not given. In [6], a balun-LNA is presented with excellent performances for less gain and phase error, but it can not maintain the performances at 50MHz and in high input levels situation; a capacitive attenuator is employed in [9], but it needs an extra circuit for input matching and the scheme requires one Gm-stage for each attenuation. In this paper, a fully integrated wideband LNA based on S2D with resistive attenuator for TV tuner applications is implemented. A double-conversion low-IF (DLIF) DVB-C tuner RF architecture is shown in Fig.1. The LNA based on S2D stage is used as a replacement of traditional scheme which employs differential LNA with an off-chip balun. This work is partly supported by Chinese National 863 Programs for High Technology Research and Development with Grant No.2007AA01Z282. * Corresponding author. Email: zwtang@fudan.edu.cn . Fig. 1 A fully integrated tuner architecture using S2D This paper is arranged as follows: the performances of S2D are analyzed in section II; we then turn to attenuator design in section III; the architecture of LNA is given in section IV; section V shows the chip implementation and measurements; the last section is for conclusion. II. SINGLE-TO-DIFFERENTIAL STAGE A. Introduction of S2D Stage Fig. 2 A well-known schematic of single-to-differential circuit A traditional well-known S2D circuit is shown in Fig.2. In this circuit, M1 is configured as a common gate (CG) stage for positive amplifier with its load RL1, the CG stage also provides input impedance matching over a wide range of frequency; M2 together with RL2 is as a common source (CS) stage to offer a same amplitude but anti-phase output signal compared to the CG stage. The output differential signal could be sent to the following stage such as an up-conversion $:LGHEDQG&0269DULDEOH*DLQ/RZ1RLVH$PSOLILHU%DVHGRQ 6LQJOHWR'LIIHUHQWLDO6WDJHIRU797XQHU$SSOLFDWLRQV Kefeng Han1 , Liang Zou1 , Youchun Liao2 , Hao Min1 and Zhangwen Tang1 * 1 ASIC & System State Key Laboratory, Fudan University, Shanghai 201203, China 2Ratio Microelectronics Technology Co., Ltd, Shanghai 200433, China 978-1-4244-2605-8/08/$25.00 ©2008 IEEE 457 IEEE Asian Solid-State Circuits Conference November 3-5, 2008 / Fukuoka, Japan 16-4

mixer in Fig.1.Ig is a current bias for CG stage and can be The first part in parentheses is for RC path to positive replaced by an off-chip inductor [3-4]or a resistor [6]. output,the second is due to CG stage and last part is the gain It has found that the S2D circuit in Fig.2 can achieve a low of CS stage.For balanced output applications,the amplitudes NF because the noise originated from M appear to be of positive and negative outputs should be equal common-mode at the differential outputs [5],thus it can be 1+8ml=8m4 greatly restrained if the S2D stage is followed by a fully (3) 8m2 8ms differential circuit with high CMRR. A modified S2D circuit is given in Fig.3.Here,M is for CG 3) Noise Factor stage and input matching,M is for CS amplifier.M2 and Ms are used as MOS loads to improve linearity [7].C,together with R,forms a high pass positive path for gain enhancement and makes sure that M can be in saturation for a higher gain. correlated The configuration of C,with R,M with M,can reduce noise originated from M [8].For integration,M;is applied as a current bias for CG stage,obviously,it adds a part of noise to Vn☒ ☒Vout output,and the impact on the noise performance will be discussed next. uncorrelated Fig.4 Noise figure analysis for S2D VB. A simple way of analysis for S2D in Fig.2 or Fig.3 is given in Fig.4.The differential signal amplified by A,and A2 is correlated and doubles in amplitude when added if a same gain is assumed for A,and 42.The noises originated from the Vn☒ M two amplifiers are uncorrelated and should be superposed in power [7],thus the SNRo is improved compared to a simple amplifier.The noise factor is calculated to be VB F=14+四运 (4) (24)4kTR Here,Vn is output noise from A and Vun is output Fig.3 Proposed S2D Circuit noise of 42 under the CG input matching.The same gain is Ar and Rs represents the source impedance.Apply the noise B.Performance Analysis factors of the two stages,an alternative expression is 1)Input matching F=1+F-1+E-1 (5) 44 If C>C.the input impedance of the S2D is Here,F,is noise factor of A,and F,is ofA2.The derived Z=(8m+sC+sCn)月 (1) noise factor can be seen in(6)with substitution of the noise Set gm=1/Rs for wideband input matching without taking factors of CS and CG stage respectively.Noise from M;is not care of the effect of input capacitances,however,as included here. frequency increases,the input impedance will be greatly affected by the gate-source capacitances of M and M,thus F=1+(B-8 ++8m4+ Y5(6) 4Rs Aigml AgmaRs ArgisRs gmsRs the dimensions of M,and M,should keep small enough for good input matching.Unfortunately,a small dimension will Using small-signal model for each noise source in Fig.3 bring much impact of flicker noise at 50MHz.As a tradeoff (M-Ms)under the conditions of (2)and (3),the actual noise factor of Fig.3 can be represented as between input matching and noise figure,a minimum length of 0.35-um is adopted for M-M2 and M-Ms here. +令+安gR+%8风+ F=1+ Y2 (7) ArgmsRs ArgmsRs 2)Gain of the S2D stage The second term in (6)is different with (7)because the The voltage gain of differential output versus single-ended noise from M,can also be a correlated output at CS stage and input can be represented as noise of M:can be seen as an outside input noise in (6),thus =1+8m+84月 (6)and(7)will coincide.According to simulation,the main Ay=- (2) sources of noise come from M.M,and M,it is a tradeoff V gm2 gms)1+gmRs between power dissipation and low noise figure. 458

mixer in Fig.1. IB is a current bias for CG stage and can be replaced by an off-chip inductor [3-4] or a resistor [6]. It has found that the S2D circuit in Fig.2 can achieve a low NF because the noise originated from M1 appear to be common-mode at the differential outputs [5], thus it can be greatly restrained if the S2D stage is followed by a fully differential circuit with high CMRR. A modified S2D circuit is given in Fig.3. Here, M1 is for CG stage and input matching, M4 is for CS amplifier. M2 and M5 are used as MOS loads to improve linearity [7]. C1 together with R1 forms a high pass positive path for gain enhancement and makes sure that M1 can be in saturation for a higher gain. The configuration of C1 with R1, M1 with M2 can reduce noise originated from M1 [8]. For integration, M3 is applied as a current bias for CG stage, obviously, it adds a part of noise to output, and the impact on the noise performance will be discussed next. Fig. 3 Proposed S2D Circuit B. Performance Analysis 1) Input matching If C3>>Cgs1, the input impedance of the S2D is   1 Z g sC sC in m gs gs 114    (1) Set gm1=1/RS for wideband input matching without taking care of the effect of input capacitances, however, as frequency increases, the input impedance will be greatly affected by the gate-source capacitances of M1 and M4, thus the dimensions of M1 and M4 should keep small enough for good input matching. Unfortunately, a small dimension will bring much impact of flicker noise at 50MHz. As a tradeoff between input matching and noise figure, a minimum length of 0.35-ȝm is adopted for M1-M2 and M4-M5 here. 2) Gain of the S2D stage The voltage gain of differential output versus single-ended input can be represented as 1 4 25 1 1 1 1 d mm V s m m mS V gg A V g g gR § ·   ¨ ¸ © ¹  (2) The first part in parentheses is for RC path to positive output, the second is due to CG stage and last part is the gain of CS stage. For balanced output applications, the amplitudes of positive and negative outputs should be equal 1 4 2 5 1 m m m m g g g g  (3) 3) Noise Factor Fig. 4 Noise figure analysis for S2D A simple way of analysis for S2D in Fig.2 or Fig.3 is given in Fig.4. The differential signal amplified by A1 and A2 is correlated and doubles in amplitude when added if a same gain is assumed for A1 and A2. The noises originated from the two amplifiers are uncorrelated and should be superposed in power [7], thus the SNRout is improved compared to a simple amplifier. The noise factor is calculated to be   2 2 ,1 ,2 2 1 2 4 out n out n V S V V F A kTR   (4) Here, Vout,n1 is output noise from A1 and Vout,n2 is output noise of A2 under the CG input matching. The same gain is AV and RS represents the source impedance. Apply the noise factors of the two stages, an alternative expression is 1 2 1 1 1 4 4 F F F     (5) Here, F1 is noise factor of A1 and F2 is of A2. The derived noise factor can be seen in (6) with substitution of the noise factors of CS and CG stage respectively. Noise from M3 is not included here.   2 1 1 2 2 44 5 21 2 2 2 12 5 5 1 4 S m m SV m V m S V m S V m S R g g F RAg Ag R Ag R Ag R J J J J        (6) Using small-signal model for each noise source in Fig.3 (M1-M5) under the conditions of (2) and (3), the actual noise factor of Fig.3 can be represented as 1 2 44 5 22 2 2 3 3 2 55 1 m m S V Vm S Vm S Vm S g F gR A Ag R Ag R Ag R J J J J      J (7) The second term in (6) is different with (7) because the noise from M1 can also be a correlated output at CS stage and noise of M3 can be seen as an outside input noise in (6), thus (6) and (7) will coincide. According to simulation, the main sources of noise come from M4, M2 and M3, it is a tradeoff between power dissipation and low noise figure. 458

III.ATTENUATOR DESIGN Passive attenuator is often used to deal with high input levels ahead of LNA without adds much non-linearity in order to achieve high dynamic range [9]when nonlinearity becomes a dominate factor for deterioration of SNR.The attenuator based on resistors has excellent linearity and accounts for less area,impedance matching can be available alone. RFn☒ ☒RF Fig.7 Die Microphotograph of the Wideband LNA R 2R 2只 2 -10 -12 High Gain Mode Fig.5 A five steps resistive attenuator -14 (Due to S2Dj) 1Attenuation (Due to S2D2&ATT) Fig.5 shows a resistive attenuator with five gain steps. -16 Attenuation is realized by controls of switches S-Ss.The -18 switch is implemented by NMOS with minimum channel length and the resistors are implemented by active n-diffusion 20 Low Gain Mode resistors with flat resistance response over the bandwidth. (Due to ATT When one of the switches is on,the impedance seen from RFi is a constant,given as -24 100200300400500600700800 R.R (8) Frequency (MHz) If the source impedance is 750,the value for R in Fig.5 can Fig.8 Measured input retum loss(S11)versus frequency be calculated to be 112.50. V.CHIP IMPLEMENTATION AND MEASUREMENT The chip was fabricated in a 0.18-um 1P6M mixed-signal IV.ARCHITECTURE OF LNA CMOS process and the microphotograph is shown in Fig.7. The total area of this VGLNA is 0.6x0.48 mm2 excluding all The whole simplified LNA is shown in Fig.6,S2D,is used the ESD protected PADs and source follow buffers. for low noise figure and input matching at 15dB fixed gain Input return loss(S11)is measured and plotted in Fig.8 when the attenuator and S2D2 is shut down.Attenuator with Due to input capacitances,the S11 degrades as the frequency S2D2 is in the low gain path for attenuation and input matching when S2D,is disabled,the gain step is 6dB.C,is an increases;however,the curves of S11 at all gain steps are still below-10dB over the whole bandwidth. AC-coupled capacitor for S2D2 and should be chosen large Measured NF is 3.8-5.0dB from 50-860MHz as shown in enough to avoid much gain loss at 50MHz.The outputs are Fig.9,the increment of NF at high frequency is due to output switched between the two different work modes.In this scheme,only two S2D stages are used. mismatch and gain drops,while at 50MHz,the contribution of flicker noise grows rapidly. IIP3 illustrated in Fig.10 is 2.6dBm and IIP2 is 8.6dBm at 15dB gain with two-tone tests.The input referred 1dB High Gain Mode compression point is-6dBm which is in accordance with the simulated-5.8dBm. RFn☒ Measurements show a maximum gain of 15dB and the gain step is about 6dB.The NF and IIP3 as function of gain control steps are given in Fig.11.It can be seen that NF increases from 4.2dB to 35.4dB and IIP3 increases from 2.6dBm to Low Gain Mode 24.6dBm as the gain drops from 15dB to -16dB at the frequency of 500MHz.IIP3 is limited by non-linearity of Fig.6 Simplified schematic of VGLNA input NMOS switch(S in Fig.5)if it exceeds 20dBm. 459

III. ATTENUATOR DESIGN Passive attenuator is often used to deal with high input levels ahead of LNA without adds much non-linearity in order to achieve high dynamic range [9] when nonlinearity becomes a dominate factor for deterioration of SNR. The attenuator based on resistors has excellent linearity and accounts for less area, impedance matching can be available alone. RFout R R R R R R 2R 2R 2R S5 S4 S3 S2 S1 RFin Rin Fig. 5 A five steps resistive attenuator Fig.5 shows a resistive attenuator with five gain steps. Attenuation is realized by controls of switches S1-S5. The switch is implemented by NMOS with minimum channel length and the resistors are implemented by active n-diffusion resistors with flat resistance response over the bandwidth. When one of the switches is on, the impedance seen from RFin is a constant, given as 2 3 Rin R (8) If the source impedance is 75ȍ, the value for R in Fig.5 can be calculated to be 112.5ȍ. IV. ARCHITECTURE OF LNA The whole simplified LNA is shown in Fig.6, S2D1 is used for low noise figure and input matching at 15dB fixed gain when the attenuator and S2D2 is shut down. Attenuator with S2D2 is in the low gain path for attenuation and input matching when S2D1 is disabled, the gain step is 6dB. C1 is an AC-coupled capacitor for S2D2 and should be chosen large enough to avoid much gain loss at 50MHz. The outputs are switched between the two different work modes. In this scheme, only two S2D stages are used. RFin RFout S2D1 ATT S2D2 C1 High Gain Mode Low Gain Mode s0 s0 s0 s0 Fig. 6 Simplified schematic of VGLNA ATT C1 S2D2 S2D1 SF Buffer Bias Fig. 7 Die Microphotograph of the Wideband LNA Fig. 8 Measured input return loss (S11) versus frequency V. CHIP IMPLEMENTATION AND MEASUREMENT The chip was fabricated in a 0.18-ȝm 1P6M mixed-signal CMOS process and the microphotograph is shown in Fig.7. The total area of this VGLNA is 0.6×0.48 mm2 excluding all the ESD protected PADs and source follow buffers. Input return loss (S11) is measured and plotted in Fig.8. Due to input capacitances, the S11 degrades as the frequency increases; however, the curves of S11 at all gain steps are still below -10dB over the whole bandwidth. Measured NF is 3.8-5.0dB from 50-860MHz as shown in Fig.9, the increment of NF at high frequency is due to output mismatch and gain drops, while at 50MHz, the contribution of flicker noise grows rapidly. IIP3 illustrated in Fig.10 is 2.6dBm and IIP2 is 8.6dBm at 15dB gain with two-tone tests. The input referred 1dB compression point is -6dBm which is in accordance with the simulated -5.8dBm. Measurements show a maximum gain of 15dB and the gain step is about 6dB.The NF and IIP3 as function of gain control steps are given in Fig.11. It can be seen that NF increases from 4.2dB to 35.4dB and IIP3 increases from 2.6dBm to 24.6dBm as the gain drops from 15dB to -16dB at the frequency of 500MHz. IIP3 is limited by non-linearity of input NMOS switch (Si in Fig.5) if it exceeds 20dBm. 459

40 NF ◆-Gain 01P3 49 20 IIP3 is Limited 10 by Input NMOS Switch 量-Measurement -Simulation 10 -Measured Fit Measured 500MHz 20 200 400 600 800 d Frequency (MHz) Gain Control Steps Fig.9 Measured and simulated NF at 15dB gain Fig.11 Measured NF/Gain IIP3 at all gain steps TABLEI Summary of Measurements Performance Comparison f=495MHz [3] 9] [101 This work =505MHz Technology 0.18um 0.18um SiGe 0.18μm 0 CMOS CMOS BiCMOS CMOS Supply (V) 1.8 1.8 2.9 1.8 20 BW(MHz) 470-860 470.870 473.767 50-860 S11(dB) <.10 11 N/A <-10 40 Gain(dB) 25 16 19 15 NF(dB) 4.5 4.3 2.7 4.2 -60 IIP3(dBm) 4 -1.5 -14 2.6 Power(mW) 16 22 25 10 IIP3=2.6dBm 0 Area (mm) 0.52 0.32 N/A 0.29 FOM 0.143 0.072 0008 1.117 .35 -30-25-20-15-10-5 The PADs are not included Input Power (dBm) ACKNOWLEDGMENT Fig.10 Measured IIP3 at 15dB gain The authors would like to thank Lee Yang,Xinyu Wang and Xinzhong Duo of SMIC (Shanghai)for chip fabrication VI.CONCLUSION and testing support. In this paper,a CMOS wideband variable gain low noise REFERENCES amplifier based on S2D stage is presented;a resistive attenuator is employed to realize a 6dB gain step and input [1]Youchun Liao,Zhangwen Tang.Hao Min."A CMOS Wide-Band matching in low gain mode.Measurements show that in Low-Noise Amplifier with Balun-based Noise-Canceling Technique," IEEE Asian Solid-State Circuits Conf,2007. 50-860MHz frequency range,the VGLNA achieves good [2] Patrick Antonie.,et al,"A Direct-Conversion Receiver for DVB-H," input matching (S11<-10dB),an average noise figure of IEEE ISSCC.2005. 4.2dB.15dB maximum gain,31dB variable gain range and an [3] Tae Wook Kim.,et al,"A 13-dB IIP3 Improved Low-Power CMOS RF IIP3 of 2.6dBm at 15dB gain while it only draws 5.7mA from Programmable Gain Amplifier Using Differential Circuit Transconductance Linearization for Various Terrestrial Mobile D-TV a 1.8V supply. Applications,"IEEE J.Solid-State Circuits,Vol.41,No.4,April 2006. Table I has summarized the measurements of this VGLNA. [4 Larry Connell.,et al,"A CMOS Broadband Tuner IC,"/EEE performance comparison is also given.Among all the works ISSCC,2002. without off-chip balun used for TV tuner applications,this [5] S.Chehrazi.,et al,"A 6.5GHz Wideband CMOS Low Noise Amplifier for Multi-Band Use,"IEEE Custom Integrated Circuits Conf,2005. work provides a moderate NF,a much higher IIP3 and [6] Stephan C.Blaakmeer.,et al,"Wideband Balun-LNA with Simultaneous consumes less power with less die area. Output Balancing,Noise-Canceling and Distortion-Canceling."IEEE For comparison between the works listed here,a FOM is Solid-State Circuits,Vol.43,No.6,June 2008. introduced [1] 7刀 Behzad Razavi,Design of Analog CMOS Integrated Circuits, FOM=Gain-IIP3 BW U.S.:McGrawHill,2001. (9) [8]Federico Bruccoleri.,et al,"Generating All Two-MOS-Transistor ΓP(F-)f Amplifiers Leads to New Wide-Band LNAs,",IEEE J.Solid-State In(9).Gain and F are in absolute values,IIP3 and Pde are Circuits,Vol.36.No.7,July 2001. [9] in milliwatts and the bandwidth is replaced by BWf.This Jianhong Xiao.,et al,"A High Dynamic Range CMOS Variable Gain Amplifier for Mobile DTV Tuner,"IEEE J.Solid-State Circuits,Vol.42, work achieves a better FOM compared with the other works, No.2.February 2007. as can be seen in TABLE I. [10]Shin'ichiro Azuma,et al,"A Digital Terrestrial Television (ISDB-T) Tuner for Mobile Applications,"IEEE /SSCC.2004. 460

1RLVH)LJXUHG% Fig. 9 Measured and simulated NF at 15dB gain Fig. 10 Measured IIP3 at 15dB gain VI. CONCLUSION In this paper, a CMOS wideband variable gain low noise amplifier based on S2D stage is presented; a resistive attenuator is employed to realize a 6dB gain step and input matching in low gain mode. Measurements show that in 50-860MHz frequency range, the VGLNA achieves good input matching (S11<-10dB), an average noise figure of 4.2dB, 15dB maximum gain, 31dB variable gain range and an IIP3 of 2.6dBm at 15dB gain while it only draws 5.7mA from a 1.8V supply. Table I has summarized the measurements of this VGLNA, performance comparison is also given. Among all the works without off-chip balun used for TV tuner applications, this work provides a moderate NF, a much higher IIP3 and consumes less power with less die area. For comparison between the works listed here, a FOM is introduced [1] 3 ( 1) dc c Gain IIP BW FOM P F f  (9) In (9), Gain and F are in absolute values, IIP3 and Pdc are in milliwatts and the bandwidth is replaced by BW/fc. This work achieves a better FOM compared with the other works, as can be seen in TABLE I. Fig. 11 Measured NF / Gain / IIP3 at all gain steps TABLE I Summary of Measurements & Performance Comparison [3] [9] [10] This work Technology 0.18ȝm CMOS 0.18ȝm CMOS SiGe BiCMOS 0.18ȝm CMOS Supply (V) 1.8 1.8 2.9 1.8 BW(MHz) 470-860 470-870 473-767 50-860 S11(dB) <-10 <-11 N/A <-10 Gain(dB) 25 16 19 15 NF(dB) 4.5 4.3 2.7 4.2 IIP3(dBm) -4 -1.5 -14 2.6 Power(mW) 16 22 25 10 Area (mm2 ) * 0.52 0.32 N/A 0.29 FOM 0.143 0.072 0.008 1.117 * The PADs are not included. ACKNOWLEDGMENT The authors would like to thank Lee Yang, Xinyu Wang and Xinzhong Duo of SMIC (Shanghai) for chip fabrication and testing support. REFERENCES [1] Youchun Liao, Zhangwen Tang, HaR 0LQ ³$ &026 :LGH%DQG /RZ1RLVH$PSOLILHUZLWK%DOXQEDVHG1RLVH&DQFHOLQJ7HFKQLTXH´ IEEE Asian Solid-State Circuits Conf , 2007. [2] 3DWULFN$QWRQLH HW DO ³$'LUHFW&RQYHUVLRQ5HFHLYHU IRU'9%+´ IEEE ISSCC, 2005. [3] 7DH:RRN.LPHWDO³$G%,,3,PSURYHG/RZ3RZHU&0265) Programmable Gain Amplifier Using Differential Circuit Transconductance Linearization for Various Terrestrial Mobile D-TV $SSOLFDWLRQV´IEEE J. Solid-State Circuits, Vol.41, No.4, April 2006. [4] /DUU\ &RQQHOO HW DO ³$ &026 %URDGEDQG 7XQHU ,&´ IEEE ISSCC ,2002. [5] 6&KHKUD]LHWDO³$*+]:Ldeband CMOS Low Noise Amplifier IRU0XOWL%DQG8VH´IEEE Custom Integrated Circuits Conf, 2005. [6] 6WHSKDQ&%ODDNPHHUHWDO³:LGHEDQG%DOXQ/1$ZLWK6LPXOWDQHRXV Output Balancing, Noise-CanceOLQJDQG'LVWRUWLRQ&DQFHOLQJ´IEEE J. Solid-State Circuits, Vol.43, No.6, June 2008. [7] Behzad Razavi, Design of Analog CMOS Integrated Circuits, U.S.:McGrawHill, 2001. [8] )HGHULFR %UXFFROHUL HW DO ³*HQHUDWLQJ $OO 7ZR0267UDQVLVWRU $PSOLILHUV /HDGV WR 1HZ :LGH%DQG /1$V´ IEEE J. Solid-State Circuits, Vol.36, No.7, July 2001. [9] -LDQKRQJ;LDRHWDO³$+LJK'\QDPLF5DQJH&0269DULDEOH*DLQ $PSOLILHUIRU0RELOH'797XQHU´IEEE J. Solid-State Circuits, Vol.42, No.2, February 2007. [10] 6KLQ¶LFKLUR $]XPDHW DO ³$ 'LJLWDO 7HUUHVWULDO 7HOHYLVLRQ ,6'%7 7XQHUIRU0RELOH$SSOLFDWLRQV´IEEE ISSCC, 2004. 460