9-3 A Wide-band CMOS Low-Noise Amplifier for TV Tuner applications Youchun Liao,Zhangwen Tang*and Hao Min ASIC System State Key Laboratory,Fudan University NO.825 Zhangheng Rd.,Shanghai,201203 China Abstract-In this paper,a wide-band CMOS low-noise ampli- Image-rejected fier (LNA)is presented,in which the thermal noise of the input MOSFET is canceled exploiting a noise-canceling technique. Mixer1 Filter Mixer2 The LNA is designed under input/output impedance matching condition.And its noise figure (NF)and linearity analysis are investigated particularly.The LNA chip is implemented in a 0.25- BPF um 1P5M RF CMOS process.Measurement results show that in This 50-860 MHz,the gain is about 13.4 dB,the NF is from 2.4 dB to 50-860MHz work 02 3.5 dB,and the input-referred third-order intercept point (IIP3) is 3.3 dBm.The chip consumes 30 mW at 2.5-V power supply and the core size is only 0.15mmx0.18mm. PLL I.INTRODUCTION The system-on-a-chip (SOC)RF TV tuners have been Fig.1.A double-conversion TV tuner architecture. widely researched during the last decade.As the first active module in TV tuners,the low-noise amplifier (LNA)needs to possess sufficient gain,low noise figure (NF),high linearity performances coincide with the simulation results,and can and good input/output impedance matching within 50-860 meet the TV tuner applications. MHz frequency range.The traditional inductively degenerated This paper is organized as follows.In Section II,a double- common-source LNA [1]achieves good input impedance conversion TV tuner is introduced,and the LNA specifica- matching and low noise figure via setting the on-chip spiral tions are given.Section III calculates the voltage gain,noise inductor and the gate-source capacitor of input MOSFET to figure and IP3 of a noise-canceling LNA under input/output resonate at the required frequency.However,it does not suit impedance matching,and gives an actual circuit design.Mea- for the tuner applications because the bandwidth is restricted surement results are presented and compared in Section IV. by the LC resonator. Finally,the conclusions are given in Section V. The resistance feedback common-source topology with a II.THE LNA SPECIFICATIONS FOR TV TUNER SYSTEM noise-canceling technique [2]can achieve low noise figure and flat gain within the required bandwidth.And the chip A double-conversion low-IF TV tuner architecture is shown size is greatly reduced because it does not need any inductor.in Fig.1 [3].The RF signal received by the antenna is firstly However,the circuit analysis and parameters calculation in filtered by a band-pass filter(BPF)to acquire 50-860 MHz TV [2]ignored the load impedance,which is always required in signal.Then,a LNA is used to amplify the weak signal and many practical applications and measurements.In this paper,suppress the noise contribution from the following modules. the voltage gain and noise figure are calculated under both Finally,the all-channel signals are converted to 40 MHz IF input and output impedance matching conditions,i.e.,Rs= signals(I and Q)by a double-conversion process,which can R;=500=Ro=RL.Furthermore,the third-order intercept reject the image signal and release the design demands of the point(IP3)calculation is proposed in this paper to give more local oscillator (LO). in-depth comprehension for the interrelationship of all these Normally the LNA performance determines the quality parameters.Calculation results show that the gain,NF and of a TV tuner system.Its gain determines the input signal IP3 are all depending on the feedback resistance only,and amplitude of the following mixer and the noise restraint benefited from a large feedback resistance,except for more capability of the tuner system.The noise figure characterizes power dissipations.Chip measurement shows that the LNA the degeneration of the system signal-to-noise ratio (SNR) because the noise in the LNA directly adds to the system.And This work was supported in part by the Shanghai Science Technology the linearity characterizes the distortion of the input signal. Committee (No.037062019)and the Shanghai Applied Material Funds (No. 0425).China. System simulation shows that the TV tuner in Fig.1 Corresponding author.Email:zwtang@fudan.edu.cn. demands good input/output 50 impedance matching charac- 0-7803-9735-5/06/$20.00©20061EEE 259
A Wide-band CMOS Low-Noise Amplifier for TV Tuner Applications Youchun Liao, Zhangwen Tang* and Hao Min ASIC & System State Key Laboratory, Fudan University NO. 825 Zhangheng Rd., Shanghai, 201203 China Abstract— In this paper, a wide-band CMOS low-noise ampli- fier (LNA) is presented, in which the thermal noise of the input MOSFET is canceled exploiting a noise-canceling technique. The LNA is designed under input/output impedance matching condition. And its noise figure (NF) and linearity analysis are investigated particularly. The LNA chip is implemented in a 0.25- µm 1P5M RF CMOS process. Measurement results show that in 50-860 MHz, the gain is about 13.4 dB, the NF is from 2.4 dB to 3.5 dB, and the input-referred third-order intercept point (IIP3) is 3.3 dBm. The chip consumes 30 mW at 2.5-V power supply and the core size is only 0.15mm×0.18mm. I. INTRODUCTION The system-on-a-chip (SOC) RF TV tuners have been widely researched during the last decade. As the first active module in TV tuners, the low-noise amplifier (LNA) needs to possess sufficient gain, low noise figure (NF), high linearity and good input/output impedance matching within 50-860 MHz frequency range. The traditional inductively degenerated common-source LNA [1] achieves good input impedance matching and low noise figure via setting the on-chip spiral inductor and the gate-source capacitor of input MOSFET to resonate at the required frequency. However, it does not suit for the tuner applications because the bandwidth is restricted by the LC resonator. The resistance feedback common-source topology with a noise-canceling technique [2] can achieve low noise figure and flat gain within the required bandwidth. And the chip size is greatly reduced because it does not need any inductor. However, the circuit analysis and parameters calculation in [2] ignored the load impedance, which is always required in many practical applications and measurements. In this paper, the voltage gain and noise figure are calculated under both input and output impedance matching conditions, i.e., RS = Ri = 50Ω = Ro = RL. Furthermore, the third-order intercept point (IP3) calculation is proposed in this paper to give more in-depth comprehension for the interrelationship of all these parameters. Calculation results show that the gain, NF and IP3 are all depending on the feedback resistance only, and benefited from a large feedback resistance, except for more power dissipations. Chip measurement shows that the LNA This work was supported in part by the Shanghai Science & Technology Committee (No. 037062019) and the Shanghai Applied Material Funds (No. 0425), China. * Corresponding author. Email: zwtang@fudan.edu.cn. PLL BPF LO1 LO2 Mixer1 Mixer2 Image-rejected Filter I Q This work LNA 50-860MHz Fig. 1. A double-conversion TV tuner architecture. performances coincide with the simulation results, and can meet the TV tuner applications. This paper is organized as follows. In Section II, a doubleconversion TV tuner is introduced, and the LNA specifications are given. Section III calculates the voltage gain, noise figure and IP3 of a noise-canceling LNA under input/output impedance matching, and gives an actual circuit design. Measurement results are presented and compared in Section IV. Finally, the conclusions are given in Section V. II. THE LNA SPECIFICATIONS FOR TV TUNER SYSTEM A double-conversion low-IF TV tuner architecture is shown in Fig. 1 [3]. The RF signal received by the antenna is firstly filtered by a band-pass filter (BPF) to acquire 50-860 MHz TV signal. Then, a LNA is used to amplify the weak signal and suppress the noise contribution from the following modules. Finally, the all-channel signals are converted to 40 MHz IF signals (I and Q) by a double-conversion process, which can reject the image signal and release the design demands of the local oscillator (LO). Normally the LNA performance determines the quality of a TV tuner system. Its gain determines the input signal amplitude of the following mixer and the noise restraint capability of the tuner system. The noise figure characterizes the degeneration of the system signal-to-noise ratio (SNR) because the noise in the LNA directly adds to the system. And the linearity characterizes the distortion of the input signal. System simulation shows that the TV tuner in Fig. 1 demands good input/output 50 Ω impedance matching charac- 0-7803-9735-5/06/$20.00 ©2006 IEEE 259 9-3
Substituted with their expressions under the noise-canceling condition,(4)can be calculated as NF=1+ RF +y(2Rs RF)/4+RL (RF/Rs)2Rs Rs Rs (2Rs+1 2 =1+ Rs +RF RE (5) where y is a parameter greater than 1 for submicron MOSFET. B.Linearity Analysis Considering only the first-order deviation of the transcon- ductance from the square law and weakly nonlinear condition, Fig.2.Topology of a LNA exploiting noise-canceling technique. the drain current of Mi and M2 can be given by id1=91,1UA+91,2v7+91,3v月 (6) teristics,gain greater than 12 dB,NF less than 4 dB and IIP3 ia2=92,1vA+92,2w7+92,3v月 greater than 3 dBm within 50-860 MHz frequency range. =n(g1,1vA+g1,2v2+g1,3u) (7) III.PARAMETER ANALYSIS AND CIRCUIT DESIGN where gij means the jthorder distortion of the transcon- ductance of MOSFET Mi (for i 1,2 and j=1,2,3),and A.Noise-canceling Under Input/output Impedance Matching n =g2.j/g1.j =1+RF/Rs.The voltage of node B can be calculated by small-signal analysis as The LNA exploiting a noise-canceling technique [2]is shown in Fig.2.The primary purpose of this circuit is to UB =(1-91.1RF)vA -91.2RFvA-91.3RFUA (8) eliminate the noise contribution of M channel thermal-noise in.,which is a dominating noise source.It flowing through Then the input IP3 of the first stage is Rg and Rs causes two instantaneous noise voltages at nodes B and A with the same phase.Then the voltage of node -91,1RF AIP3.fs- 91,1 (9) A is amplified by a common-source stage M2 and node B 3 91,3RF 91,3 91,3RF is followed by a source-follow stage M3.Consequently,the Here,the first term is the non-linearity contribution of thermal noise of M could be counteracted at the output due the common-source topology M and the latter is that of to the opposite voltage gain sign of M2 and M3. the feedback resistor RF.Normally g1,31V). 9m1 =9m3 =1/Rs (1) Therefore,the voltage at the output can be written as Considering the influence of load impedance RL,the noise- vo =-(ng1.1Rs+91.1RF-1)vA+91.2(nRs RF)vA canceling condition is +91,3(nRs+Rr)u]/2 (10) 9m2=(1+RF/Rs)/Rs (2) And the input IP3 of the total circuit is where Rp is the feedback resistor.Thus,under the impedance AIP3,total ng1,1Rs+91,1RF-1 matching and noise-canceling condition,the voltage gain from 3 91.3(nRs +RF) node A to output is 4 91.1 1 (11) Av Uo/VA=-RF/Rs (3) 391,3 91,3(Rs+2RF) According to [4],the noise figure (or noise factor)can be From (3),(5)and (11),it can be seen that Av,NF and IP3 represented as are only depended on the feedback resistor RF.High gain,low noise figure and high linearity can be achieved simultaneously NF=1+ 吃M十吃Rp十吃，M2,Mg十院RL when Rr is large enough.However,a large RF needs a large (4) A·4kTRs gm2 to meet the noise-canceling condition(2),and this would lead much greater power consumption.The relationships of where话，i,哈，，哈.wa,and疏-are the noise contribu-- Ay,NF,IIP3,Idd(total current)versus the feedback resistor tions at the output of Mi,RF,M2-M3 and RL,respectively. RF are shown in Fig.3. 260
B I RF M1 A B M2 M3 Vdd RS S v o v RL Ri Ro 1 n M, Ci i Co Fig. 2. Topology of a LNA exploiting noise-canceling technique. teristics, gain greater than 12 dB, NF less than 4 dB and IIP3 greater than 3 dBm within 50-860 MHz frequency range. III. PARAMETER ANALYSIS AND CIRCUIT DESIGN A. Noise-canceling Under Input/output Impedance Matching The LNA exploiting a noise-canceling technique [2] is shown in Fig. 2. The primary purpose of this circuit is to eliminate the noise contribution of M1 channel thermal-noise in,M1, which is a dominating noise source. It flowing through RF and RS causes two instantaneous noise voltages at nodes B and A with the same phase. Then the voltage of node A is amplified by a common-source stage M2 and node B is followed by a source-follow stage M3. Consequently, the thermal noise of M1 could be counteracted at the output due to the opposite voltage gain sign of M2 and M3. The input and output impedances can be calculated as Ri = 1/gm1 and Ro = 1/gm3, respectively. And the load impedance is RL = RS = 50 Ω. Then the impedance matching condition is gm1 = gm3 = 1/RS (1) Considering the influence of load impedance RL, the noisecanceling condition is gm2 = (1 + RF /RS)/RS (2) where RF is the feedback resistor. Thus, under the impedance matching and noise-canceling condition, the voltage gain from node A to output is AV = vo/vA = −RF /RS (3) According to [4] , the noise figure (or noise factor) can be represented as NF = 1 + v 2 n,M1 + v 2 n,RF + v 2 n,M2,M3 + v 2 n,RL A2 V · 4kT RS (4) where v 2 n,M1 , v 2 n,RF , v 2 n,M2,M3 and v 2 n,RL are the noise contributions at the output of M1, RF , M2-M3 and RL, respectively. Substituted with their expressions under the noise-canceling condition, (4) can be calculated as NF = 1 + RF + γ(2RS + RF )/4 + RL (RF /RS) 2RS = 1 + RS RF + γ 4 RS RF 2RS RF + 1 + RS RF 2 (5) where γ is a parameter greater than 1 for submicron MOSFET. B. Linearity Analysis Considering only the first-order deviation of the transconductance from the square law and weakly nonlinear condition, the drain current of M1 and M2 can be given by id1 = g1,1vA + g1,2v 2 A + g1,3v 3 A (6) id2 = g2,1vA + g2,2v 2 A + g2,3v 3 A = n g1,1vA + g1,2v 2 A + g1,3v 3 A (7) where gi,j means the j th-order distortion of the transconductance of MOSFET Mi (for i = 1, 2 and j = 1, 2, 3), and n = g2,j/g1,j = 1 + RF /RS. The voltage of node B can be calculated by small-signal analysis as vB = (1 − g1,1RF )vA − g1,2RF v 2 A − g1,3RF v 3 A (8) Then the input IP3 of the first stage is AIP 3,fs = s 4 3 1 − g1,1RF g1,3RF = s 4 3 g1,1 g1,3 − 1 g1,3RF (9) Here, the first term is the non-linearity contribution of the common-source topology M1 and the latter is that of the feedback resistor RF . Normally g1,3 1V). Therefore, the voltage at the output can be written as vo = − (ng1,1RS + g1,1RF − 1)vA + g1,2(nRS + RF )v 2 A +g1,3(nRS + RF )v 3 A /2 (10) And the input IP3 of the total circuit is AIP 3,total = s 4 3 ng1,1RS + g1,1RF − 1 g1,3(nRS + RF ) = s 4 3 g1,1 g1,3 − 1 g1,3(RS + 2RF ) (11) From (3), (5) and (11), it can be seen that AV , NF and IP3 are only depended on the feedback resistor RF . High gain, low noise figure and high linearity can be achieved simultaneously when RF is large enough. However, a large RF needs a large gm2 to meet the noise-canceling condition (2), and this would lead much greater power consumption. The relationships of AV , NF, IIP3, Idd (total current) versus the feedback resistor RF are shown in Fig. 3. 260
20 80 60 Idd 10 40 NE 100 200 300 400 500 (a) (b) Feedback resistor R(2) Fig.5.Photograph of (a)Chip (b)PCB. Fig.3.Relationship of Av,NF,IIP,Idd vs.RF. 20 S21 10 611 -20 30 200 400 600 800 1000 Frequency(MHz) Fig.6.Measured S-parameters. of M2 can be calculated from the noise-canceling condition (2),which is gm2 =gm3(1+RF/Rs)=0.18 S.However, Fig.4.Schematic of the designed noise-canceling LNA. for the power dissipation restriction,gm2 is actually chosen to be 0.08 S in this design.Consequently,the voltage gain will decrease and the NF will deteriorate due to the deviation of C.LNA Design the noise-canceling condition. Figure 4 is the schematic of a noise-canceling LNA.A PMOS MiB is exploited to increase the transconductance of IV.CHIP IMPLEMENTATION AND MEASUREMENT input stage via a current-reuse technique.And a capacitor C The chip is implemented in a 0.25-um RF CMOS process. is used to reduce the influence of power supply fluctuating Figure 5 is the photograph of the chip and test PCB.The core and to filter out the noise from current-mirror M-M5.The size is only 0.15mmx0.18mm.And it draws 12 mA from a second stage is AC-coupled to the first stage via a high-pass 2.5-V power supply.The ground Vss is connected via four topology C2-R2.A cascode transistor M2B is used to increase bonding-wires to reduce the parasitic inductance. the inverse isolation (S12).Its DC bias voltage is provided by The measured S-parameters are shown in Fig.6.In the the branch M6-Ms.And C3 is used to filter out the noise from frequency range of 50 MHz-1 GHz,the S21 (voltage gain)is this branch.M3 and M2B are deep n-well NMOS devices, about 13.4 dB with a 3-dB bandwidth of 1 MHz-1.3 GHz, whose substrates are connected to each source to eliminate the input matching S11 is from-16 dB to-9 dB,the output body effect. matching S22 is below-10 dB,and the inverse isolation S12 It is easy to obtain the devices parameters from the previous is less than-19 dB. analysis.The transconductances of M and M3 are determined The simulated and measured NF are shown in Fig.7.The by the impedance matching condition (1).which is gmiA+ measured NF is less than 3.5 dB from 50 MHz to 1 GHz,with 9m1B=gm3 =0.02S.The feedback resistor Re is chosen to a minimum NF of 2.4 dB at 350 MHz.The NF increases at be 400 n considering the trade-offs between the gain,noise low frequency because of the MOSFET flick noise,and degen- figure,linearity and power consumption.The transconductance erates at high frequency due to the input parasitic capacitances 261
100 200 300 400 500 0 5 10 15 20 Feedback resistor RF (Ω) NF(dB),IIP3(dBm) and Av(dB) NF IIP3 Idd Av 100 200 300 400 500 0 20 40 60 80 Total current(mA) Fig. 3. Relationship of Av, NF, IIP, Idd vs. RF . RF M1A RS S v A B M2A M3 Vdd M1B M4 M5 Ci Co C2 R2 M2B M6 M7 M8 C1 C3 Rx Vss o v RL Fig. 4. Schematic of the designed noise-canceling LNA. C. LNA Design Figure 4 is the schematic of a noise-canceling LNA. A PMOS M1B is exploited to increase the transconductance of input stage via a current-reuse technique. And a capacitor C1 is used to reduce the influence of power supply fluctuating and to filter out the noise from current-mirror M4-M5. The second stage is AC-coupled to the first stage via a high-pass topology C2-R2. A cascode transistor M2B is used to increase the inverse isolation (S12). Its DC bias voltage is provided by the branch M6-M8. And C3 is used to filter out the noise from this branch. M3 and M2B are deep n-well NMOS devices, whose substrates are connected to each source to eliminate body effect. It is easy to obtain the devices parameters from the previous analysis. The transconductances of M1 and M3 are determined by the impedance matching condition (1), which is gm1A + gm1B = gm3 = 0.02S. The feedback resistor RF is chosen to be 400 Ω considering the trade-offs between the gain, noise figure, linearity and power consumption. The transconductance Vi Vo Vdd Vss Vss Vss Vss Idc (a) RF_in LNA RF_out Vss Vdd Rx (b) Fig. 5. Photograph of (a) Chip (b) PCB. 0 200 400 600 800 1000 −40 −30 −20 −10 0 10 20 Frequency(MHz) S−parameters(dB) S21 S22 S11 S12 Fig. 6. Measured S-parameters. of M2 can be calculated from the noise-canceling condition (2), which is gm2 = gm3(1 + RF /RS) = 0.18 S. However, for the power dissipation restriction, gm2 is actually chosen to be 0.08 S in this design. Consequently, the voltage gain will decrease and the NF will deteriorate due to the deviation of the noise-canceling condition. IV. CHIP IMPLEMENTATION AND MEASUREMENT The chip is implemented in a 0.25-µm RF CMOS process. Figure 5 is the photograph of the chip and test PCB. The core size is only 0.15mm×0.18mm. And it draws 12 mA from a 2.5-V power supply. The ground VSS is connected via four bonding-wires to reduce the parasitic inductance. The measured S-parameters are shown in Fig. 6. In the frequency range of 50 MHz–1 GHz, the S21 (voltage gain) is about 13.4 dB with a 3-dB bandwidth of 1 MHz–1.3 GHz, the input matching S11 is from –16 dB to –9 dB, the output matching S22 is below –10 dB, and the inverse isolation S12 is less than –19 dB. The simulated and measured NF are shown in Fig. 7. The measured NF is less than 3.5 dB from 50 MHz to 1 GHz, with a minimum NF of 2.4 dB at 350 MHz. The NF increases at low frequency because of the MOSFET flick noise, and degenerates at high frequency due to the input parasitic capacitances 261
20 (wgp) IIP3-3.3dBm -simulation -e-simulation measurement measurement 200 400 600 800 1000 25 20 -15 -10 -5 0 5 Frequency(MHz) Input power(dBm) Fig.7. Simulated and measured NF. Fig.8. Simulated and measured IIP3 TABLE I SUMMARY OF MEASUREMENT RESULTS AND PERFORMANCE COMPARISON 2] [5 [6 刀 This Work Process 0.25um CMOS 0.5um CMOS 0.18um CMOS 0.18um CMOS 0.25um CMOS Frequency 150-2000MHz 50-700MHz 54-880MHz 470-860MHz 50-860MHz S11(dB) -8 N/A -10 N/A 9 S21(dB) 13.7 14.8 10-22 10 13.4 S12(dB) .36 -41 NIA NIA -19 S22(dB) -12 N/A N/A N/A -10 NF(dB) 1.8-2.2 2.3-3.3 4.2-6 5.7 2.43.5 IdBCP(dBm) 9 N/A N/A N/A -6.7 IIP3(dBm) 0 -4.7 4.3-5@11dB 10 3.3 Power 14mA×2.5V 3.3mA×3V 23mA×1.8V 2.9mA×1.8V 12mA×2.5V Chip size(mm2) 0.3×0.25 1.0×1.2 1.19×0.59 N/A 0.15×0.18 which cause the noise-canceling condition deviating. TV tuner applications The third-order intercept point is measured with a two-tone ACKNOWLEDGMENT test at 500 MHz and 502 MHz,as shown in Fig.8.The measured IIP3 is 3.3 dBm and varies slightly with the two- The authors would like to thank Fuxiao Li,Baowen Qiao, tone frequencies.The input-referred 1dB compression point Zhenyu Zhu,Yuhong Ye,and Haiyang Hu for their help in (1dBCP)measures to be-6.7 dBm at 500 MHz. chip package and measurement,and thank Yan He,Lei Lu, Table I gives the measurement results compared with re- Zhenyu Yang,and Liming Jin for many helpful discussions. cently published works.It can be seen that the S-parameters REFERENCES performance of this work are approaching to the others.and the [1]D.K.Shaeffer and T.H.Lee,"A 1.5-V.1.5-GHz CMOS low noise IIP3 increases 3.3 dB and power consumption decreases 2 mA amplifier,"IEEE J.Solid-Stae Circuits,vol.32,pp.745-759,May.1997 compared to [2].Furthermore,the presented LNA occupies the [2]F.Bruccoleri,E.A.M.Klumperink,and B.Nauta,"Wide-band CMOS low-noise amplifier exploiting thermal noise canceling,"IEEE /Solid. smallest chip size. State Circuits,vol.39,pp.275-281,Feb.2004. [3]M.Dawkins,A.P.Burdett,and N.Cowley,"A single-chip tuner for DVB- V.CONCLUSION T:"IEEE J.Solid-State Circuits.vol38.pp.1307-1317.Aug.2003. [4]B.Razavi.RF Microelectronics.New Jersey:Prentice-Hall.1998 In this paper,a wide-band CMOS LNA exploiting a noise- [5]J.Janssens.J.Crols,and M.Steyaert,"A 10mW inductorless broadband canceling technique is designed and measured,and the voltage CMOS low noise amplifier for 900MHz wireless communications,"in gain,noise figure and linearity of the LNA is analyzed in Proc.of IEEE CICC,1998.pp.75-78 [6]S.Lou and H.Luong."A wideband CMOS variable-gain low-noise detail.The circuit design process and parameter calculation amplifier for cable TV tuners,"in IEEE Asian Solid-State Circuits Conf. method are also presented.Measurement results show that the (ASSCC,2005,Pp.181-184 presented LNA achieves good input/output 50 impedance [7]T.W.Kim and B.Kim,"A 13-dB IIP3 improved low-power CMOS RF programmable gain amplifier using differential circuit transconductance matching,high gain,low noise figure and high linearity in 50- linearization for various terrestrial mobile D-TV applications,"IEEE. 860 MHz frequency range,and meets the requirements of the Solid-State Circuits.vol.41.pp.945-953.Apr.2006. 262
0 200 400 600 800 1000 1 1.5 2 2.5 3 3.5 4 Frequency(MHz) NF(dB) simulation measurement Fig. 7. Simulated and measured NF. −30 −25 −20 −15 −10 −5 0 5 −80 −60 −40 −20 0 20 Input power(dBm) Output power(dBm) IIP3=3.3dBm simulation measurement Fig. 8. Simulated and measured IIP3. TABLE I SUMMARY OF MEASUREMENT RESULTS AND PERFORMANCE COMPARISON [2] [5] [6] [7] This Work Process 0.25µm CMOS 0.5µm CMOS 0.18µm CMOS 0.18µm CMOS 0.25µm CMOS Frequency 150-2000 MHz 50-700 MHz 54-880 MHz 470-860 MHz 50-860 MHz S11(dB) -8 N/A -10 N/A -9 S21(dB) 13.7 14.8 10-22 10 13.4 S12(dB) -36 -41 N/A N/A -19 S22(dB) -12 N/A N/A N/A -10 NF(dB) 1.8-2.2 2.3-3.3 4.2-6 5.7 2.4-3.5 1dBCP(dBm) -9 N/A N/A N/A -6.7 IIP3(dBm) 0 -4.7 4.3-5 @11dB 10 3.3 Power 14mA×2.5V 3.3mA×3V 23mA×1.8V 2.9mA×1.8V 12mA×2.5V Chip size(mm2 ) 0.3×0.25 1.0×1.2 1.19×0.59 N/A 0.15×0.18 which cause the noise-canceling condition deviating. The third-order intercept point is measured with a two-tone test at 500 MHz and 502 MHz, as shown in Fig. 8. The measured IIP3 is 3.3 dBm and varies slightly with the twotone frequencies. The input-referred 1dB compression point (1dBCP) measures to be –6.7 dBm at 500 MHz. Table I gives the measurement results compared with recently published works. It can be seen that the S-parameters performance of this work are approaching to the others, and the IIP3 increases 3.3 dB and power consumption decreases 2 mA compared to [2]. Furthermore, the presented LNA occupies the smallest chip size. V. CONCLUSION In this paper, a wide-band CMOS LNA exploiting a noisecanceling technique is designed and measured, and the voltage gain, noise figure and linearity of the LNA is analyzed in detail. The circuit design process and parameter calculation method are also presented. Measurement results show that the presented LNA achieves good input/output 50 Ω impedance matching, high gain, low noise figure and high linearity in 50- 860 MHz frequency range, and meets the requirements of the TV tuner applications. ACKNOWLEDGMENT The authors would like to thank Fuxiao Li, Baowen Qiao, Zhenyu Zhu, Yuhong Ye, and Haiyang Hu for their help in chip package and measurement, and thank Yan He, Lei Lu, Zhenyu Yang, and Liming Jin for many helpful discussions. REFERENCES [1] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-Stae Circuits, vol. 32, pp.745-759, May. 1997. [2] F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, “Wide-band CMOS low-noise amplifier exploiting thermal noise canceling,” IEEE J. SolidState Circuits, vol. 39, pp. 275-281, Feb. 2004. [3] M. Dawkins, A. P. Burdett, and N. Cowley, “A single-chip tuner for DVBT,” IEEE J. Solid-State Circuits, vol. 38, pp. 1307-1317, Aug. 2003. [4] B. Razavi, RF Microelectronics. New Jersey: Prentice-Hall, 1998 [5] J. Janssens, J. Crols, and M. Steyaert, “A 10mW inductorless broadband CMOS low noise amplifier for 900MHz wireless communications,” in Proc. of IEEE CICC, 1998, pp. 75-78 [6] S. Lou and H. Luong, “A wideband CMOS variable-gain low-noise amplifier for cable TV tuners,” in IEEE Asian Solid-State Circuits Conf. (ASSCC), 2005, pp. 181-184 [7] T. W. Kim and B. Kim, “A 13-dB IIP3 improved low-power CMOS RF programmable gain amplifier using differential circuit transconductance linearization for various terrestrial mobile D-TV applications,” IEEE J. Solid-State Circuits, vol. 41, pp. 945-953, Apr. 2006. 262
