IEEE 2009 Custom Intergrated Circuits Conference(CICC) A Sub-0.75RMs-Phase-Error Differentially-Tuned Fractional-N Synthesizer with On-Chip LDO Regulator and Analog-Enhanced AFC Technique Lei Lu,Lingbu Meng,Liang Zou,Hao Min and Zhangwen Tang ASIC System State Key Laboratory,Fudan University,Shanghai 201203,China Abstract-This paper presents a low-phase-error wideband (s) Koo=△fsJ△V fractional-N frequency synthesizer.Differential tuning is Charge 00p described and a level shift circuit is proposed to obtain Pump symmetrical tuning range.On-chip LDO regulator is designed to VCO improve the power supply rejection for VCO.A voltage monitor is used to enhance the digital AFC technique to overcome the Divide temperature variation.The synthesizer was implemented in a 0.18-um CMOS process with a 16-mA supply current and a lcpZF(S)K.co 1.47-mm2 die area.The measured in-band phase noise is less than open-loop gain三 -97 dBe/Hz at a 10-kHz frequency offset and the integrated phase (a) error is less than 0.75gMs.The measured reference spur is less than-71 dBe and the locking time is smaller than 20 us. 0.5le ZF(s) Loop Kico-Afc/A(VEp-Ven) I.INTRODUCTION Charge Filter Pump Fractional-N frequency synthesizers with wide tuning Loop range are essential for digital TV tuners.To meet the Filter 0.5/ requirements of the tuners,synthesizer should also have low ZF(s) phase noise,low phase error,constant loop bandwidth as well as automatic frequency calibration(AFC)techniques [1]. For the synthesizer loops,either single-ended or differen- DSM gain= [0.5/cp-(-0.5/p)]ZH(s)K.c tial architectures can be adopted.Fig.I shows the block 2TN diagram of a typical A fractional-N frequency synthesizer. (b) The differences in circuit blocks between single-ended and differential configurations are that differential charge pumps Fig.1.Block diagram of a typical AS fractional-N frequency synthesizer.(a) Single-ended configuration.(b)Differentially-tuned configuration. with common-mode feedback,two loop filters and differentially-uned VCOs are used in the latter.To obtain the lead to current mismatch in most cases when common-mode same loop characteristics as the single-ended form,half the voltage is not Vpp/2.This paper proposes a level shift circuit to charge pump current lep should be assigned to each side in the acquire a symmetrical tuning range using symmetrical differential form.Besides that,twice area of the loop filter and inversion mode MOS varactors(I-MOS).A low-noise high differentially-tuned varactors in LC VCO are needed. power-supply-rejection(PSR)low-dropout (LDO)regulator is Compared with the single-ended form,the differential form designed to bias VCO power supply.Due to the temperature has other advantages.The loop filter area can be reduced to a drift,the frequency variation may exceed 30 MHz for the half when two big capacitors in series are combined into one. multi-band VCO of this synthesizer,so a voltage monitor is Differential tuning characteristics can suppress the common- adopted to guarantee the robustness of the AFC technique. mode noise from power supply,substrate and control lines. Differential charge pump can obtain better linearity,which II.SYNTHESIZER ARCHITECTURE may effectively avoid the degradation of in-band phase noise The detail block diagram of the presented 1.2-2.1-GHz generated from quantization noise of A modulator going differentially-tuned A fractional-N frequency synthesizer is through analog blocks with large nonlinearity. shown in Fig.2.The big capacitor Cl is reduced to a half To achieve a symmetrical tuning range in the differential compared with the single-ended form and the loop filter is form,the common-mode voltage of VCO outputs is sensed to fully integrated.The phase-frequency detector (PFD)uses a decide the common-mode voltage of charge pump differential conventional tri-state deadzone free circuit.The charge pump outputs [2].However,non-symmetrical accumulation mode has rail-to-rail outputs and common-mode feedback with MOS varactors(A-MOS)are used.In addition,the common- excellent current match.Level shift circuits are added before mode voltage of charge pump outputs also varies,which may the control voltages of the VCO to compensate the difference between common-mode of charge pump outputs and VCO Corresponding author.Email:zwtang@fudan.edu.cn. outputs as well as the threshold voltage of the I-MOS varactors. 978-1-4244-4072-6/09/S25.00©20091EEE 5-41 53
A Sub-0.75°RMS-Phase-Error Differentially-Tuned Fractional-N Synthesizer with On-Chip LDO Regulator and Analog-Enhanced AFC Technique Lei Lu, Lingbu Meng, Liang Zou, Hao Min and Zhangwen Tang* ASIC & System State Key Laboratory, Fudan University, Shanghai 201203, China Abstract—This paper presents a low-phase-error wideband fractional-N frequency synthesizer. Differential tuning is described and a level shift circuit is proposed to obtain symmetrical tuning range. On-chip LDO regulator is designed to improve the power supply rejection for VCO. A voltage monitor is used to enhance the digital AFC technique to overcome the temperature variation. The synthesizer was implemented in a 0.18-μm CMOS process with a 16-mA supply current and a 1.47-mm2 die area. The measured in-band phase noise is less than –97 dBc/Hz at a 10-kHz frequency offset and the integrated phase error is less than 0.75°RMS. The measured reference spur is less than –71 dBc and the locking time is smaller than 20 μs. I. INTRODUCTION Fractional-N frequency synthesizers with wide tuning range are essential for digital TV tuners. To meet the requirements of the tuners, synthesizer should also have low phase noise, low phase error, constant loop bandwidth as well as automatic frequency calibration (AFC) techniques [1]. For the synthesizer loops, either single-ended or differential architectures can be adopted. Fig. 1 shows the block diagram of a typical ΔΣ fractional-N frequency synthesizer. The differences in circuit blocks between single-ended and differential configurations are that differential charge pumps with common-mode feedback, two loop filters and differentially-uned VCOs are used in the latter. To obtain the same loop characteristics as the single-ended form, half the charge pump current Icp should be assigned to each side in the differential form. Besides that, twice area of the loop filter and differentially-tuned varactors in LC VCO are needed. Compared with the single-ended form, the differential form has other advantages. The loop filter area can be reduced to a half when two big capacitors in series are combined into one. Differential tuning characteristics can suppress the commonmode noise from power supply, substrate and control lines. Differential charge pump can obtain better linearity, which may effectively avoid the degradation of in-band phase noise generated from quantization noise of ΔΣ modulator going through analog blocks with large nonlinearity. To achieve a symmetrical tuning range in the differential form, the common-mode voltage of VCO outputs is sensed to decide the common-mode voltage of charge pump differential outputs [2]. However, non-symmetrical accumulation mode MOS varactors (A-MOS) are used. In addition, the commonmode voltage of charge pump outputs also varies, which may * Corresponding author. Email: zwtang@fudan.edu.cn. lead to current mismatch in most cases when common-mode voltage is not VDD/2. This paper proposes a level shift circuit to acquire a symmetrical tuning range using symmetrical inversion mode MOS varactors (I-MOS). A low-noise high power-supply-rejection (PSR) low-dropout (LDO) regulator is designed to bias VCO power supply. Due to the temperature drift, the frequency variation may exceed 30 MHz for the multi-band VCO of this synthesizer, so a voltage monitor is adopted to guarantee the robustness of the AFC technique. II. SYNTHESIZER ARCHITECTURE The detail block diagram of the presented 1.2–2.1-GHz differentially-tuned ΔΣ fractional-N frequency synthesizer is shown in Fig. 2. The big capacitor C1 is reduced to a half compared with the single-ended form and the loop filter is fully integrated. The phase-frequency detector (PFD) uses a conventional tri-state deadzone free circuit. The charge pump has rail-to-rail outputs and common-mode feedback with excellent current match. Level shift circuits are added before the control voltages of the VCO to compensate the difference between common-mode of charge pump outputs and VCO outputs as well as the threshold voltage of the I-MOS varactors. (a) (b) Fig. 1. Block diagram of a typical ΔΣ fractional-N frequency synthesizer. (a) Single-ended configuration. (b) Differentially-tuned configuration. 53 IEEE 2009 Custom Intergrated Circuits Conference (CICC) 978-1-4244-4072-6/09/$25.00 ©2009 IEEE 5-4-1
Digital AFC Band Shif V=1.5V O load with buff DSM 00 Fig.2.Detail block-level diagram of the 1.2-2.1-GHz differentially tuned AE fractional-N frequency synthesizer with level shift of differential control voltages. Vi(Vp+Vo)2 60 楼 60 e2 V (b) (c) VF(Vis+V)2 Fig.4.Schematic of the low-noise high-PSR LDO regulator for VCO power supply.(a)Bode diagram.(b)Simulated output noise and power supply rejection. maximal tuning gain in the tuning curve is the point with (a) maximal slope in the C-Vcurve.A symmetrical tuning range 并楼 means the point when Vep-Vn-0 has the maximal tuning gain. T-VE+ For A-MOS varactors,if the common-mode voltage Vocm of VCO outputs is equal to the common-mode voltage Veem of control voltages,the tuning range could be symmetrical [2]. However,for I-MOS varactors,even if the two common-mode Veon-VintVan Ve voltages are the same,the tuning range is still not symmetrical C↑Van+Vinch-lVapl-V.on since Ihn and IIthpl do not have the same values. To compensate both the common-mode difference and threshold voltage,level shift circuits are added before the control voltages directly connected to VCO.Control voltage IVsl-IVael Ve Ven goes through a voltage drop of Vasn firstly,and then sees a (b) threshold voltage rise to Vocm.If after the two voltage level Fig.3.C-V curves of I-MOS varactors.(a)Conversional circuit which ha shifts,Ven is equal to Vocm,then the C-V curve shifts toward asymmetrical tuning curves.(b)Proposed method to obtain symmetrical the right and becomes symmetrical.It is also like that for Vep. tuning curves where V2. Therefore,we can obtain Vasn and IVgsp as following Digital AFC counts the VCO clock directly and selects one of f'n=a+('.m-'.em) the 256 sub-bands of VCO whose center frequency is closest (1) to the target frequency.After AFC finishes,a voltage monitor Vpp=Vop-(Vscm-Vacm) will always detect control voltages and ensure the robustness of the loop.Multi-modulus divider adopts programmed P/S By adjusting the sizes of the level shift transistors with counters and 4/4.5 prescaler to obtain the wide division ratio certain bias current,the gate-source voltage can be changed to meet the relationship in (1).The extra current consumption is and reduce the quantization noise from A modulator by 6 dB. Adaptive bandwidth control is used to obtain constant loop very small compared to the VCO circuit.But the bias current can not be too small,since noise issues should be considered. bandwidth across the whole frequency range [3]. III.CIRCUIT IMPLEMENTATION B.On-Chip LDO Regulator On-chip LDO regulator for VCO should have low output A.Level Shift noise and high PSR.The schematic of the regulator is shown I-MOS varactors have p-type and n-type in process,so they in Fig.4.Diode-connected transistor M is inserted to sense are the best choice in differentially-tuned LC VCOs.Fig.3 the supply variation and conduct it to the gate of the pass shows the C-V curves of I-MOS varactors.The point with transistor,thus the gate-source voltage can be constant due to 5-4-2 54
Digital AFC counts the VCO clock directly and selects one of the 256 sub-bands of VCO whose center frequency is closest to the target frequency. After AFC finishes, a voltage monitor will always detect control voltages and ensure the robustness of the loop. Multi-modulus divider adopts programmed P/S counters and 4/4.5 prescaler to obtain the wide division ratio and reduce the quantization noise from ΔΣ modulator by 6 dB. Adaptive bandwidth control is used to obtain constant loop bandwidth across the whole frequency range [3]. III. CIRCUIT IMPLEMENTATION A. Level Shift I-MOS varactors have p-type and n-type in process, so they are the best choice in differentially-tuned LC VCOs. Fig. 3 shows the C–V curves of I-MOS varactors. The point with maximal tuning gain in the tuning curve is the point with maximal slope in the C–V curve. A symmetrical tuning range means the point when Vcp–Vcn=0 has the maximal tuning gain. For A-MOS varactors, if the common-mode voltage Vocm of VCO outputs is equal to the common-mode voltage Vccm of control voltages, the tuning range could be symmetrical [2]. However, for I-MOS varactors, even if the two common-mode voltages are the same, the tuning range is still not symmetrical since Vthn and |Vthp| do not have the same values. To compensate both the common-mode difference and threshold voltage, level shift circuits are added before the control voltages directly connected to VCO. Control voltage Vcn goes through a voltage drop of Vgsn firstly, and then sees a threshold voltage rise to Vocm. If after the two voltage level shifts, Vcn is equal to Vocm, then the C–V curve shifts toward the right and becomes symmetrical. It is also like that for Vcp. Therefore, we can obtain Vgsn and |Vgsp| as following ( ) ( ) gsn thn ccm ocm gsp thp ccm ocm . ⎧ =+ − ⎪ ⎨ =− − ⎪⎩ VV VV V V VV (1) By adjusting the sizes of the level shift transistors with certain bias current, the gate-source voltage can be changed to meet the relationship in (1). The extra current consumption is very small compared to the VCO circuit. But the bias current can not be too small, since noise issues should be considered. B. On-Chip LDO Regulator On-chip LDO regulator for VCO should have low output noise and high PSR. The schematic of the regulator is shown in Fig. 4. Diode-connected transistor M1 is inserted to sense the supply variation and conduct it to the gate of the pass transistor, thus the gate-source voltage can be constant due to Differential LPF PFD Digital AFC fref R1 R1 C1/2 C2 C2 R3 R3 C3 C3 Vref s1 s1 s2 s2 Differential CP up upb dn dnb Level Shift Vref s1 s1 Vcp Vcn Vcpo Vcno Divider DSM N fvco 8 Band Shift VCO LDO fdiv Voltage Monitor Level Shift Fig. 2. Detail block-level diagram of the 1.2–2.1-GHz differentially tuned ΔΣ fractional-N frequency synthesizer with level shift of differential control voltages. (a) Vcn Cn Vocm–Vthn+Vgsn Vcp Cp Vocm+|Vthp|–|Vgsp| Vocm–Vthn+Vgsn=Vccm Vocm+|Vthp|–|Vgsp|=Vccm (b) Fig. 3. C–V curves of I-MOS varactors. (a) Conversional circuit which has asymmetrical tuning curves. (b) Proposed method to obtain symmetrical tuning curves where Vccm=(Vcp+Vcn)/2. Vin=1.5V add one zero to improve stability sense VDD variation to improve PSRR Pass Transistor folded cascode CL 15mA VDD cancelled VCO load with buffer M1 (a) -20 0 20 40 60 80 100 Gain (dB) 1e2 1e3 1e4 1e5 1e6 1e7 1e8 1e9 -60 -20 20 60 100 140 180 Frequency (Hz) Phase (Deg) Loop UGB=176MHz Phase Margin=62.5° (b) 1e2 1e3 1e4 1e5 1e6 1e7 1e8 -180 -170 -160 -150 -140 Frequency (Hz) Output Noise (dB20[V2/Hz]) 1e2 1e3 1e4 1e5 1e6 1e7 1e8 -100 -80 -60 -40 -20 0 Power Supply Rejection (dB) (c) Fig. 4. Schematic of the low-noise high-PSR LDO regulator for VCO power supply. (a) Bode diagram. (b) Simulated output noise and power supply rejection. 5-4-2 54
Digital AFC start 47mm 8”Comp7 Wait 80us N FC+DSM Shift VCO band N AFC finished Digital AFC:Voltage Monitor (a) AFC Fig.6.Die micrograph VLinear Range (AV 1.66 ch (b) A工O 1.65 Fig.5.Diagram of the analog-enhanced AFC technique.(a)Flow chart.(b) The voltage monitor to detect the control voltages. 1.64 the cancellation [4].The RC connection after the folded- 1.63 cascode amplifier is to introduce a zero within the GBW to improve the loop stability.The unit-gain bandwidth is 176 MHz and the phase margin is 62.5.The input voltage 1.5 V is 1.62 generated from a low noise bandgap output.The simulated 8 ""m output noise at 100 Hz frequency is less than -140 1.61 一Symmetrica dB20[V2/Hz]and reaches -170 dB20[V2/Hz]at 1 MHz -1.5 -0.50 0.5 1.5 frequency.This will have no effect on VCO phase noise.The Differential Control Voltages (V) simulated PSR is-97 dB at DC,-80 dB at 100 kHz frequency and-60 dB at 1 MHz frequency.This will effectively suppress Fig.7.Measured VCO tuning curves in part. the noise from power supply lines. Ph/Raf-d 0.0 C.Analog-Enhanced Digital AFC Technique 0的 Division-ratio-based digital AFC technique is used to select 0的 48.5313小 the sub-band of VCO [3].However,the temperature drift of . 70C may lead to the oscillation frequency variation of 30 0.的 MHz,which exceeds the linear tuning range of one tuning 0.的 0国 curve.The analog-enhanced AFC technique is shown in Fig.5. 前的 A voltage monitor including four comparators and one NAND 第.国 gate is introduced to detect the differential control voltages 1000 After 80 us when AFC finishes,the voltage monitor starts 1100 working.80 us is to ensure the synthesizer has been locked. 20月 When the synthesizer looses lock due to the temperature drift, 300 the control voltages exceed Veh or Vel,then NAND gate outputs 1400 "1"to restart digital AFC.This method is similar to [5],but 150.0 1600 different from that.This voltage monitor restarts AFC and does not adjust the sub-band directly.Because the AFC time is very 70 short,restarting AFC can always ensure the operation of VCO Fig.8.Measured phase noise at the oscillation frequency of 1.6135GHz. closest to the center frequency of the sub-band with adding only a little more time including loop filter and PADs IV.EXPERIMENTAL RESULTS The measured tuning range is from 1.2 GHz to 2.1 GHz. Fig.7 shows some measured VCO tuning curves.The The differentially-tuned AE fractional-N frequency synthe- measured fractional-N phase noise at the oscillation frequency sizer was implemented in a 0.18-um CMOS process with a of 1.6135 GHz is shown in Fig.8.The in-band phase noise is current consumption of 16 mA from a 1.8-V supply.The die less than -96 dBc/Hz and the out-of-band phase noise at a micrograph is shown in Fig.6.The die area is 1.47 mm2, 1-MHz frequency offset is less than-123 dBc/Hz,which is 5-4-3 55
the cancellation [4]. The RC connection after the foldedcascode amplifier is to introduce a zero within the GBW to improve the loop stability. The unit-gain bandwidth is 176 MHz and the phase margin is 62.5°. The input voltage 1.5 V is generated from a low noise bandgap output. The simulated output noise at 100 Hz frequency is less than –140 dB20[V2 /Hz] and reaches –170 dB20[V2 /Hz] at 1 MHz frequency. This will have no effect on VCO phase noise. The simulated PSR is –97 dB at DC, –80 dB at 100 kHz frequency and –60 dB at 1 MHz frequency. This will effectively suppress the noise from power supply lines. C. Analog-Enhanced Digital AFC Technique Division-ratio-based digital AFC technique is used to select the sub-band of VCO [3]. However, the temperature drift of 70℃ may lead to the oscillation frequency variation of 30 MHz, which exceeds the linear tuning range of one tuning curve. The analog-enhanced AFC technique is shown in Fig. 5. A voltage monitor including four comparators and one NAND gate is introduced to detect the differential control voltages. After 80 μs when AFC finishes, the voltage monitor starts working. 80 μs is to ensure the synthesizer has been locked. When the synthesizer looses lock due to the temperature drift, the control voltages exceed Vch or Vcl, then NAND gate outputs “1” to restart digital AFC. This method is similar to [5], but different from that. This voltage monitor restarts AFC and does not adjust the sub-band directly. Because the AFC time is very short, restarting AFC can always ensure the operation of VCO closest to the center frequency of the sub-band with adding only a little more time. IV. EXPERIMENTAL RESULTS The differentially-tuned ΔΣ fractional-N frequency synthesizer was implemented in a 0.18-μm CMOS process with a current consumption of 16 mA from a 1.8-V supply. The die micrograph is shown in Fig. 6. The die area is 1.47 mm2 , including loop filter and PADs. The measured tuning range is from 1.2 GHz to 2.1 GHz. Fig. 7 shows some measured VCO tuning curves. The measured fractional-N phase noise at the oscillation frequency of 1.6135 GHz is shown in Fig. 8. The in-band phase noise is less than –96 dBc/Hz and the out-of-band phase noise at a 1-MHz frequency offset is less than –123 dBc/Hz, which is (a) (b) Fig. 5. Diagram of the analog-enhanced AFC technique. (a) Flow chart. (b) The voltage monitor to detect the control voltages. 1mm Fig. 6. Die micrograph. Fig. 8. Measured phase noise at the oscillation frequency of 1.6135GHz. -1.5 -1 -0.5 0 0.5 1 1.5 1.61 1.62 1.63 1.64 1.65 1.66 Differential Control Voltages (V) Oscillation Frequency (GHz) Fig. 7. Measured VCO tuning curves in part. 5-4-3 55
-70 1.65 80 LDO regulator off 90 1.55 100 1.5 110 LDO regulator on L.527 1.526 120 1.4 525 130 1574 1.35 1015.202530 140 -AFC- PLL 159e2 10 20 30 1e3 1e4 1e5 1e6 1e7 Time (us) Frequency Offset(Hz) Fig.11.Measured total locking time with AFC time of 6.4 us. Fig.9.Comparisons of measured phase noise with and without LDO regulator at the output frequency of 1813.5 MHz Table i performance summary 0.18-um CMOS 160 Technology 0.9 Die Area 1.47mm Supply Voltage 1.8 V(VCO with 1.5V) 140 0.8 Current 16 mA Reference Clock 25 MHz 120 0.7 Output Frequency 1.2 GHz~2.1 GHz Phase Noise Integer-N -100@10kHz,-127@1MHz (dBc/Hz) Fractional-N -96@10kHz-123@1MHz 100 0.6 Phase Error (100 Hz Integer-N <0.5°Rws Fracitonal-N ~40 MHz) Fractional-N <0.75s 80 0.5 Reference Spur <-71dBc 00 Integer-N Locking Time 204s 60 power supply.A voltage monitor is introduced to detect control 40 0.3 1.21.31.41.51.61.71.81.922.1 voltages to guarantee the robustness of the digital AFC Output Frequency (GHz) technique.The measured integrated phase error is less than Fig.10.Measured 3-dB closed-loop bandwidth and integrated RMS phase 0.75RMs and the in-band phase noise is less than-96 dBc/Hz error from 100 Hz to 40 MHz in integer-N and fractional-N mode in fractional-N mode.The measured reference spur is less than -71 dBc and the locking time is less than 20 us.The chip consumes a 16-mA current with a die area of 1.47 mm2. deteriorated by high-pass quantization noise of Ax modulator. The measured phase noise with and without on-chip LDO is ACKNOWLEDGMENT shown in Fig.9.Compared with using on-chip LDO regulator. The work was partly supported by the National 863 the phase noise is worsened by 5 dB at a 60-kHz frequency Program of China Grant No.2007AA01Z282 and the National offset when using off-chip power supply. Science Funding of China Grant No.60876019. Fig.10 shows the measured loop bandwidth and integrated phase error.The measured loop bandwidth is from 125 kHz to REFERENCES 155 kHz with the variation less than 10.7%.The integrated [1]L.Lu,J.Chen,L.Yuan,H.Min,and Z.Tang,"An 18 mW 1.175-to-2 phase error from 100 Hz to 40 MHz is less than 0.75RMs in GHz Frequency Synthesizer with A Constant Loop Bandwidth for fractional-N mode and less than 0.5RMs in integer-N mode. DVB-T Tuners,"IEEE Trans.Microw.Theory Tech..vol.57,No.4,pp. The measured reference spur at 25 MHz frequency offset is 928-937,Apr.2009. less than -71 dBc across the whole frequency range.The [2]B.Soltanian et al.,"An ultra compact differentially tuned 6 GHz CMOS locking time is shown in Fig.11.The total locking time is less LC VCO with dynamic common-mode feedback,"in Proc.IEEE C/CC, than 20 us,with 6.4 us for AFC time.Table I shows a Sept.2006,Pp.671-674. [3]L.Lu,Z.Gong,Y.Liao,H.Min,and Z.Tang,"A 975-to-1960 MHz, performance summary of the measured results. Fast-Locking Fractional-N Synthesizer with Adaptive Bandwidth Control V.CONCLUSION and 4/4.5 Prescaler for Digital TV Tuners,"ISSCC Dig.Tech.Papers, Feb.2009,pp.396-397 A 1.2-2.1-GHz differentially-tuned Ax fractional-N [4]S.K.Hoon et al.,"A low noise,high power supply rejection low dropout frequency synthesizer was implemented in a 0.18-um CMOS regulator for wireless system-on-chip applications,"in Proc.IEEECICC, process.Level shift circuits are proposed to obtain Sept.2005,pp.759-762 [5]T.-H.Lin and W.J.Kaiser,"A 900-MHz 2.5-mA CMOS frequency symmetrical tuning range.On-chip LDO regulators are synthesizer with an automatic SC tuning loop,"IEEE J.Solid-State employed to effectively suppress the noise from off-chip Circuits,vol.36,pp.424-431,Mar.2001. 5-4-4 56
deteriorated by high-pass quantization noise of ΔΣ modulator. The measured phase noise with and without on-chip LDO is shown in Fig. 9. Compared with using on-chip LDO regulator, the phase noise is worsened by 5 dB at a 60-kHz frequency offset when using off-chip power supply. Fig. 10 shows the measured loop bandwidth and integrated phase error. The measured loop bandwidth is from 125 kHz to 155 kHz with the variation less than 10.7%. The integrated phase error from 100 Hz to 40 MHz is less than 0.75°RMS in fractional-N mode and less than 0.5°RMS in integer-N mode. The measured reference spur at 25 MHz frequency offset is less than –71 dBc across the whole frequency range. The locking time is shown in Fig. 11. The total locking time is less than 20 μs, with 6.4 μs for AFC time. Table I shows a performance summary of the measured results. V. CONCLUSION A 1.2–2.1-GHz differentially-tuned ΔΣ fractional-N frequency synthesizer was implemented in a 0.18-μm CMOS process. Level shift circuits are proposed to obtain symmetrical tuning range. On-chip LDO regulators are employed to effectively suppress the noise from off-chip power supply. A voltage monitor is introduced to detect control voltages to guarantee the robustness of the digital AFC technique. The measured integrated phase error is less than 0.75°RMS and the in-band phase noise is less than –96 dBc/Hz in fractional-N mode. The measured reference spur is less than –71 dBc and the locking time is less than 20 μs. The chip consumes a 16-mA current with a die area of 1.47 mm2 . ACKNOWLEDGMENT The work was partly supported by the National 863 Program of China Grant No. 2007AA01Z282 and the National Science Funding of China Grant No. 60876019. REFERENCES [1] L. Lu, J. Chen, L. Yuan, H. Min, and Z. Tang, “An 18 mW 1.175-to-2 GHz Frequency Synthesizer with A Constant Loop Bandwidth for DVB-T Tuners,” IEEE Trans. Microw. Theory Tech., vol. 57, No.4, pp. 928–937, Apr. 2009. [2] B. Soltanian et al., “An ultra compact differentially tuned 6 GHz CMOS LC VCO with dynamic common-mode feedback,” in Proc. IEEE CICC, Sept. 2006, pp. 671–674. [3] L. Lu, Z. Gong, Y. Liao, H. Min, and Z. Tang, “A 975-to-1960 MHz, Fast-Locking Fractional-N Synthesizer with Adaptive Bandwidth Control and 4/4.5 Prescaler for Digital TV Tuners,” ISSCC Dig. Tech. Papers, Feb. 2009, pp. 396-397. [4] S. K. Hoon et al., “A low noise, high power supply rejection low dropout regulator for wireless system-on-chip applications,” in Proc. IEEE CICC, Sept. 2005, pp. 759-762. [5] T.-H. Lin and W. J. Kaiser, “A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop,” IEEE J. Solid-State Circuits, vol. 36, pp. 424-431, Mar. 2001. 1e2 1e3 1e4 1e5 1e6 1e7 -150 -140 -130 -120 -110 -100 -90 -80 -70 Frequency Offset (Hz) Phase Noise (dBc/Hz) Fig. 9. Comparisons of measured phase noise with and without LDO regulator at the output frequency of 1813.5 MHz. 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 40 60 80 100 120 140 160 Output Frequency (GHz) Loop Bandwidth (kHz) 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Phase Error (Deg) Fracitonal-N Integer-N Fig. 10. Measured 3-dB closed-loop bandwidth and integrated RMS phase error from 100 Hz to 40 MHz in integer-N and fractional-N mode. Table I. PERFORMANCE SUMMARY Technology 0.18-μm CMOS Die Area 1.47 mm2 Supply Voltage 1.8 V (VCO with 1.5 V) Current 16 mA Reference Clock 25 MHz Output Frequency 1.2 GHz ~ 2.1 GHz Phase Noise Integer-N –100 @ 10 kHz; –127 @ 1MHz (dBc/Hz) Fractional-N –96 @ 10 kHz; –123 @ 1MHz Phase Error (100 Hz Integer-N < 0.5°RMS ~ 40 MHz) Fractional-N < 0.75°RMS Reference Spur < -71 dBc Locking Time 20 μs 0 10 20 30 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 Time (μs) Frequency (GHz) 10 15 20 25 30 1.524 1.525 1.526 1.527 Fig. 11. Measured total locking time with AFC time of 6.4 μs. 5-4-4 56
