HIGH-PERFORMANCE ALL-DIGITAL QUADRATURE FREQUENCY SYNTHESIZER/MIXER Zhangwen Tang Student Member,IEEE,Yang Wang,and Hao Min,Member,IEEE ASIC System State Key Laboratory,Fudan University Shanghai.200433.P.R.China ABSTRACT In this paper,a high-performance all-digital quadrature fre- quency synthesizer/mixer applied to QAM modulation and demodulation is presented,which synthesizes 12-bit sine and cosine waveforms with a spectral purity of -83.0dB.The synthesizer covers a bandwidth from dc to 100 MHz in steps of 0.0466Hz with a corresponding switching speed of 5 ns at 200MHz clock frequency.Also,it is capable of frequency, (a) phase and quadrature amplitude modulation.In this design,an efficient ROM look-up table method for calculating the sine and cosine function is employed,and a compression algorithm that only calculates one-eighth sine function is adopted to reduce the volume of ROM.By taking advantage of sine and cosine symmetries,the size of the ROM look-up table is only 1/51 of that of traditional one.The resulting chip fabricated in 0.35um five-level metal CMOS process has a complexity of ) about 20,000 gates with core area of 2.00X 1.00 mm Fig.1.Tunable QAM Modulator(a),and Demodulator (b) 1.INTRODUCTION ephme-leled L traditional high-frequency mixers are implemented in analog mixer technology.However,thanks to the CMOS technology progress,digital techniques are today capable of handling high frequency synthesizer/mixer.High performance quadrature frequency synthesizers/mixers play an extremely important role in modern digital com- munications.They offer many advantages including fast switching response,fine frequency resolution,large bandwidth,and good spectral purity.Meanwhile,in the Fig.2.Architecture of Direct Digital Frequency Synthesizer past few years,improvements in digital-to-analog con- The sine and cosine function generator is a ROM look-up verter (DAC)technology have made quadrature fre- table that stores the sine and cosine samples.Frequency quency synthesizer/mixer feasible at RF frequency.So resolution can be doubled by each addition of one bit to they become widespread in frequency agile communi- the word length of the phase accumulator. cations system such as CDMA digital cellular telephones, spread spectrum wireless LAN's,HDTV.For example,a For a given Frequency Control Word(FCW),clocking frequency tunable quadrature amplitude modulation (QAM)mo- ()and phase accumulator word length (L),the output dulator and demodulator are shown in Fig.1. The architecture (Fig.2)of direct digital frequency syn- frequency (of the synthesizer is given by thesizer(DDFS)used in this design was originally intro- duced by Tierney,Rader,and Gold [1].An overflowing -&·FCm (1) L-bit accumulator is utilized to generate the phase argu- 24 ment of the sine and cosine function generator.Each overflow of the phase argument represents one period of and the frequency resolution is given by a sine and cosine wave.The input Frequency Control Word (FCW)of the phase accumulator controls the frequency of the generated sine and cosine waveform. 2 (2) I-1 0-7803-75246/02/S17.00⊙2002IEEE
HIGH-PERFORMANCE ALL-DIGITAL QUADRATURE FREQUENCY SYNTHESIZER/MIXER Zhangwen Tang Student Member,IEEE, Yang Wang, and Hao Min, Member,IEEE ASIC & System State Key Laboratory, Fudan University Shanghai, 200433, P. R. China ABSTRACT In this paper, a high-performance all-digital quadrature frequency synthesizer/mixer applied to QAM modulation and demodulation is presented, which synthesizes 12-bit sine and cosine waveforms with a spectral purity of –83.0dB. The synthesizer covers a bandwidth from dc to 100 MHz in steps of 0.0466Hz with a corresponding switching speed of 5 ns at 200MHz clock frequency. Also, it is capable of frequency, phase and quadrature amplitude modulation. In this design, an efficient ROM look-up table method for calculating the sine and cosine function is employed, and a compression algorithm that only calculates one-eighth sine function is adopted to reduce the volume of ROM. By taking advantage of sine and cosine symmetries, the size of the ROM look-up table is only 1/51 of that of traditional one. The resulting chip fabricated in 0.35um five-level metal CMOS process has a complexity of about 20,000 gates with core area of 2.00ᱢ1.00 mm2 . 1. INTRODUCTION RADITIONAL high-bandwidth frequency synthesizers are based on phase-locked loop (PLL), and traditional high-frequency mixers are implemented in analog mixer technology. However, thanks to the CMOS technology progress, digital techniques are today capable of handling high frequency synthesizer/mixer. High performance quadrature frequency synthesizers/mixers play an extremely important role in modern digital communications. They offer many advantages including fast switching response, fine frequency resolution, large bandwidth, and good spectral purity. Meanwhile, in the past few years, improvements in digital-to-analog converter (DAC) technology have made quadrature frequency synthesizer/mixer feasible at RF frequency. So they become widespread in frequency agile communications system such as CDMA digital cellular telephones, spread spectrum wireless LAN’s, HDTV. For example, a tunable quadrature amplitude modulation (QAM) modulator and demodulator are shown in Fig. 1. The architecture (Fig. 2) of direct digital frequency synthesizer (DDFS) used in this design was originally introduced by Tierney, Rader, and Gold [1]. An overflowing L-bit accumulator is utilized to generate the phase argument of the sine and cosine function generator. Each overflow of the phase argument represents one period of a sine and cosine wave. The input Frequency Control Word (FCW) of the phase accumulator controls the frequency of the generated sine and cosine waveform. The sine and cosine function generator is a ROM look-up table that stores the sine and cosine samples. Frequency resolution can be doubled by each addition of one bit to the word length of the phase accumulator. For a given Frequency Control Word (FCW), clocking frequency ( clk f ), and phase accumulator word length (L), the output frequency ( out f ) of the synthesizer is given by 2 clk out L f FCW f (1) and the frequency resolution is given by 2 clk L f ' f (2) T Serial to Parallel Symbol Generati on Square-Root Nyquist Filter Square-Root Nyquist Filter Interpolation Filter Interpolation Filter D/A Quadrature Oscillator sinZn cosZn Baseband IF Q I A/D Quadrature Oscillator IF Decimation Filter Decimation Filter Square-Root Nyquist Filter Square-Root Nyquist Filter Q I Baseband (a) (b) sinZn cosZn Fig. 1. Tunable QAM Modulator (a), and Demodulator (b) R E G Phase ACCU. (N bits) N bit Reg Computation ROM DAC LPF N bits N M L FCW N ) 2 sin( 2 N I n S Fref I(n) digital analog Fig. 2. Architecture of Direct Digital Frequency Synthesizer 0-7803-7523-8/02/$17.00 ©2002 IEEE I-1 0-7803-7524-6/02/$17.00 ©2002 IEEE
ND MSE FCW MCU DDFS CORE COM FO UD (X Fig.3.Architecture of Quadrature Frequency Synthesizer/Mixer Fig.4.Optimized Architecture of DDFS In this paper,the word length of the phase accumulator is 32 bits and the maximum clock frequency is 200MHz.Thus the minimum frequency resolution is 0.0466Hz.The switching speed between two frequencies is one clock cycle,5ns. ROM 2 -COM Fig.3 is the architecture of the quadrature frequency syn- 32bt LUT thesizer/mixer.which consists of four main modules:direct digital frequency synthesizer,modified Booth multiplier with Wallace adder tree,anti-SINC FIR filter with CSD coefficients 0 and a simple microcontroller.Direct digital frequency synthesizer employs one-eighth sine waveform compression Fig.5.Modulation Capabilities algorithms to achieve high frequency resolution and high bandwidth.12-bit x 12-bit multipliers adopt modified Booth and that of the fine ROM is 4 bits.Thus,214X12 sine samples encode and Wal-lace adder tree to improve the speed of are compressed into 28 X 11 coarse samples and 2%X 4 fine multiplication.An anti-SINC FIR filter is used to samples resulting in a compression ratio of 51:1.Thus,by compensate the loss of D/A converter's frequency response taking advantage of sine and cosine symmetries,the size before D/A output.The coefficients of this filter are Canonic of the look-up table ROM is only 1/51 of that of tradi- Signed-Digit(CSD)code,which utilize minimum shift-adder to tional one. complete multiplication operation avoiding many of complicated multiplications.The internal control word registers (such as 2.1.2 Quadrature Ouputs FCW,Phase offset)are wrote or read through a simple For a design where quadrature outputs are desired,a simple microcontroller to reduce the number of 1/O pads of control method would be to store both sine and cosine samples from 0 to signals /2.This would double the size of the ROM look-up table Instead,one could take advantage of one-eighth wave symmetry 2.ARCHITECTURE DESIGN ISSUES of a sine and cosine waveform,since cosine samples from 0 to /4 are the same as sine samples from /4 to n/2.Similarly,sine 2.1 Direct Digital Frequency Synthesizer sample from 0 to n/4 are the same as cosine sample from i/4 to /2.Hence,one need only store sine and cosine samples from 0 This design is based on the optimized architecture of Nicholas to /4.The third MSB of the phase accumulator can be used to and Samueli[2],Zhangwen Tang and Han Min[3].The optimi- select between these samples. zation of direct digital frequency synthesizer (DDFS)involves trading off the finite word lengths and sine computation methods 2.1.3 Modulation Capabilities against the sine-wave spectral purity and maximum clock rate. The modulation capabilities [5]of this chip include frequency Fig.4 shows a block diagram of DDFS in this design,which modulation,phase modulation,quadrature amplitude modulation, employs eighth sine waveform compression algorithms to and frequency mixing.Frequency modulation is performed decrease the volume of the ROM look-up table. directly by modulating the Frequency Control Word.Phase 2.1.1 1/8 Sine Waveform Compression Technique modulation is obtained by adding a phase offset to the phase accumulator output before addressing the ROM look-up table. As we all known,arbitrary functions can be partitioned into Furthermore,this chip accepts only an 8-bit word for phase coarse and fine ROM samples [2],[3].[4].Let A+B+C be total modulation.Finally,quadrature amplitude modulation and number of bits of the phase address,with A being the most frequency mixing are obtained by adding a complex multiplier significant bits,B the next most significant bits,and C the least block to the sine and cosine outputs of the quadrature DDFS as significant bits.Then using this algorithm,the coarse ROM shown in Fig.5.The word length for I and Q rails for amplitude would have 24+B samples,and the fine ROM would have 24+c modulation are 12 bits each.The complex multiplier block is samples.According to the conclusion in [4],A=4,B=4 and C=4 made up of two 12-bit X 12-bit multipliers. is optimal.The output word length of the coarse ROM is 11 bits, I-2
In this paper, the word length of the phase accumulator is 32 bits and the maximum clock frequency is 200MHz. Thus the minimum frequency resolution is 0.0466Hz. The switching speed between two frequencies is one clock cycle, 5ns. Fig. 3 is the architecture of the quadrature frequency synthesizer/mixer, which consists of four main modules: direct digital frequency synthesizer, modified Booth multiplier with Wallace adder tree, anti-SINC FIR filter with CSD coefficients and a simple microcontroller. Direct digital frequency synthesizer employs one-eighth sine waveform compression algorithms to achieve high frequency resolution and high bandwidth. 12-bitᱢ12-bit multipliers adopt modified Booth encode and Wal-lace adder tree to improve the speed of multiplication. An anti-SINC FIR filter is used to compensate the loss of D/A converter’s frequency response before D/A output. The coefficients of this filter are Canonic Signed-Digit (CSD) code, which utilize minimum shift-adder to complete multiplication operation avoiding many of complicated multiplications. The internal control word registers (such as FCW, Phase offset) are wrote or read through a simple microcontroller to reduce the number of I/O pads of control signals. 2. ARCHITECTURE DESIGN ISSUES 2.1 Direct Digital Frequency Synthesizer This design is based on the optimized architecture of Nicholas and Samueli[2], Zhangwen Tang and Han Min[3]. The optimization of direct digital frequency synthesizer (DDFS) involves trading off the finite word lengths and sine computation methods against the sine-wave spectral purity and maximum clock rate. Fig. 4 shows a block diagram of DDFS in this design, which employs eighth sine waveform compression algorithms to decrease the volume of the ROM look-up table. 2.1.1 1/8 Sine Waveform Compression Technique As we all known, arbitrary functions can be partitioned into coarse and fine ROM samples [2], [3], [4]. Let A+B+C be total number of bits of the phase address, with A being the most significant bits, B the next most significant bits, and C the least significant bits. Then using this algorithm, the coarse ROM would have 2A+B samples, and the fine ROM would have 2A+C samples. According to the conclusion in [4], A=4, B=4 and C=4 is optimal. The output word length of the coarse ROM is 11 bits, and that of the fine ROM is 4 bits. Thus, 214h12 sine samples are compressed into 28h11 coarse samples and 28h4 fine samples resulting in a compression ratio of 51:1. Thus, by taking advantage of sine and cosine symmetries, the size of the look-up table ROM is only 1/51 of that of traditional one. 2.1.2 Quadrature Ouputs For a design where quadrature outputs are desired, a simple method would be to store both sine and cosine samples from 0 to ʌ/2. This would double the size of the ROM look-up table. Instead, one could take advantage of one-eighth wave symmetry of a sine and cosine waveform, since cosine samples from 0 to ʌ/4 are the same as sine samples from ʌ/4 to ʌ/2. Similarly, sine sample from 0 to ʌ/4 are the same as cosine sample from ʌ/4 to ʌ/2. Hence, one need only store sine and cosine samples from 0 to ʌ/4. The third MSB of the phase accumulator can be used to select between these samples. 2.1.3 Modulation Capabilities The modulation capabilities [5] of this chip include frequency modulation, phase modulation, quadrature amplitude modulation, and frequency mixing. Frequency modulation is performed directly by modulating the Frequency Control Word. Phase modulation is obtained by adding a phase offset to the phase accumulator output before addressing the ROM look-up table. Furthermore, this chip accepts only an 8-bit word for phase modulation. Finally, quadrature amplitude modulation and frequency mixing are obtained by adding a complex multiplier block to the sine and cosine outputs of the quadrature DDFS as shown in Fig. 5. The word length for I and Q rails for amplitude modulation are 12 bits each. The complex multiplier block is made up of two 12-bith12-bit multipliers. MCU DDFS CORE X sin(x) 8 12 12 I Q D WR_clk WR_en FQ_UD 32 FCW 8 Phase cosZn sinZn 12 12 23 23 12 12 COM clk Fig. 3. Architecture of Quadrature Frequency Synthesizer/Mixer 2:2 MUX 2:2 MUX 2:2 MUX Coarse ROMA Coarse ROMB Fine ROMA Fine ROMB + + 2:2 MUX 2ND MSB 1's compl 1's compl MSB 12 12 sin cos MSB 2ND MSB 12 12 11 11 4 4 11 11 12 12 8 8 8 8 2ND MSB 3RD MSB Q D clk D Flip-Flop FCW ADDER Phase Registers clk carry in Modification 32 14 Fig. 4. Optimized Architecture of DDFS Phase ACCU. (32 bit) ROM LUT Phase Offset Phase Modulation FCW Frequency Modulation 32 14 8 32 12 12 SIN COS 12 12 I Q COM 23 23 Fig. 5. Modulation Capabilities I-2
Wallace Adder Tree 2s 起中 Fig.6.12bitsX 12bits Multiplier with Modified Booth Algorithm and Wallace Adder Tree 2.2 12-bitX 12-bit Multiplier Fig.7.(a)SINC Amplitude Distortion, (b)Transpose-form Realization of 11-tap Anti-SINC FIR The structure of 12-bit X 12-bit multiplier is shown in Fig.6. Filter This multiplier uses a parallel structure with Booth's algorithm and Wallace's adder tree.The multiplier consists of the following three blocks:Booth block,adder array block and final adder.By applying the modified Booth algorithm [6],the number of partial products is halved.Since this multiplier performs 12-bit multiplications,6 partial products are generated. ⑧ By employing the Wallace adder tree and a 4:2 compressor adder Fig.8.(a)Simple Microcontroller, [7].only two addition stages are needed in order to add 6 partial (b)Timing Diagram of Read and Write products.This addition is performed in the form of a tournament by using the Wallace adder tree method.The addition of the and a pipeline register.Therefore,this FIR filter can work in partial products uses the 4:2 compressor adder,which can sum high clock rate. up four partial products concurrently.The 4:2 compressor adder can add without propagating the carry to a higher position,and it 2.4 Simple microcontroller generates a 23-bit sum and carry. In order to reduce the number of pads of controlling signals,a Finally,the 23-bit sum and carry is added with the 23-bit carry simple microcontroller (Fig.8a)is used to write and read 32-bit propagation.This adder consists of a 4-bit carry look-ahead Frequency Control Words and 8-bit phase offset.The timing adder and an 8-bit carry select adder to propagate the carry at diagram of this simple microcontroller is shown in Fig.8b.The high speed. 40-bit controlling registers are wrote and read in 5 clock cycles through 8-bit bidirectional data bus.WR clk,WR en and 2.3 Anti-SINC FIR filter FQ UD are clock signal,enable signal and update signal separately. Digital-to-analog (D/A)converters introduce an inherent sin(x)/x amplitude distortion (Fig.7a)into the spectrum of signals being 3.CIRCUIT AND LAYOUT DESIGN converted.For many systems,the performance degradation due ISSUES to this distortion is not acceptable and compensation is required. A digital compensation filter prior to D/A conversion has the The whole chip was designed using VHDL language in Active-HDL4.2 environment.Top-Down design metho- advantage that the x/sin(x)(Anti-SINC)compensation is accurate dology was adopted to design the whole chip in RTL for all sampling rates design stage.In logic synthesis stage,Bottom-Up design In this paper an 11-tap x/sin(x)linear-phase FIR digital filter [8] methodology was employed in Synopsys design compiler environment.Each module of the whole chip was syn- is used,as shown in Fig.7b.A transpose-form structure with 2- thesized in Europractice 0.35-um CMOS standard cell digit CSD coefficients to each tap is chosen for the realization of library.Top circuit was shown in Fig.9a.And each the compensation filter.Therefore,each tap multiplier is imple- module was placed&routed in Cadence Silicon Ensemble. mented with at most a single adder/subtracter and some hard- The floorplan of whole silicon chip is Fig.9b.The resulting wired shifts.A carry save addition(CSA)scheme is used for the chip fabricated in 0.35um five-level metal CMOS process has a implementation of the adders to avoid carry propagation.And complexity of about 20,000 gates with core area of 2.00x 1.00 pipeline registers were inserted after every adder stage.Con- mm.The photomicrograph of the packaged chip is shown sequently,the critical path consists of only a single full-adder in Fig.10. I-3
2.2 12-bith12-bit Multiplier The structure of 12-bith12-bit multiplier is shown in Fig. 6. This multiplier uses a parallel structure with Booth’s algorithm and Wallace’s adder tree. The multiplier consists of the following three blocks: Booth block, adder array block and final adder. By applying the modified Booth algorithm [6], the number of partial products is halved. Since this multiplier performs 12-bit multiplications, 6 partial products are generated. By employing the Wallace adder tree and a 4:2 compressor adder [7], only two addition stages are needed in order to add 6 partial products. This addition is performed in the form of a tournament by using the Wallace adder tree method. The addition of the partial products uses the 4:2 compressor adder, which can sum up four partial products concurrently. The 4:2 compressor adder can add without propagating the carry to a higher position, and it generates a 23-bit sum and carry. Finally, the 23-bit sum and carry is added with the 23-bit carry propagation. This adder consists of a 4-bit carry look-ahead adder and an 8-bit carry select adder to propagate the carry at high speed. 2.3 Anti-SINC FIR filter Digital-to-analog (D/A) converters introduce an inherent sin(x)/x amplitude distortion (Fig.7a) into the spectrum of signals being converted. For many systems, the performance degradation due to this distortion is not acceptable and compensation is required. A digital compensation filter prior to D/A conversion has the advantage that the x/sin(x) (Anti-SINC) compensation is accurate for all sampling rates. In this paper an 11-tap x/sin(x) linear-phase FIR digital filter [8] is used, as shown in Fig. 7b. A transpose-form structure with 2- digit CSD coefficients to each tap is chosen for the realization of the compensation filter. Therefore, each tap multiplier is implemented with at most a single adder/subtracter and some hardwired shifts. A carry save addition (CSA) scheme is used for the implementation of the adders to avoid carry propagation. And pipeline registers were inserted after every adder stage. Consequently, the critical path consists of only a single full-adder and a pipeline register. Therefore, this FIR filter can work in high clock rate. 2.4 Simple microcontroller In order to reduce the number of pads of controlling signals, a simple microcontroller (Fig. 8a) is used to write and read 32-bit Frequency Control Words and 8-bit phase offset. The timing diagram of this simple microcontroller is shown in Fig. 8b. The 40-bit controlling registers are wrote and read in 5 clock cycles through 8-bit bidirectional data bus. WR_clk, WR_en and FQ_UD are clock signal, enable signal and update signal separately. 3. CIRCUIT AND LAYOUT DESIGN ISSUES The whole chip was designed using VHDL language in Active-HDL4.2 environment. Top-Down design methodology was adopted to design the whole chip in RTL design stage. In logic synthesis stage, Bottom-Up design methodology was employed in Synopsys design compiler environment. Each module of the whole chip was synthesized in Europractice 0.35-um CMOS standard cell library. Top circuit was shown in Fig.9a. And each module was placed&routed in Cadence Silicon Ensemble. The floorplan of whole silicon chip is Fig.9b. The resulting chip fabricated in 0.35um five-level metal CMOS process has a complexity of about 20,000 gates with core area of 2.00ᱢ1.00 mm2 . The photomicrograph of the packaged chip is shown in Fig. 10. Partial products generator BOOTH Encoder C.A. A C.A. B C.A.C Carry Select Adder &CLA Multiplier(12 bits) Multiplicand(12 bits) Booth Block Partial Product Adder Array Block Final Adder Product (23 bits) Compressor Adder I1I2I3I4 C S Cout Cin I1I2I3I4 C S Cout Cin I1I2I3I4 C S Cout Cin I1I2I3I4 C S Cout Cin I1I2I3I4 C S Cout Cin I1I2I3I4 C S Cout Cin C I1I2I3I4 C S Cout Cin I1I2I3I4 C S Cout Cin I1I2I3I4 C S Cout Cin Partial Products Partial Products Full Adder Full Adder I1 I2 I3 I4 Cout Cin S C A A B B Cin Cin Cout Cout Sum Sum Wallace Adder Tree 4:2 Compression Adder 0 Fig. 6. 12bitsh12bits Multiplier with Modified Booth Algorithm and Wallace Adder Tree D D D D D h(10) h(9) h(8) h(7) D D D D D D D D D D + -1/512 1/256 h(0) -1/128 1/64 1/256 -1/512 CV Xin Xin Yout Yout FA FA FA 2D 2D 2D FA FA FA 2D 2D 2D D D Xin[0] D Xin[1] Xin[2] Sin[0] Cin[0] Sin[1] Cin[1] Sin[2] Cin[2] Sout[2] Cout[2] Sout[1] Cout[1] Sout[0] Cout[0] CSA CPA .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .. CV:Compensation Vector CSA:Carry Save Adder CPA:Carry Propagation Adder (a) (b) Fig. 7. (a) SINC Amplitude Distortion, (b) Transpose-form Realization of 11-tap Anti-SINC FIR Filter FQ_UD MCU D 8 WR_clk WR_en FCW 32 8 Phase W1 W2 W3 W4 W5 OLD NEW OLD NEW D[7:0] WR_clk WR_en FQ_UD FCW[31:0] Phase[7:0] D[7:0] W1 W2 W3 W4 W5 WR_clk WR_en (a) (b) Fig. 8. (a) Simple Microcontroller, (b) Timing Diagram of Read and Write I-3
MCU DDFS Booth Booth Multiplie Anti-SINC Filter SINC ADDER ⊙ b) Fig.9(a)Top Circuit of the Whole Chip, DDES CORE (b)Floorplan of Layout 4.SIMULATION AND MEASUREMENT To verify the chip functionality,cosimulations with a Fig.10.Photomicrograph of the Packaged Chip synthesizable testbench were run in software and hardware environments.We built a test board with two FPGA chips (Xilinx SpartanII and Virtex),one for generating stimulus signals,another for sampling the outputting signals.It should be mentioned that due to parasitic effects on the PCB,we were not able to conduct 50 the measurements up to 200MHz.Instead,we used a lower master clock of 100MHz.The 50-MHz mode was 83.0 measured completely.Fig.11 was the FFT diagram of outputting signal.In Fig.11,the worst-case spurious 100 component is at-83.0 dB 5.CONCLUSION 0.050.10.150.20.25030.350.4 049 FREQUENCY NORMALIZED TO SAMPLERATE An implementation of a high-performance all-digital quadrature frequency synthesizer/mixer is presented.It Fig.11.FFT Diagram of Outputting Signal has been designed that operates at 200MHz and synthesized-83.0 dBc spectrally pure sine and cosine waveforms.By taking advantage of sine and cosine dBc spurious performance,"IEEE J.Solid-State Circuits, symmetries,the size of the ROM look-up table is only vol.26,pp.1959-1969,Dec.1991. 1/51 of that of traditional one.The chip is capable of [3]Zhangwen Tang and Hao Min,"A direct digital frequency frequency,phase and quadrature amplitude modulation.The synthesizer Implemented with FPGA,"Transaction of resulting chip fabricated in 0.35um five level metal CMOS Microelectronics,vol.5,Oct.2001. process has a complexity of 20,000 gates with core area of 2.00 [4]H.T.Nicholas,III,H.Samueli,and B.Kim,"The ×1.00mm2 optimization of direct digital frequency synthesizer performance in the presence of finite word length effects," 6.ACKNOWLEDGMENT In Proc.42d Annu.Frequency Cont.Symp.USER-ACOM, Mar.1988,pp.357-363. [5]L.K.Tan and H.Samueli,"A 200MHz Quadrature Digital The authors wish to thank Wenhong Li for providing the help in Synthesizer/Mixer in 0.8 um CMOS,"IEEE J.Solid-State using EDA tools and Yawei Guo,Cheng Chen for DRC and LVS Circuits,vol.30,pp.193-200,Mar.1993. of the layout of the whole chip. [6 M.Nagamatsu et al.,"A 15-ns 32 X 32-bit CMOS Multiplier with an improved paralled structure,"/EEEJ. 7.REFERENCES Solid-State Circuits,vol 25,pp.494-497,April 1990. [7]J.Mori et al.,"A 10-ns 54X54-b Parallel Structured Full [1]C.Tierney,M.Rader,and B.Gold,"A digital frequency Array Multiplier with 0.5 um CMOS Technology,"IEEEJ synthesizer,"IEEE Trans.Audio Electroacoust,vol.AU-19, Solid-State Circuits,vol 26,pp.600-606,April 1991. pp.48-57,1971. [8]T.Lin,and H.Samueli,"A 200-MHz CMOS x/sin(x) [2]H.T.Nicholas,III and H.Samueli,"A 150 MHz direct Digital Filter for Compensating D/A Converter Frequency digital frequency synthesizer in 1.25-um CMOS with-90 Response Distortion,"IEEE J.Solid-State Circuits,vol 26. pp.1278-1285,Sep.1991. I-4
4. SIMULATION AND MEASUREMENT To verify the chip functionality, cosimulations with a synthesizable testbench were run in software and hardware environments. We built a test board with two FPGA chips (Xilinx SpartanII and Virtex), one for generating stimulus signals, another for sampling the outputting signals. It should be mentioned that due to parasitic effects on the PCB, we were not able to conduct the measurements up to 200MHz. Instead, we used a lower master clock of 100MHz. The 50-MHz mode was measured completely. Fig.11 was the FFT diagram of outputting signal. In Fig.11, the worst-case spurious component is at –83.0 dB. 5. CONCLUSION An implementation of a high-performance all-digital quadrature frequency synthesizer/mixer is presented. It has been designed that operates at 200MHz and synthesized –83.0 dBc spectrally pure sine and cosine waveforms. By taking advantage of sine and cosine symmetries, the size of the ROM look-up table is only 1/51 of that of traditional one. The chip is capable of frequency, phase and quadrature amplitude modulation. The resulting chip fabricated in 0.35um five level metal CMOS process has a complexity of 20,000 gates with core area of 2.00 ᱢ1.00 mm2 . 6. ACKNOWLEDGMENT The authors wish to thank Wenhong Li for providing the help in using EDA tools and Yawei Guo, Cheng Chen for DRC and LVS of the layout of the whole chip. 7. REFERENCES [1] C. Tierney, M. Rader, and B. Gold, “A digital frequency synthesizer,” IEEE Trans. Audio Electroacoust, vol. AU-19, pp.48-57, 1971. [2] H. T. Nicholas, III and H. Samueli, “A 150 MHz direct digital frequency synthesizer in 1.25-µm CMOS with –90 dBc spurious performance,” IEEE J. Solid-State Circuits, vol. 26, pp. 1959-1969, Dec. 1991. [3] Zhangwen Tang and Hao Min, “A direct digital frequency synthesizer Implemented with FPGA,” Transaction of Microelectronics, vol. 5, Oct. 2001. [4] H. T. Nicholas, III, H. Samueli, and B. Kim, “The optimization of direct digital frequency synthesizer performance in the presence of finite word length effects,” In Proc. 42nd Annu. Frequency Cont. Symp. USER-ACOM, Mar. 1988, pp. 357-363. [5] L. K. Tan and H. Samueli, “A 200MHz Quadrature Digital Synthesizer/Mixer in 0.8 µm CMOS,” IEEE J. Solid-State Circuits, vol. 30, pp. 193-200, Mar. 1993. [6] M. Nagamatsu et al., “A 15-ns 32 h 32-bit CMOS Multiplier with an improved paralled structure,” IEEE J. Solid-State Circuits, vol 25, pp. 494-497, April 1990. [7] J. Mori et al., “A 10-ns 54h54-b Parallel Structured Full Array Multiplier with 0.5 µm CMOS Technology,” IEEE J. Solid-State Circuits, vol 26, pp. 600-606, April 1991. [8] T. Lin, and H. Samueli, “A 200-MHz CMOS x/sin(x) Digital Filter for Compensating D/A Converter Frequency Response Distortion,” IEEE J. Solid-State Circuits, vol 26, pp. 1278-1285, Sep. 1991. MCU DDFS Adder Anti-SINC Filter Booth Multiplier Booth Multiplier Din[7:0] Dout[7:0] FQ_UD WR_clk WR_en reset reset clk reset clk reset clk reset clk re c FCW[31:0] Phase[7:0] Sin[11:0] Cos[11:0] I[11:0] Q COM[11:0] GND VDD (a) (b) Fig. 9 (a) Top Circuit of the Whole Chip, (b) Floorplan of Layout Fig. 10. Photomicrograph of the Packaged Chip Fig. 11. FFT Diagram of Outputting Signal I-4
