方法二:逻辑真值描述 LBRARY=日 USE IEEE STD_LOGIC_-1164ALLi ENTITY and3 S PORT (a, b, C: IN STD_LOGIC; y OUT STD_LOGIC); END and35 ARCHTECTURE and32 OF ands BEGIN t4: PROCESS (a, b, c) VARIABLE comb:STD_LOGIC_VECTOR(2 DOWNTO O)B BEGIN combe=a &b方法二：逻辑真值描述 LIBRARY IEEE; USE IEEE STD_LOGIC_1164.ALL; ENTITY and3 IS PORT (a，b，c : IN STD_LOGIC; y : OUT STD_LOGIC); END and3; ARCHITECTURE and3_2 OF and3 IS BEGIN t4: PROCESS (a，b，c) VARIABLE comb:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN comb := a & b & c;