T13/1532D Volume 3 Revision 0 Contents Page 1 Scope.… .1 Interface physical and electrical requirements 2.1 Cable configuration....... .3 2.2 Electrical characteristics..............3 2.3 Connectors and cable asemblies. 8 2.4 Physical form factors ...... .30 3 Interface signal assignments and descriptions .46 3.1 Signal summary. 46 3.2 Signal descriptions... .47 4 General operational requirements...................... 44440444444444444044444444444444 .52 4.1 Interrupts........ .52 4.2 Multiword DMA... .53 4.3 Ultra DMA feature set........ 53 4.4 Host determination of cable type by detecting CBLID- 56 4.5 Overlapped feature set.... .57 4.6 Queued feature set..… .59 5 Interface register definitions and descriptions .60 5.1 Device addressing considerations............ .60 5.2 1/O register descriptions........... .67 5.3 Alternate Status register.... .67 5.4 Command register............. 444444444444 68 5.5 Data port.. .69 5.6 Data register............. .69 5.7 Device register........... 444444444444 .70 5.8 Device Control register.... .71 5.9 Error register.................... 72 5.10 Features register.. .73 5.11 LBA High register............. .73 5.12 LBA Low register............. .74 5.13 LBA Mid register...… .74 5.14 Sector Count register............ .75 5.15 Status register.....… 444444444444444 .75 6 Protocol...… .79 6.1 Power-on and hardware reset protocol .82 6.2 Software reset protocol... 4444404444044444444044 .86 6.3 Bus idle protocol..… .91 6.4 Non-data command protocol... .102 6.5 PlO data-in command protocol.................. .104 6.6 PlO data-out command protocol...... .108 6.7 DMA command protocol........ 112 6.8 PACKET command protocol..................... .115 6.9 READ/WRITE DMA QUEUED command protocol... ....127 6.10 EXECUTE DEVICE DIAGNOSTIC command protocol. .131 6.11 DEVICE RESET command protocol... .136 6.12 Signature and persistence............. .137 6.13 Ultra DMA data-in commands............. .138 6.14 Ultra DMA data-out commands 141 6.15 Ultra DMA CRC rules........... 44444 ..143 6.16 Single device configurations .145 7 Timing...... .147 7.1 Deskewing.............. .147 7.2 Transfer timing............ .147 Page iT13/1532D Volume 3 Revision 0 Page i Contents Page 1 Scope .....................................................................................................................................1 2 Interface physical and electrical requirements .............................................................................3 2.1 Cable configuration .........................................................................................................3 2.2 Electrical characteristics .................................................................................................3 2.3 Connectors and cable asemblies......................................................................................8 2.4 Physical form factors ......................................................................................................30 3 Interface signal assignments and descriptions ............................................................................46 3.1 Signal summary .............................................................................................................46 3.2 Signal descriptions .........................................................................................................47 4 General operational requirements...............................................................................................52 4.1 Interrupts .......................................................................................................................52 4.2 Multiword DMA...............................................................................................................53 4.3 Ultra DMA feature set......................................................................................................53 4.4 Host determination of cable type by detecting CBLID-........................................................56 4.5 Overlapped feature set.....................................................................................................57 4.6 Queued feature set .........................................................................................................59 5 Interface register definitions and descriptions ..............................................................................60 5.1 Device addressing considerations.....................................................................................60 5.2 I/O register descriptions ..................................................................................................67 5.3 Alternate Status register..................................................................................................67 5.4 Command register ..........................................................................................................68 5.5 Data port........................................................................................................................69 5.6 Data register ..................................................................................................................69 5.7 Device register................................................................................................................70 5.8 Device Control register ....................................................................................................71 5.9 Error register..................................................................................................................72 5.10 Features register ............................................................................................................73 5.11 LBA High register ...........................................................................................................73 5.12 LBA Low register............................................................................................................74 5.13 LBA Mid register.............................................................................................................74 5.14 Sector Count register......................................................................................................75 5.15 Status register................................................................................................................75 6 Protocol ..................................................................................................................................79 6.1 Power-on and hardware reset protocol ..............................................................................82 6.2 Software reset protocol....................................................................................................86 6.3 Bus idle protocol.............................................................................................................91 6.4 Non-data command protocol ............................................................................................102 6.5 PIO data-in command protocol.........................................................................................104 6.6 PIO data-out command protocol.......................................................................................108 6.7 DMA command protocol..................................................................................................112 6.8 PACKET command protocol ............................................................................................115 6.9 READ/WRITE DMA QUEUED command protocol..............................................................127 6.10 EXECUTE DEVICE DIAGNOSTIC command protocol.........................................................131 6.11 DEVICE RESET command protocol .................................................................................136 6.12 Signature and persistence...............................................................................................137 6.13 Ultra DMA data-in commands ..........................................................................................138 6.14 Ultra DMA data-out commands ........................................................................................141 6.15 Ultra DMA CRC rules ......................................................................................................143 6.16 Single device configurations .............................................................................................145 7 Timing.....................................................................................................................................147 7.1 Deskewing .....................................................................................................................147 7.2 Transfer timing................................................................................................................147