MC14553B IA CIB Q1H07 D St D33 VoD= PIN 16 Figure 1. Block Diagram TRUTH TABLE Master Reset Clock Disable Outputs 000 0 No Change 0 1 X No Change No Change 000 No Change Q0=Q1=Q2=Q3=0 X= Dont Care httpllonsemi.comMC14553B http://onsemi.com 2 Figure 1. Block Diagram 12 10 11 13 9 7 6 5 14 2 1 15 VDD = PIN 16 VSS = PIN 8 4 3 CLOCK LE DIS MR Q0 Q1 Q2 Q3 O.F. DS1 DS2 DS3 CIA CIB TRUTH TABLE Inputs Master Reset Clock Disable LE Outputs 0 0 0 No Change 0 0 0 Advance 0 X 1 X No Change 0 1 0 Advance 0 1 0 No Change 0 0 X X No Change 0 X X Latched 0 X X 1 Latched 1 X X 0 Q0 = Q1 = Q2 = Q3 = 0 X = Don’t Care