【例9-3】 LIBRARY IEEE USE IEEE STD LOGIC 1164.ALL: USE IEEE STD LOGIC UNSIGNEDALL ENTITY alu Is PORT a, b: IN STD LOGIC VECTOR (7 DOWNTO0); opcode: IN STD LOGIC VECTOR(I DOWNTO0); result: OUT STD LOGIC VECTOR(7 DOWNTOO)) END alu: arChitECtURe behave of alu is CONSTANT plus STD LOGIC VECTOR (I DOWNTO0): =b00 CONSTANT minus STD LOGIC VECTOR (I DOWNTO0): b01; CONSTANTequal STD LOGIC VECTOR(I DOWNTO0: =b"10 CONSTANT not equal: STD LOGIC VECTOR (I DOWNTO0): =bl1"; 接下页接下页 【例9-3】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY alu IS PORT( a, b : IN STD_LOGIC_VECTOR(7 DOWNTO0); opcode:IN STD_LOGIC_VECTOR(1 DOWNTO0); result:OUT STD_LOGIC_VECTOR(7 DOWNTO0) ); END alu; ARCHITECTUREbehave OF alu IS CONSTANTplus : STD_LOGIC_VECTOR(1 DOWNTO0) := b"00"; CONSTANT minus : STD_LOGIC_VECTOR(1 DOWNTO0) := b"01"; CONSTANTequal : STD_LOGIC_VECTOR(1 DOWNTO0) := b"10"; CONSTANTnot_equal: STD_LOGIC_VECTOR (1 DOWNTO0) := b"11";