不完整的条件语句的VHDL 1. ENTITY COMP BAD IS 2 PORT( a1 BIT BIT 4 q OUT BIT 6. END ENTITY COMP BAD 7. ARCHITECTUREone OF COMP BAd is 8. BEGIN PROCESS(a1, b1) 10 BEGIN 11 IF a1> b1 THEN 12. q1= 13. ELSIF a1< b1 THEN 请看图 14. q 15 END IF END PROCESS A END ARCHITECTURE one GG不完整的 条件语句 的VHDL 1. ENTITY COMP_BAD IS 2. PORT ( a1 : IN BIT; 3. b1 : IN BIT; 4. q1 : OUT BIT 5. ); 6. END ENTITY COMP_BAD; 7. ARCHITECTURE one OF COMP_BAD IS 8. BEGIN 9. PROCESS(a1,b1) 10. BEGIN 11. IF a1 > b1 THEN 12. q1 <= '1'; 13. ELSIF a1 < b1 THEN 14. q1 <= '0'; 15. END IF; 16. END PROCESS; 17. END ARCHITECTURE one; 请看图