序列发生器参考程序 工工 BRARY工EEE; USE IEEE STD LOGIC 1164.ALL ENTITY DSM IS PORT( CLK: IN STD LOGIC; DP: OUT STD LOGIC VECTOR(7 dOWNTo 0)i DOUT: OUT STD LOGIC ) i END DSM: ARCHITECTURE A OF DSM IS SIGNAL ST: STD LOGIC VECTOR(7 DOWNTo 0)i SIGNAL M: INTEGER RANGE 0 To 7; BEGIN ST<="01110010"; DP<=STi PROCESS (CLK) BEGIN IF CLK EVENT AND CLK=1 THEN M<=M-1 END工F; END PROCESS DOUT<=ST(M)i END Ai序列发生器参考程序： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DSM IS PORT( CLK: IN STD_LOGIC; DP:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); DOUT:OUT STD_LOGIC ); END DSM; ARCHITECTURE A OF DSM IS SIGNAL ST:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL M:INTEGER RANGE 0 TO 7; BEGIN ST<="01110010"; DP<=ST; PROCESS(CLK) BEGIN IF CLK'EVENT AND CLK='1' THEN M<=M-1; END IF; END PROCESS; DOUT<=ST(M); END A;