3.2 Pipelining 966 3 tap FIR filter y(n)=box(n)+bx(n-1)+bx(n-2) x(n) D b0 bl b2 critical path=TM+2TA y(n) The speed of an architecture is limited by the longest path ASIC between any 2 registers or la path 1 海D or between an input and a re path3 Path 4 CLK or between a register/latch al path 2 or between the input and the 2021年2月 42021年2月 4 3.2 Pipelining  The speed of an architecture is limited by the longest path  between any 2 registers or latches  or between an input and a register/latch  or between a register/latch and an output  or between the input and the output. D D X X X + + x(n) y(n) b0 b1 b2 3 tap FIR filter ( ) ( ) ( 1) ( 2) y n  b0 x n  b1 x n   b2 x n  critical path=TM+2TA