/966 This longest path or the critical path can be reduced by suitable placing the pipelining registers/latches in the architecture; The pipelining registers/latches can only be placed across any feed-forward cutset of the graph. x(n) D critical path-TM+TA 3 y(n) 1 Clock Input Point 1 Point 2 Point 3 Output 0 X0) ax(0)+bx(-1) 1 X(1) ax(1)+bx(0) ax(0)+bx(-1) 2 X(2) ax(2)+bx(1) ax(1)+bx(0) 3 X3) ax(3)+bx(2) ax(2)+bx(1) cx(0) ax(2)+bx(1)+cx(0)=y2) 2021年2月 52021年2月 5  This longest path or the critical path can be reduced by suitable placing the pipelining registers/latches in the architecture;  The pipelining registers/latches can only be placed across any feed-forward cutset of the graph. D D X X X + + x(n) y(n) a b c D D critical path=TM+TA Clock Input Point 1 Point 2 Point 3 Output 0 X(0) ax(0)+bx(-1) 1 X(1) ax(1)+bx(0) ax(0)+bx(-1) 2 X(2) ax(2)+bx(1) ax(1)+bx(0) 3 X(3) ax(3)+bx(2) ax(2)+bx(1) cx(0) ax(2)+bx(1)+cx(0)=y(2) 1 2 3