工程科学学报.第42卷，第8期：1065-1073.2020年8月 Chinese Journal of Engineering,Vol.42,No.8:1065-1073,August 2020 https://doi.org/10.13374/j.issn2095-9389.2019.08.03.001;http://cje.ustb.edu.cn 基于摆幅恢复传输管逻辑的高性能全加器设计 韩金亮)，张跃军)四，温亮》，张会红) 1)宁波大学信息科学与工程学院，宁波3152112)中国人民武装警察部队海警学院电子技术系.宁波315211 ☒通信作者，E-mail:zhangyuejun(@nbu.edu.cn 摘要为了降低硬件开销，越来越多的加法器电路采用传输管逻辑来减少晶体管数量，同时导致阈值损失、性能降低等问 题.本文通过对摆幅恢复逻辑与全加器电路的研究，提出一种基于摆幅恢复传输管逻辑(Swing restored pass transistor logic, SPL)的全加器设计方案.该方案首先分析电路的阈值损失机理，结合晶体管传输高、低电平的特性，提出一种摆幅恢复传 输管逻辑的设计方法：然后，采用对称结构设计无延时偏差输出的异或/同或电路，利用MOS管补偿阈值损失的方式，实现异 或/同或电路的全摆幅输出：最后，将异或/同或电路融合于全加器结构.结合4TXOR求和电路与改进的传输门进位电路实现 摆幅恢复的高性能全加器.在TSMC65m工艺下，本文采用HSPICE仿真验证所设计的逻辑功能，与文献相比延时降低 10.8%,功耗延时积(Power-delay product,.PDP)减少13.5%以上. 关键词异或同或：摆幅恢复：高性能全加器：阈值损失：全摆幅 分类号TN702 High-performance full adder design based on SRPL HAN Jin-liang,ZHANG Yue-jun,WEN Liang,ZHANG Hui-hong 1)Faculty of Electrical Engineering and Computer Science,Ningbo University,Ningbo 315211,China 2)Department of Electronic Technology,China Coast Guard Academy,Ningbo 315211,China Corresponding author,E-mail:zhangyuejun @nbu.edu.cn ABSTRACT The adder circuit is the core component of the high-performance system-on-chip(SoC).It is also important in image and voice encryption.The full adder circuit is a basic unit with a very high reuse rate among all the units.Therefore,the design of an adder with high energy efficiency is of great significance for the optimization of digital circuit systems.In recent years,numerous researchers have studied the design of advanced adder circuits,which are characterized by high speed and low power consumption.To reduce the hardware overhead,an increasing number of adder circuits utilize the transmission tube logic to reduce the number of transistors. However,this method also brings about several negative effects,such as threshold loss and performance degradation.In this paper,by studying the swing recovery logic and full adder circuit,we proposed a full adder design scheme based on swing restored pass-transistor logic(SRPL).First,the threshold loss mechanism of the circuit was analyzed,and the characteristics of the high-efficiency transmission of high-level and low-level transistors were considered;then the design method of the swing recovery transmission tube logic was developed.We used a symmetric structure to design an XOR/XNOR circuit without delay deviation output.The two-shot MOS tube was used to compensate the threshold loss to realize the full swing output of the XOR/XNOR circuit.Finally,we fused the designed XOR/XNOR circuit to the full adder structure and used the 4T XOR sum circuit and the improved transmission gate carry circuit to implement the high-performance full adder for swing recovery.In the TSMC 65 nm process,the logic function of our method was verified by HSPICE simulation.Compared with the conventional approach,the delay is reduced by 10.8%,and the power-delay product 收稿日期：2019-08-03 基金项目：国家自然科学基金资助项目(61871244,61874078)：浙江省自然科学基金资助项目LY18℉040002)：宁波大学王宽减幸福基金：宁 波大学教学研究资助项目(JYXMXYB201934)片宁波大学研究生科研创新资助基金(2019SRP1335)基于摆幅恢复传输管逻辑的高性能全加器设计 韩金亮1)，张跃军1) 苣，温    亮2)，张会红1) 1) 宁波大学信息科学与工程学院，宁波 315211    2) 中国人民武装警察部队海警学院电子技术系，宁波 315211 苣通信作者，E-mail: zhangyuejun@nbu.edu.cn 摘    要    为了降低硬件开销，越来越多的加法器电路采用传输管逻辑来减少晶体管数量，同时导致阈值损失、性能降低等问 题. 本文通过对摆幅恢复逻辑与全加器电路的研究，提出一种基于摆幅恢复传输管逻辑（Swing restored pass transistor logic, SRPL）的全加器设计方案. 该方案首先分析电路的阈值损失机理，结合晶体管传输高、低电平的特性，提出一种摆幅恢复传 输管逻辑的设计方法；然后，采用对称结构设计无延时偏差输出的异或/同或电路，利用 MOS 管补偿阈值损失的方式，实现异 或/同或电路的全摆幅输出；最后，将异或/同或电路融合于全加器结构，结合 4T XOR 求和电路与改进的传输门进位电路实现 摆幅恢复的高性能全加器. 在 TSMC 65 nm 工艺下，本文采用 HSPICE 仿真验证所设计的逻辑功能，与文献相比延时降低 10.8%，功耗延时积（Power-delay product, PDP）减少 13.5% 以上. 关键词    异或/同或；摆幅恢复；高性能全加器；阈值损失；全摆幅 分类号    TN702 High-performance full adder design based on SRPL HAN Jin-liang1) ，ZHANG Yue-jun1) 苣 ，WEN Liang2) ，ZHANG Hui-hong1) 1) Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China 2) Department of Electronic Technology, China Coast Guard Academy, Ningbo 315211, China 苣 Corresponding author, E-mail: zhangyuejun@nbu.edu.cn ABSTRACT    The adder circuit is the core component of the high-performance system-on-chip (SoC). It is also important in image and voice encryption. The full adder circuit is a basic unit with a very high reuse rate among all the units. Therefore, the design of an adder with high energy efficiency is of great significance for the optimization of digital circuit systems. In recent years, numerous researchers have studied the design of advanced adder circuits, which are characterized by high speed and low power consumption. To reduce the hardware  overhead,  an  increasing  number  of  adder  circuits  utilize  the  transmission  tube  logic  to  reduce  the  number  of  transistors. However, this method also brings about several negative effects, such as threshold loss and performance degradation. In this paper, by studying the swing recovery logic and full adder circuit, we proposed a full adder design scheme based on swing restored pass-transistor logic (SRPL). First, the threshold loss mechanism of the circuit was analyzed, and the characteristics of the high-efficiency transmission of  high-level  and  low-level  transistors  were  considered;  then  the  design  method  of  the  swing  recovery  transmission  tube  logic  was developed. We used a symmetric structure to design an XOR/XNOR circuit without delay deviation output. The two-shot MOS tube was used  to  compensate  the  threshold  loss  to  realize  the  full  swing  output  of  the  XOR/XNOR  circuit.  Finally,  we  fused  the  designed XOR/XNOR circuit to the full adder structure and used the 4T XOR sum circuit and the improved transmission gate carry circuit to implement  the  high-performance  full  adder  for  swing  recovery.  In  the  TSMC  65  nm  process,  the  logic  function  of  our  method  was verified by HSPICE simulation. Compared with the conventional approach, the delay is reduced by 10.8%, and the power-delay product 收稿日期: 2019−08−03 基金项目: 国家自然科学基金资助项目 (61871244, 61874078)；浙江省自然科学基金资助项目 LY18F040002)；宁波大学王宽诚幸福基金；宁 波大学教学研究资助项目 (JYXMXYB201934)；宁波大学研究生科研创新资助基金 (2019SRIP1335) 工程科学学报，第 42 卷，第 8 期：1065−1073，2020 年 8 月 Chinese Journal of Engineering, Vol. 42, No. 8: 1065−1073, August 2020 https://doi.org/10.13374/j.issn2095-9389.2019.08.03.001; http://cje.ustb.edu.cn