【例9-1】 工工 BRARY工; USE IEEE STD LOGIC 1164.ALL: ENTITY mux41 IS ORT(s4, s3, s2, s1: IN STD LOGICi z4, z3, z2, Z1: OUT STD LOGIC) END mux41 ARcH工 TECTURE ad七 1v OF mUX41工s SIGNAL sel: INTEGER RANGE 0 To 15; BEGIN PROCESs (sel s4, s3, s2, s1) BEGIN se1<=0; 输入初始值 IF (sl =1 THEN sel < sel+l i ElSIF (s2 =1)THEN sel < sel+2 ElSIF ( s3 =1 THEN sel < sel+4 i ElSIF (s4=l')THEN sel < sel+8 i ELSE NULL 注意,这里使用了空操作语句 END工F; z1<=·0;z2<=10";z3<="0';z4<="0"; 输入初始值 CASE sel IS WHeN o z1<=11!; 当se]=0时选中 接下页KX 康芯科技 【例9-1】 LIBRARY IEEE； USE IEEE.STD_LOGIC_1164.ALL； ENTITY mux41 IS PORT (s4，s3, s2，s1 : IN STD_LOGIC; z4，z3, z2，z1 : OUT STD_LOGIC); END mux41； ARCHITECTURE activ OF mux41 IS SIGNAL sel : INTEGER RANGE 0 TO 15; BEGIN PROCESS (sel ，s4，s3，s2，s1 ) BEGIN sel<= 0 ; -- 输入初始值 IF (s1 ='1') THEN sel <= sel+1 ; ELSIF (s2 ='1') THEN sel <= sel+2 ; ELSIF (s3 ='1') THEN sel <= sel+4 ; ELSIF (s4 ='1') THEN sel <= sel+8 ; ELSE NULL; -- 注意，这里使用了空操作语句 END IF ; z1<='0' ; z2<='0'; z3<='0'; z4<='0'; --输入初始值 CASE sel IS WHEN 0 => z1<='1' ; -- 当sel=0时选中 接下页