Contents RM0394 8.3.3 O port control registers 262 8.3.4 l/o port data registers.....................................262 8.3.5 V/O data bitwise handling ,262 8.36 GPIO locking mechanism 263 8.3.7 1/O alternate function input/output........................... 263 8.3.8 Extemnal interrupt/wakeup lines 263 83.9 Input configuration,,,,,,,,,,,,,,,,,,,,,,,,, 264 8.3.10 Output configuration 264 8311 Altemnate function configuration 265 8.3.12 Analog configuration.................................... 8313 Using the HSE or LSE oscillator pins as GPIOs … 266 8.3.14 Using the GPIO pins in the RTC supply domain 266 8.3.15 Using PH3 as GPIO 267 8.4 GPIO registers........................ 267 8.4.1 GPIO port mode register(GPIOx_MODER)(x=A to E and H). 267 8.4.2 GPIO port output type register(GPIOx_OTYPER)(x=A to E and H)268 8.4.3 268 8.4.4 268 8.4.5 GPIO port input data register (GPIOx IDR)(x =A to E and H)......269 8.4.6 GPIO port output data register(GPIOx_ODR)(x=A to E and H) ..269 8.47 GPIO port bit set/reset register (GPIOx_BSRR)(x=Ato E and H) 8.4.8 GPIO port configuration lock register(GPIOx_LCKR) (=Ato Eand H)....................................... 270 8.4.9 GPIO alternate function low register(GPIOx_AFRL) (x=A to E and H）.................... 271 8.4.10 GPIO alternate function high register(GPIOx_AFRH) (x =A to E and H)......... .272 8411 GPIO port bit reset register(GPIOx_BRR)(x=A to E and H)......273 84.12 GPIO register map 274 9 System configuration controller (SYSCFG)....................276 9.1 SYSCFG main features 。。。。 276 9.2 SYSCFG registers................ 276 9.2.1 SYSCFG memory remap register(SYSCFG_MEMRMP)...... 276 9.22 SYSCFG configuration register 1(SYSCFG CFGR1) ,..277 9.2.3 errupt configuration register1 .278 8/1600 RM0394 Rev 4 7Contents RM0394 8/1600 RM0394 Rev 4 8.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 8.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 8.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 8.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 8.3.7 I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 8.3.8 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 8.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 8.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 8.3.11 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 8.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 8.3.13 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 266 8.3.14 Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 266 8.3.15 Using PH3 as GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 8.4 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 8.4.1 GPIO port mode register (GPIOx_MODER) (x =A to E and H) . . . . . . 267 8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A to E and H) 268 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A to E and H) . . . . . . 269 8.4.6 GPIO port output data register (GPIOx_ODR) (x = A to E and H) . . . . 269 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A to E and H) . . 270 8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to E and H) . . . . . . 273 8.4.12 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 9 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 276 9.1 SYSCFG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 9.2 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 9.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . . . . . . . 276 9.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 277 9.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278