RM0394 e.augmented Reference manual STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx advanced Arm-based 32-bit MCUs Introduction ual targets application devel vides complete information peripherals. The STM32L41xxx/42xXx/43xxx/44xxx/45xxx/46xxx is a family of microcontrollers with different memory sizes,packages and peripherals. mechanical and electrical device characteristics please refer to the Related documents Cortex-M4 Technical Reference Manual,available from:http://infocenter.arm.com STM32L412XX STM321422XX STM321431 STM321432XX STM321433xX STM32L442xx STM32L443X,STM32L451xx STM32L452xx STM32L462xx datasheets STM32F3.STM32F4.STM32L4 and STM32L4+Series Cortex-M4(PM0214) October 2018 RM0394 Rev4 1V160 www.st.com
October 2018 RM0394 Rev 4 1/1600 1 RM0394 Reference manual STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx advanced Arm®-based 32-bit MCUs Introduction This reference manual targets application developers. It provides complete information on how to use the STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx microcontroller memory and peripherals. The STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx is a family of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics please refer to the corresponding datasheets. For information on the Arm® Cortex®-M4 core, please refer to the Cortex®-M4 Technical Reference Manual. Related documents • Cortex®-M4 Technical Reference Manual, available from: http://infocenter.arm.com • STM32L412xx, STM32L422xx, STM32L431xx, STM32L432xx, STM32L433xx, STM32L442xx, STM32L443xx, STM32L451xx, STM32L452xx, STM32L462xx datasheets • STM32F3, STM32F4, STM32L4 and STM32L4+ Series Cortex®-M4 (PM0214) www.st.com
Contents RM0394 Contents Documentation conventions.................................60 1.1 General information..........................................60 1.2 List of abbreviations for registers...............................60 1.3 Glossary...............61 1.4 Availability of peripherals 61 1.5 Product specific features .,.61 System and memory overview 000gggg。g0g000000080000800800g 63 2.1 System architecture 63 2.1.1 80:hbus................................................64 212 S1:D-bus」 2.1.3 S2:S-bus 0……。。4。。。。……。…“。……。…。……。… 65 2.1.4 S3,S4:DMA-bus.................................... 2.15 BusMatrix 2.2 Memory organization........................................ 66 2.21 Introduction 2.2.2 Memory map and register boundary addresses............. 2.3 Bit banding…70 2.4 Embedded SRAM.................71 2.4.1 SRAM2 parity check 2.4.2 SRAM2 Write protection....................................72 243 SRAM2 Read protection ..73 2.4.4 SRAM2Erase.................................... 73 2.5 Flash memory overview 7 2.6 Bootconfiguration..........................................74 3 Embedded Flash memory (FLASH)........................... .77 3.1 Introduction.. ..77 32 FLASH main features........................................ 3.3 FLASH functional description .77 3.3.1 Flash memory organization 77 3.3.2 Error code correction (ECC) ....78 3.3.3 Read access latency 2/1600 RM0394Rev4 7
Contents RM0394 2/1600 RM0394 Rev 4 Contents 1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1.1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1.2 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1.3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.4 Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.5 Product specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2 System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.1.1 S0: I-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.1.2 S1: D-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.1.3 S2: S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.1.4 S3, S4: DMA-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.1.5 BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.2.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 67 2.3 Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.4.1 SRAM2 parity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.4.2 SRAM2 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.4.3 SRAM2 Read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.4.4 SRAM2 Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.5 Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.6 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3 Embedded Flash memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.2 FLASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.3 FLASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.3.1 Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.3.2 Error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.3.3 Read access latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
RM0394 Contents 3.3.4 Adaptive real-time memory accelerator (ART AcceleratorTM) 80 3.35 Flash program and erase operations .82 3.3.6 Flash main memory erase sequences ..........................83 3.3.7 Flash main memory programming sequences 3.4 FLASH option bytes 88 34.1 Option bytes description 3.4.2 Option bytes programming............................. .92 35 FLASH memory protection 3.5.1 Read protection(RDP) 94 3.52 Proprietary code readout protection(PCROP) 35.3 Write protection(WRP) 。，。 3.6 FLASH interrupts 3.7 FLASHregisters...........................................100 3.7.1 Flash access control register(FLASH_ACR) 100 3.7.2 Flash Power-down key register(FLASH_PDKEYR) 3.73 Flash key register(FLASH KEYR). 3.74 Flash option key register(FLASH_OPTKEYR 102 3.7.5 Flash status register (FLASH_SR)....................... 102 3.7.6 Flash control register(FLASH_CR) 104 3.77 Flash ECC register(FLASH_ECCR) 106 3.7.8 Flash option register (FLASH OPTR) 107 3.7.9 Flash PCROP Start address register(FLASH_PCROP1SR) 109 3.7.10 Flash PCROP End address register(FLASH PCROP1ER) .109 3711 Flash WRP area A address register(FLASH WRP1AR) ,110 37.12 Flash WRP area B address register (FLASH_WRP1BR) 3.7.13 .112 Firewall (FW) 114 4.1 Introduction 114 4.2 Firewall main features 。。。。，。。 .114 4.3 Firewall functional description .115 4.3.1 Firewall AMBA bus snoop ............................ ,115 4.32 Functional requirements 115 43.3 Firewall segments 116 4.3.4 Segment accesses and properties...........................117 4.3.5 Firewall initialization ..118 RM0394 Rev4 3/1600
RM0394 Rev 4 3/1600 RM0394 Contents 43 3.3.4 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 80 3.3.5 Flash program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.3.6 Flash main memory erase sequences . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.3.7 Flash main memory programming sequences . . . . . . . . . . . . . . . . . . . . 84 3.4 FLASH option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.4.1 Option bytes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.4.2 Option bytes programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.5 FLASH memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.5.1 Read protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.5.2 Proprietary code readout protection (PCROP) . . . . . . . . . . . . . . . . . . . 97 3.5.3 Write protection (WRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.6 FLASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.7 FLASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.7.1 Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . 100 3.7.2 Flash Power-down key register (FLASH_PDKEYR) . . . . . . . . . . . . . . 101 3.7.3 Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.7.4 Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . 102 3.7.5 Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.7.6 Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 3.7.7 Flash ECC register (FLASH_ECCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.7.8 Flash option register (FLASH_OPTR) . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.7.9 Flash PCROP Start address register (FLASH_PCROP1SR) . . . . . . . 109 3.7.10 Flash PCROP End address register (FLASH_PCROP1ER) . . . . . . . . 109 3.7.11 Flash WRP area A address register (FLASH_WRP1AR) . . . . . . . . . . 110 3.7.12 Flash WRP area B address register (FLASH_WRP1BR) . . . . . . . . . . 110 3.7.13 FLASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4 Firewall (FW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 4.2 Firewall main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 4.3 Firewall functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 4.3.1 Firewall AMBA bus snoop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.3.2 Functional requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.3.3 Firewall segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.3.4 Segment accesses and properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.3.5 Firewall initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Contents RM0394 4.3.6 Firewall states 119 4.4 Firewall registers........ 121 441 Code segment start address(FW_CSSA) 2 4.42 Code segment length(FW CSL)..... 4.4.3 Non-volatile data segment start address(FW_NVDSSA) 1 444 Non-volatile data segment length (FW_NVDSL) 122 4.4.5 Volatile data segment start address(FW_VDSSA) .123 4.4.6 Volatile data segment length(FW_VDSL) ,123 4.47 Configuration register (FW CR)............................ 124 4.4.8 Firewall register map.......,......................... 125 Power control(PWR) 126 5.1 Power supplies 126 5.1.1 Independent analog peripherals supply 128 5.1.2 Independent USB transceivers supply 129 513 ndependent LCD supply 129 5.1.4 Battery backup domai ,130 5.15 Voltage reaulator .131 5.1.6 VDD12 domain 132 5.1.7 Dynamic voltage scaling management 133 5.2 Power supply supervisor 135 5.2.1 66mePoRoertaneaPoR1romoae 5.2.2 Programmable voltage detector (PVD)..... 135 523 Peripheral Voltage Monitoring(PVM) 136 5.3 Low-power modes 137 531 Run mode 5.3.2 Low-power run mode (LP run)............................... 4 5.3.3 Low power modes 45 53.4 Sleep mode 14 5.3.5 Low-power sleep mode (LP sleep) 5.3.6 Stop 0 mode 148 5.3.7 Stop1mode........................................ 5.3.8 Stop 2 mode. .151 5.3.9 Standby mode 3 5.3.10 Shutdown mode. 156 5.3.11 Auto-wakeup from low-power mode .157 4/1600 RM0394 Rev 4 7
Contents RM0394 4/1600 RM0394 Rev 4 4.3.6 Firewall states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.4 Firewall registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.4.1 Code segment start address (FW_CSSA) . . . . . . . . . . . . . . . . . . . . . . 121 4.4.2 Code segment length (FW_CSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.4.3 Non-volatile data segment start address (FW_NVDSSA) . . . . . . . . . . 122 4.4.4 Non-volatile data segment length (FW_NVDSL) . . . . . . . . . . . . . . . . . 122 4.4.5 Volatile data segment start address (FW_VDSSA) . . . . . . . . . . . . . . . 123 4.4.6 Volatile data segment length (FW_VDSL) . . . . . . . . . . . . . . . . . . . . . . 123 4.4.7 Configuration register (FW_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.4.8 Firewall register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.1.1 Independent analog peripherals supply . . . . . . . . . . . . . . . . . . . . . . . . 128 5.1.2 Independent USB transceivers supply . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.1.3 Independent LCD supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.1.4 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.1.5 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.1.6 VDD12 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5.1.7 Dynamic voltage scaling management . . . . . . . . . . . . . . . . . . . . . . . . 133 5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.2.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 135 5.2.3 Peripheral Voltage Monitoring (PVM) . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5.3.1 Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 5.3.2 Low-power run mode (LP run) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 5.3.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5.3.4 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.3.5 Low-power sleep mode (LP sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5.3.6 Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.3.7 Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 5.3.8 Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.3.9 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 5.3.10 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 5.3.11 Auto-wakeup from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . 157
RM0394 Contents 5.4 PWR registers 158 5.4.1 Power control register 1 (PWR CR1) .158 5.4.2 Power control register 2(PWR CR2) 159 5.4.3 Power control register 3(PWR_CR3) 160 5.4.4 Power control reaister 4(PWR CR4) 161 5.4.5 Power status register 1(PWR_SR1) 16x 5.46 Power status register 2(PWR_SR2) 164 5.47 Power status clear register(PWR SCR) 1 54.8 Power Port A pull-up control register(PWR_PUCRA) 166 5.4.9 Power Port A pull-down control register(PWR PDCRA). 166 5.4.10 Power Port B pull-up control register(PWR PUCRB) 167 5.4.11 Power Port B pull-down control register(PWR_PDCRB) 167 5.4.12 Power Port C pull-up control register (PWR PUCRC) .168 5.4.13 Power Port C pull-down control register(PWR_PDCRC) 16g 5414 Power Port D pull-up control register(PWR_PUCRD) 169 5.415 Power Port D pull-down control register(PWR PDCRD) 169 5.416 Power Port E pull-up control register(PWR_PUCRE) 0 5.4.17 Power Port E pull-down control register(PWR PDCRE) ,170 5.4.18 Power Port H pull-up control register(PWR_PUCRH) 171 5.419 Power Port H pull-down control register(PWR_PDCRH) 5.4.20 PWR register map and reset value table .173 Reset and clock control(RCC) 175 6.1 Reset 175 611 Power reset 15 6.1.2 175 6.1.3 Backup domain reset 176 6.2 Clocks...................................................TT 6.21 HSE clock 181 622 HSI16 clock 6.23 MSI clock 183 624 HS148 clock 183 6.2.5 pLL............................................... ,184 6.2.6 LSE clock 185 6.2.7 LSI clock 185 6.2.8 System clock (SYSCLK)selection..................... .185 629 Clock source frequency versus voltage scaling ,186 RM0394 Rev 4 5/1600
RM0394 Rev 4 5/1600 RM0394 Contents 43 5.4 PWR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.4.1 Power control register 1 (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.4.2 Power control register 2 (PWR_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.4.3 Power control register 3 (PWR_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . 160 5.4.4 Power control register 4 (PWR_CR4) . . . . . . . . . . . . . . . . . . . . . . . . . 161 5.4.5 Power status register 1 (PWR_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.4.6 Power status register 2 (PWR_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.4.7 Power status clear register (PWR_SCR) . . . . . . . . . . . . . . . . . . . . . . . 165 5.4.8 Power Port A pull-up control register (PWR_PUCRA) . . . . . . . . . . . . . 166 5.4.9 Power Port A pull-down control register (PWR_PDCRA) . . . . . . . . . . 166 5.4.10 Power Port B pull-up control register (PWR_PUCRB) . . . . . . . . . . . . . 167 5.4.11 Power Port B pull-down control register (PWR_PDCRB) . . . . . . . . . . 167 5.4.12 Power Port C pull-up control register (PWR_PUCRC) . . . . . . . . . . . . 168 5.4.13 Power Port C pull-down control register (PWR_PDCRC) . . . . . . . . . . 168 5.4.14 Power Port D pull-up control register (PWR_PUCRD) . . . . . . . . . . . . 169 5.4.15 Power Port D pull-down control register (PWR_PDCRD) . . . . . . . . . . 169 5.4.16 Power Port E pull-up control register (PWR_PUCRE) . . . . . . . . . . . . . 170 5.4.17 Power Port E pull-down control register (PWR_PDCRE) . . . . . . . . . . 170 5.4.18 Power Port H pull-up control register (PWR_PUCRH) . . . . . . . . . . . . 171 5.4.19 Power Port H pull-down control register (PWR_PDCRH) . . . . . . . . . . 171 5.4.20 PWR register map and reset value table . . . . . . . . . . . . . . . . . . . . . . . 173 6 Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.1.1 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.1.2 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 6.2.2 HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 6.2.3 MSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 6.2.4 HSI48 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 6.2.5 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 6.2.6 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.2.7 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.2.8 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.2.9 Clock source frequency versus voltage scaling . . . . . . . . . . . . . . . . . . 186
Contents RM0394 6.2.10 Clock security system(CSS) 6.2.11 Clock security system on LSE...............................187 6212 ADC clock ,187 62.13 RTCclock 187 6.2.14 ,188 6.2.15 Watchdog clock 188 6.2.16 Clock-out capability 6.2.17 Intemnal/extemal clock measurement with TIM15IM16 ..189 6218 191 6.3 Low-power modes 191 6.4 RCC registers 193 6.4.1 Clock control register (RCC CR)........... ,193 6.4.2 Intemal clock sources calibration register(RCC_ICSCR) 196 6.43 Clock configuration register (RCC_CFGR) 6.4.4 PLL configuration register (RCC PLLCFGR) 198 PLLSAI1 configuration register(RCC_PLLSAI1CFGR) 201 Clock interrupt enable register(RCC_CIER) 。。。 204 6.4.7 Clock interrupt flag register(RCC CIFR) 206 648 Clock interrupt clear register(RCC_CICR 207 6.4.9 AHB1 peripheral reset register(RCC_AHB1RSTR) 208 6.4.10 AHB2 peripheral reset register(RCC_AHB2RSTR) 209 6.4.11 AHB3 peripheral reset register(RCC_AHB3RSTR) 211 6.4.12 APB1 peripheral reset register 1(RCC APB1RSTR1) 211 64.13 APB1 peripheral reset register 2(RCC_APB1RSTR2) 214 6.4.14 APB2 peripheral reset register(RCC_APB2RSTR) 215 6.415 AHB1 peripheral clock enable register(RCC AHB1ENR) 216 6.4.16 AHB2 peripheral clock enable register(RCC_AHB2ENR) 218 6.4.17 AHB3 peripheral clock enable register(RCC AHB3ENR)...... 219 6.4.18 APB1 peripheral clock enable register 1(RCC_APB1ENR1) 6.4.19 APB1 peripheral clock enable register 2(RCC_APB1ENR2) 6.4.20 APB2 peripheral clock enable register(RCC_APB2ENR). .224 6.4.21 ocks enable in Sleep and Stop modes register 225 6.422 enable in Sleep and Stop modes registe AHB2SMENR) 226 6.4.23 cks AHB3SMENR enable in Sleep and Stop modes registe .228 6/1600 RM0394 Rev 4 7
Contents RM0394 6/1600 RM0394 Rev 4 6.2.10 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 6.2.11 Clock security system on LSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.2.12 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.2.13 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.2.14 Timer clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 6.2.15 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 6.2.16 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 6.2.17 Internal/external clock measurement with TIM15/TIM16 . . . . . . . . . . . 189 6.2.18 Peripheral clock enable register (RCC_AHBxENR, RCC_APBxENRy) . . . . . . . . . . . . . . . . . . . . . . . . . 191 6.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 6.4 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.4.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.4.2 Internal clock sources calibration register (RCC_ICSCR) . . . . . . . . . . 196 6.4.3 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 196 6.4.4 PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . . . . . 198 6.4.5 PLLSAI1 configuration register (RCC_PLLSAI1CFGR) . . . . . . . . . . . 201 6.4.6 Clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . . . . . 204 6.4.7 Clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . . . . . 206 6.4.8 Clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . . . . . 207 6.4.9 AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . . . . . 208 6.4.10 AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . . . . . 209 6.4.11 AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . . . . . 211 6.4.12 APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . . . . . . . . . 211 6.4.13 APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . . . . . . . . . 214 6.4.14 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 215 6.4.15 AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . . . . . 216 6.4.16 AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . . . . . 218 6.4.17 AHB3 peripheral clock enable register(RCC_AHB3ENR) . . . . . . . . . . 219 6.4.18 APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . . . . 220 6.4.19 APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . . . . 222 6.4.20 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 224 6.4.21 AHB1 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 6.4.22 AHB2 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 6.4.23 AHB3 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
RM0394 Contents 6.4.24 8pRe8ieEaenensepansapmoteseer1 .228 6.4.25 ble and opmodes .231 6.4.26 APB2 peripheral clocks enable in Sleep and Stop modes register (RCC APB2SMENR) 233 6.4.27 Peripherals independent clock configuration register(RCC_CCIPR) 234 6.4.28 Backup domain control register (RCC BDCR)..................237 6420 Controlstatus register(RCC CSR) 239 6.4.30 Clock recovery RC register(RCC_CRRCR)..... 241 6.4.31 Peripherals independent clock configuration register(RCC_CCIPR2)242 6432 RCC register map 242 Clock recovery system (CRS)...............................247 7.1 Introduction 247 7.2 CRS main features. 247 7.3 CRS functional description................................... 248 7.3.1 CRS block diagram 248 7.32 Synchronization input 248 7.3.3 Frequency error measurement 249 73.4 Frequency error evaluation and automatic trimming 250 7.3.5 CRS initialization and configuration ......................... 250 7.4 CRS low-power modes. 251 7.5 CRS interrupts.......................................... 251 7.6 CRS registers 252 7.6.1 CRS control register(CRS CR)..... ,252 7.6.2 CRS configuration register (CRS_CFGR) 253 7.6.3 CRS interrupt and status register (CRS ISR).................. .254 764 CRS interupt flag clear register(CRS ICR) .256 7.6.5 CRS register map 257 8 General-purpose l/os (GPIO)............................... 258 8.1 Introduction 258 8.2 GPIO main features 258 8.3 GPIO functional description 258 8.3.7 General-purpose /(GPIO 261 8.3.2 1/O pin alternate function multiplexer and mapping........... ,261 7 RM0394 Rev4 71600
RM0394 Rev 4 7/1600 RM0394 Contents 43 6.4.24 APB1 peripheral clocks enable in Sleep and Stop modes register 1 (RCC_APB1SMENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 6.4.25 APB1 peripheral clocks enable in Sleep and Stop modes register 2 (RCC_APB1SMENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 6.4.26 APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 6.4.27 Peripherals independent clock configuration register (RCC_CCIPR) . 234 6.4.28 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 237 6.4.29 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 6.4.30 Clock recovery RC register (RCC_CRRCR) . . . . . . . . . . . . . . . . . . . . 241 6.4.31 Peripherals independent clock configuration register (RCC_CCIPR2) 242 6.4.32 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 7 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 7.2 CRS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 7.3 CRS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 7.3.1 CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 7.3.2 Synchronization input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 7.3.3 Frequency error measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 7.3.4 Frequency error evaluation and automatic trimming . . . . . . . . . . . . . . 250 7.3.5 CRS initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 7.4 CRS low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 7.5 CRS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 7.6 CRS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 7.6.1 CRS control register (CRS_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 7.6.2 CRS configuration register (CRS_CFGR) . . . . . . . . . . . . . . . . . . . . . . 253 7.6.3 CRS interrupt and status register (CRS_ISR) . . . . . . . . . . . . . . . . . . . 254 7.6.4 CRS interrupt flag clear register (CRS_ICR) . . . . . . . . . . . . . . . . . . . . 256 7.6.5 CRS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 8 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 8.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 8.3 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 8.3.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 8.3.2 I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 261
Contents RM0394 8.3.3 O port control registers 262 8.3.4 l/o port data registers.....................................262 8.3.5 V/O data bitwise handling ,262 8.36 GPIO locking mechanism 263 8.3.7 1/O alternate function input/output........................... 263 8.3.8 Extemnal interrupt/wakeup lines 263 83.9 Input configuration,,,,,,,,,,,,,,,,,,,,,,,,, 264 8.3.10 Output configuration 264 8311 Altemnate function configuration 265 8.3.12 Analog configuration.................................... 8313 Using the HSE or LSE oscillator pins as GPIOs … 266 8.3.14 Using the GPIO pins in the RTC supply domain 266 8.3.15 Using PH3 as GPIO 267 8.4 GPIO registers........................ 267 8.4.1 GPIO port mode register(GPIOx_MODER)(x=A to E and H). 267 8.4.2 GPIO port output type register(GPIOx_OTYPER)(x=A to E and H)268 8.4.3 268 8.4.4 268 8.4.5 GPIO port input data register (GPIOx IDR)(x =A to E and H)......269 8.4.6 GPIO port output data register(GPIOx_ODR)(x=A to E and H) ..269 8.47 GPIO port bit set/reset register (GPIOx_BSRR)(x=Ato E and H) 8.4.8 GPIO port configuration lock register(GPIOx_LCKR) (=Ato Eand H)....................................... 270 8.4.9 GPIO alternate function low register(GPIOx_AFRL) (x=A to E and H）.................... 271 8.4.10 GPIO alternate function high register(GPIOx_AFRH) (x =A to E and H)......... .272 8411 GPIO port bit reset register(GPIOx_BRR)(x=A to E and H)......273 84.12 GPIO register map 274 9 System configuration controller (SYSCFG)....................276 9.1 SYSCFG main features 。。。。 276 9.2 SYSCFG registers................ 276 9.2.1 SYSCFG memory remap register(SYSCFG_MEMRMP)...... 276 9.22 SYSCFG configuration register 1(SYSCFG CFGR1) ,..277 9.2.3 errupt configuration register1 .278 8/1600 RM0394 Rev 4 7
Contents RM0394 8/1600 RM0394 Rev 4 8.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 8.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 8.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 8.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 8.3.7 I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 8.3.8 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 8.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 8.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 8.3.11 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 8.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 8.3.13 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 266 8.3.14 Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 266 8.3.15 Using PH3 as GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 8.4 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 8.4.1 GPIO port mode register (GPIOx_MODER) (x =A to E and H) . . . . . . 267 8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A to E and H) 268 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A to E and H) . . . . . . 269 8.4.6 GPIO port output data register (GPIOx_ODR) (x = A to E and H) . . . . 269 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A to E and H) . . 270 8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to E and H) . . . . . . 273 8.4.12 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 9 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 276 9.1 SYSCFG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 9.2 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 9.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . . . . . . . 276 9.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 277 9.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
RM0394 Contents 9.2.4 SYSCFG extemnal interrupt configuration register 2 (SYSCFG EXTICR2) ..280 9.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG EXTICR3) 281 926 SYSCFG extemnal interrupt configuration register 4 (SYSCFG EXTICR4) 283 9.2.7 SYSCFG SRAM2 control and status register(SYSCFG_SCSR) 284 9.2.8 SYSCFG configuration register 2(SYSCFG CFGR2)............285 929 SYSCFG SRAM2 write protection register(SYSCFG SWPR).. ..286 9.2.10 SYSCFG SRAM2 key register(SYSCFG_SKR) 286 9.2.11 SYSCFG register map. .287 Peripherals interconnect matrix 288 10.1 Introduction............ 288 10.2 Connection summary.................................... 288 10.3 Interconnection details 289 10.3.1 2er (TM/TM2/M15/TM1)tomer (TIM1/M2TM15/TM1) 10.3.2 From timer (TIM1/TIM2/TIM6/TIM15)and EXTI to ADC (ADC1).....290 10.3.3 From ADC(ADC1)to timer (TIM1) 290 10.3.4 From timer (TIM2/TIM6/TIM7)and EXTI to DAC(DAC1/DAC2) 10.3.5 From HSE,LSE,LSI.MSI.MCO.RTC to timer(TIM2/TIM15/TIM16).291 103.6 From RTC,COMP1,COMP2 to low-power timer(LPTIM1/LPTIM2)..291 10.3.7 2. 292 10.3.8 From ADC(ADC1)to ADC(ADC2)..........................292 10.3.9 From USB to timer (TIM2) 292 10.3.10 nal analog source to ADC (ADC1)and OPAMP ,293 10.3.11 1/COMP2)to timers 293 10.312 From system errors to timers (TIM1/TIM15/TIM16) 294 10.3.13 From timers (TIM16)to IRTIM.... .294 Direct memory access controller(DMA) 295 11.1 Introduction 295 11.2 DMA main features........... 295 11.3 DMA implementation 296 11.3.1 DMA1 and DMA2 296 7 RM0394 Rev4 9/1600
RM0394 Rev 4 9/1600 RM0394 Contents 43 9.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 9.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 9.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 9.2.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR) . . . . 284 9.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 285 9.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR) . . . . . . 286 9.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR) . . . . . . . . . . . . . . . . . 286 9.2.11 SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 10 Peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 10.2 Connection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 10.3 Interconnection details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 10.3.1 From timer (TIM1/TIM2/TIM15/TIM16) to timer (TIM1/TIM2/TIM15/TIM16) 289 10.3.2 From timer (TIM1/TIM2/TIM6/TIM15) and EXTI to ADC (ADC1) . . . . . 290 10.3.3 From ADC (ADC1) to timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 10.3.4 From timer (TIM2/TIM6/TIM7) and EXTI to DAC (DAC1/DAC2) . . . . . 290 10.3.5 From HSE, LSE, LSI, MSI, MCO, RTC to timer (TIM2/TIM15/TIM16) . 291 10.3.6 From RTC, COMP1, COMP2 to low-power timer (LPTIM1/LPTIM2) . . 291 10.3.7 From timer (TIM1/TIM2/TIM15) to comparators (COMP1/COMP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.3.8 From ADC (ADC1) to ADC (ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.3.9 From USB to timer (TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.3.10 From internal analog source to ADC (ADC1) and OPAMP (OPAMP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 10.3.11 From comparators (COMP1/COMP2) to timers (TIM1/TIM2/TIM15/TIM16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 10.3.12 From system errors to timers (TIM1/TIM15/TIM16) . . . . . . . . . . . . . . . 294 10.3.13 From timers (TIM16) to IRTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 295 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 11.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 11.3 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 11.3.1 DMA1 and DMA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Contents RM0394 1132 DMA request mapping 296 11.4 DMA functional description. 299 114.1 DMA block diagram 114.2 DMA transfers. 309 114.3 DMA arbitration 301 14.4 DMA channels 302 11.4.5 DMA data width,alignment and endianness................ .306 1146 DMA error management 307 11.5 DMA interrupts....,.................. 。。。。。。 308 11.6 DMA registers 308 11.6.1 DMA interrupt status register(DMA_ISR). 308 11.6.2 DMA interrupt flag clear register(DMA_IFCR) 311 11.6.3 DMA channel x configuration register (DMA CCRx)........ 312 1164 DMA channel x number of data to transfer register (DMA CNDTRx).315 11.6.5 DMA channel x peripheral address register (DMA_CPARx) 11.6.6 DMA channel x memory address register(DMA_CMARx) .........316 116 7 DMA channel selection register (DMA CSELR) 317 11.6.8 DMA register map and reset values 317 Nested vectored interrupt controller(NVIC)................. 320 12.1 NVIC main features........................................ 320 12.2 SysTick calibration value register 320 12.3 Interrupt and exception vectors 321 13 Extended interrupts and events controller(EXTI)............... 325 13.1 Introduction..... 325 13.2 EXTI main features........................................ 325 13.3 EXTI functional description 325 13.3.1 EXTI block diagram .326 1332 Wakeup event management 13.3.3 Peripherals asynchronous Interrupts...................... 13.3.4 Hardware interrupt selection 13.35 Hardware event selection 327 13.3.6 Software interrupt/event selection........................... .327 13.4 EXTI interrupt/event line mapping............................ 327 13.5 EXTI registers 330 10/1600 RM0394 Rev4 7
Contents RM0394 10/1600 RM0394 Rev 4 11.3.2 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 11.4 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 11.4.1 DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 11.4.2 DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 11.4.3 DMA arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 11.4.4 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 11.4.5 DMA data width, alignment and endianness . . . . . . . . . . . . . . . . . . . . 306 11.4.6 DMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 11.5 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 11.6 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 11.6.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 308 11.6.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 311 11.6.3 DMA channel x configuration register (DMA_CCRx) . . . . . . . . . . . . . . 312 11.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx) . 315 11.6.5 DMA channel x peripheral address register (DMA_CPARx) . . . . . . . . 315 11.6.6 DMA channel x memory address register (DMA_CMARx) . . . . . . . . . 316 11.6.7 DMA channel selection register (DMA_CSELR) . . . . . . . . . . . . . . . . . 317 11.6.8 DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 317 12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 320 12.1 NVIC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 12.2 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 12.3 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 13 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . 325 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 13.2 EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 13.3 EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 13.3.1 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 13.3.2 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 13.3.3 Peripherals asynchronous Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 327 13.3.4 Hardware interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 13.3.5 Hardware event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 13.3.6 Software interrupt/event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 13.4 EXTI interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 13.5 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
