ARM Cortex-M4 Processor Revision:r0p1 Technical Reference Manual ARM copmge200,20n98i620l5Agsesened
ARM® Cortex® -M4 Processor Revision: r0p1 Technical Reference Manual Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. ARM 100166_0001_00_en
ARM Cortex'-M4 Processor ARM Cortex-M4 Processo Technical Reference Manual Release Information Document History Issue Date Confidentiality Change A 22 December 2009 Non-Confidential First release for rop 02 March 2010 Non-Confidential Second release 29June2010 Non-Confidential First release for ropl D 11Junc2013 Non-Confidential Second release for rp 0001-00 23 February 2015 Non-Confidential Document source updated to comply with DITA standards. BTAXnbercthagodo1o166olbwiegaoaveSoato Non-Confidential Proprietary Notice This document is protccted by coovrisht and other related rights and the practice or implementation of the information contained in this documn may be protcted bynmore patentso pending patent application Nopar of this document may be ARM.,by Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents. THIS DOCUMENT IS PROVIDED "AS IS"ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES EXPRESS,IMPLIED OR STATUTORY,INCLUDING,WITHOUT LIMITATION,THE IMPLIED WARRANTIES OF MERCHANTABILITY,SATISFACTORY QUALITY,NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR This document may include technical inaccuracies or typographical errors. TO THE EXTENT NOT PROHIBITED BY LAW IN NO EVENT WILL ARM BE LIABLE FORANY DAMAGES INCLUDING WITHOUT LIMITATION ANY DIRECT,INDIRECT,SPECIAL,INCIDENTAL,PUNITIVE,OR CONSEQUENTIAL DAMAGES,HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,ARISING USE OF THIS DOCUMENT EVEN IF ARM HAS BEEN ADVISED OF OF SUCH This document onsolyof commritems You shall be responsible for ening that anyseduplicationr disclosure of to this document any time and without notice. English version of this document and any translation,the terms of the English version of the Agreement shall prevail. owners.Please follow ARM's trademark usage guidelines at hp:/www.arm.cow/about/trademark-usage-gmridelines php ARM Limited.Company 02557590 registered in England ARM100166_0001_00_en copy7gre20c9,2010318a05MW临sened
ARM® Cortex® -M4 Processor Technical Reference Manual Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. Release Information Document History Issue Date Confidentiality Change A 22 December 2009 Non-Confidential First release for r0p0 B 02 March 2010 Non-Confidential Second release for r0p0 C 29 June 2010 Non-Confidential First release for r0p1 D 11 June 2013 Non-Confidential Second release for r0p1 0001-00 23 February 2015 Non-Confidential Document source updated to comply with DITA standards. Document number changed to 100166 following conversion to DITA-XML. Non-Confidential Proprietary Notice This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of ARM. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated. Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents. THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, ARM makes no representation with respect to, and has undertaken no analysis to identify or understand the scope and content of, third party patents, copyrights, trade secrets, or other rights. This document may include technical inaccuracies or typographical errors. TO THE EXTENT NOT PROHIBITED BY LAW, IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING OUT OF ANY USE OF THIS DOCUMENT, EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is not exported, directly or indirectly, in violation of such export laws. Use of the word “partner” in reference to ARM’s customers is not intended to create or refer to any partnership relationship with any other company. ARM may make changes to this document at any time and without notice. If any of the provisions contained in these terms conflict with any of the provisions of any signed written agreement covering this document with ARM, then the signed written agreement prevails over and supersedes the conflicting provisions of these terms. This document may be translated into other languages for convenience, and you agree that if there is any conflict between the English version of this document and any translation, the terms of the English version of the Agreement shall prevail. Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited or its affiliates in the EU and/or elsewhere. All rights reserved. Other brands and names mentioned in this document may be the trademarks of their respective owners. Please follow ARM’s trademark usage guidelines at http://www.arm.com/about/trademark-usage-guidelines.php Copyright © [2009, 2010, 2013, 2015], ARM Limited or its affiliates. All rights reserved. ARM Limited. Company 02557590 registered in England. ARM® Cortex® -M4 Processor ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 2 Non-Confidential
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110 Fulbourn Road, Cambridge, England CB1 9NJ. LES-PRE-20349 Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to. Unrestricted Access is an ARM internal classification. Product Status The information in this document is Final, that is for a developed product. Web Address http://www.arm.com ARM® Cortex® -M4 Processor ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 3 Non-Confidential
Contents ARM Cortex-M4 Processor Technical Reference Manual Preface About this book Feedback Chapter 1 Introduction 1.1 About the processor.-12 1.2 Features.. .1-13 13 Extemal interfaces .1-14 Confiaurable ontions .1-15 1.5 Product documentation. 1-16 1.6 Product revisions. .1-19 Chapter2 Functional Description 2.1 About the functions. 2-21 22 Processor features ...... .2-22 23 Interfaces...... .2-24 Chapter3 Programmers'Model 31 3.2 2 model Modes of o 3-29 33 r memory mod ARM100166_0001_00_en Non-Co
Contents ARM® Cortex® -M4 Processor Technical Reference Manual Preface About this book ...................................................... ...................................................... 7 Feedback .................................................................................................................... 10 Chapter 1 Introduction 1.1 About the processor ................................................................................................ 1-12 1.2 Features .................................................................................................................. 1-13 1.3 External interfaces ................................................. ................................................. 1-14 1.4 Configurable options ................................................................................................ 1-15 1.5 Product documentation ............................................................................................ 1-16 1.6 Product revisions .................................................. .................................................. 1-19 Chapter 2 Functional Description 2.1 About the functions .................................................................................................. 2-21 2.2 Processor features .................................................................................................. 2-22 2.3 Interfaces ........................................................ ........................................................ 2-24 Chapter 3 Programmers’ Model 3.1 About the programmers’ model ....................................... ....................................... 3-28 3.2 Modes of operation and execution .......................................................................... 3-29 3.3 Instruction set summary .......................................................................................... 3-30 3.4 Processor memory model ........................................................................................ 3-40 ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 4 Non-Confidential
3.5 Write buffer 3-43 3.6 Exclusive monitor. 34 Bit-banding 345 3.8 Processor core register summary 3-47 3.9 Exceptions 3-49 Chapter4 System Control 4.1 System control registers. 452 Auxiliary Control Register,ACTLR. ,454 3 CPUID Base Register.CPUID. 455 4.4 Auxiliary Fault Status Register,AFSR. 456 Chapter 5 Memory Protection Unit About the MPU MPU programmers model table Chapter 6 Nested Vectored Interrupt Controller 61 NVIC functional description. 6-62 6.2 NVIC programmers'model 6-63 Chapter 7 Floating-Point Unit 7.1 About the FPU.. 7-66 7.2 FPU functional description 7-67 7.3 FPU programmers'model 7.72 Chapter 8 Debug ccess port Chapter 9 Data Watchpoint and Trace Unit 9.1 DWT functional description. .9-85 9.2 DWT Programmers'model L9-86 Chapter 10 Instrumentation Trace Macrocell Unit 10.1 ITM functional description... 10-89 10.2 ITM programmers'model.. …10-90 10.3 ITM Trace Privilege Register,ITM_TPR. 10-91 Chapter 11 Trace Port Interface Unit u the TPIU Jhnctonalcescnipton TPIU programmers'model 11-96 Appendix A Revisions A.1 Revisions Appx-A-107 RM100166000100en 0opyvmere209,2010318a05hSMWw6sened
3.5 Write buffer .............................................................................................................. 3-43 3.6 Exclusive monitor .................................................................................................... 3-44 3.7 Bit-banding .............................................................................................................. 3-45 3.8 Processor core register summary ............................................................................ 3-47 3.9 Exceptions ....................................................... ....................................................... 3-49 Chapter 4 System Control 4.1 System control registers .......................................................................................... 4-52 4.2 Auxiliary Control Register, ACTLR .......................................................................... 4-54 4.3 CPUID Base Register, CPUID ........................................ ........................................ 4-55 4.4 Auxiliary Fault Status Register, AFSR .................................. .................................. 4-56 Chapter 5 Memory Protection Unit 5.1 About the MPU ........................................................................................................ 5-58 5.2 MPU functional description ...................................................................................... 5-59 5.3 MPU programmers model table ....................................... ....................................... 5-60 Chapter 6 Nested Vectored Interrupt Controller 6.1 NVIC functional description .......................................... .......................................... 6-62 6.2 NVIC programmers’ model ...................................................................................... 6-63 Chapter 7 Floating-Point Unit 7.1 About the FPU .................................................... .................................................... 7-66 7.2 FPU functional description ........................................... ........................................... 7-67 7.3 FPU programmers’ model ........................................... ........................................... 7-72 Chapter 8 Debug 8.1 Debug configuration ................................................................................................ 8-74 8.2 AHB-AP debug access port .......................................... .......................................... 8-79 8.3 Flash Patch and Breakpoint Unit (FPB) ................................. ................................. 8-82 Chapter 9 Data Watchpoint and Trace Unit 9.1 DWT functional description ...................................................................................... 9-85 9.2 DWT Programmers’ model ...................................................................................... 9-86 Chapter 10 Instrumentation Trace Macrocell Unit 10.1 ITM functional description ...................................................................................... 10-89 10.2 ITM programmers’ model ...................................................................................... 10-90 10.3 ITM Trace Privilege Register, ITM_TPR ................................................................ 10-91 Chapter 11 Trace Port Interface Unit 11.1 About the TPIU ...................................................................................................... 11-93 11.2 TPIU functional description .................................................................................... 11-94 11.3 TPIU programmers’ model .................................................................................... 11-96 Appendix A Revisions A.1 Revisions .................................................. .................................................. Appx-A-107 ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 5 Non-Confidential
Preface This preface introduces the ARM Cortex"-M4 Processor Technical Reference Mamual It contains the following: About this book on age 7. ·Feedback on page0 ARM100166_0001_00_en Copygh1gsve 6
Preface This preface introduces the ARM® Cortex® -M4 Processor Technical Reference Manual. It contains the following: • About this book on page 7. • Feedback on page 10. ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 6 Non-Confidential
About this ook About this book ARM Cortex-M4 Technical Reference Manual(TRM).This manual contains documentation for the Cmd.nmn Product revision status Identifies the major revision of the product,for example,rl. pn Identifies the minor revision or modification status of the product,for example,p2. Intended audience program Using this book This book is organized into the following chapters Chapter 1 Introduction This chapter in roduces the Cortex-M4 processor and instruction set,processor features and interfaces,configurable options,and product documentation. Chapter 2 Functional Description This chapter introduces the Cortex-M4 processor and its external interfaces. the Co ortex-M4 processor programmers'model. Chapter 4 System Control Chapter 5 Memory Protection Unit This chapter describes the processor Memory Protection Unit(MPU). interrupt handling,and controls power management. e programmers'model of the Floating-Point Unit (FPU). Chapter 8 Debug This chapter describes how to debug and test software running on the processor Chapter 11 Trace Port Interface Unit This chapter describes the Cortex-M4 TPIU,the Trace Port Interface Unit that is specific to the Cortex-M4 processor. ARM100166000100en opygh1ghtsv
About this book ARM Cortex-M4 Technical Reference Manual (TRM). This manual contains documentation for the Cortex-M4 processor, the programmer’s model, instruction set, registers, memory map,floating point, multimedia, trace and debug support. Product revision status The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2, where: rm Identifies the major revision of the product, for example, r1. pn Identifies the minor revision or modification status of the product, for example, p2. Intended audience This manual is written to help system designers, system integrators, verification engineers, and software programmers who are implementing a System-on-Chip (SoC) device based on the Cortex® -M4 processor. Using this book This book is organized into the following chapters: Chapter 1 Introduction This chapter introduces the Cortex-M4 processor and instruction set, processor features and interfaces, configurable options, and product documentation. Chapter 2 Functional Description This chapter introduces the Cortex-M4 processor and its external interfaces. Chapter 3 Programmers’ Model This chapter describes the Cortex-M4 processor programmers’ model. Chapter 4 System Control This chapter provides a summary of the system control registers whose implementation is specific to the Cortex-M4 processor. Chapter 5 Memory Protection Unit This chapter describes the processor Memory Protection Unit (MPU). Chapter 6 Nested Vectored Interrupt Controller This chapter describes the Nested Vectored Interrupt Controller (NVIC). The NVIC provides configurable interrupt handling abilities to the processor, facilitates low- latency exception and interrupt handling, and controls power management. Chapter 7 Floating-Point Unit This chapter describes the programmers’ model of the Floating-Point Unit (FPU). Chapter 8 Debug This chapter describes how to debug and test software running on the processor. Chapter 9 Data Watchpoint and Trace Unit This chapter describes the Data Watchpoint and Trace (DWT) unit. Chapter 10 Instrumentation Trace Macrocell Unit This chapter describes the Instrumentation Trace Macrocell (ITM) unit. Chapter 11 Trace Port Interface Unit This chapter describes the Cortex-M4 TPIU, the Trace Port Interface Unit that is specific to the Cortex-M4 processor. Appendix A Revisions The technical changes between released issues of this manual. Preface About this book ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 7 Non-Confidential
boo Glossary The ARM Glossary is a list of terms used in ARM documentation,together with definitions for those terms.The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning. See the ARMGlossary for more information. Typographic conventions italie Introduces special terminology,denotes cross-references,and citations. bold Highlight ce elements,such as menu names.Denotes signal names.Also used for terms list monospace Denotes text that you can enter at the keyboard,such as commands,file and program names, and source code. tted abb instead of the full command or option name. and or option.You can enter the underlined text monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value onosp language key ords when used outside example code Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example MRC p15,0 ,,, SMALL CAPITALS Timing diagrams The following figure explains the components used in timing diagrams.Variations,when they occur. haveclear labels.You must not assume any timing information that is not explicit in the diagrams. Shade Clock☐ HIGH to LOW Transient HIGHLOW to HIGH Bus stable Busto high impedance Bus change High impedance to stable bus Figure 1 Key to timing diagram conventions Signals The signal conventions are ARM100166_0001_00_en 8
Glossary The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning. See the ARM Glossary for more information. Typographic conventions italic Introduces special terminology, denotes cross-references, and citations. bold Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate. monospace Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code. monospace Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name. monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value. monospace bold Denotes language keywords when used outside example code. Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example: MRC p15, 0 , , , SMALL CAPITALS Used in body text for a few terms that have specific technical meanings, that are defined in the ARM glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE. Timing diagrams The following figure explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams. Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation. Clock HIGH to LOW Transient HIGH/LOW to HIGH Bus stable Bus to high impedance Bus change High impedance to stable bus Figure 1 Key to timing diagram conventions Signals The signal conventions are: Preface About this book ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 8 Non-Confidential
About thisbook Signal level The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means .HIGH for active-HIGH signals. LOW for active-LOW signals. hered ofme denoe Lower-case Additional reading This book contains information that is specific to this product.See the following documents for other relevant information. 7-MArchicre Reference Ma(ARM) M4 and Imp ARM DII 0239) Re HB-I v1.0)(A RM AMBA3 APB Protocol on (ARM IHI ence Ma ARM DDI0314) ARM D ication (ARM H00 Cortex-M4 Lay Stacking and Context Switehing Application Note 29 (ARM DA10298). Other publications IEEE Standard [Test Access Port and Boundary-Scan Architecture 1149.1-2001 (JTAG) .IEEE Standard [EEE Standard for Binary Floating-Point Arithmetic]754-2008. ARM100166000100en opygh1ghtsv 9
Signal level The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means: • HIGH for active-HIGH signals. • LOW for active-LOW signals. Lower-case n At the start or end of a signal name denotes an active-LOW signal. Additional reading This book contains information that is specific to this product. See the following documents for other relevant information. ARM publications • ARMv7-M Architecture Reference Manual (ARM DDI 0403). • ARM® Cortex-M4 Integration and Implementation Manual (ARM DII 0239). • ARM ETM-M4 Technical Reference Manual (ARM DDI 0440). • ARM AMBA® 3 AHB-Lite Protocol (v1.0) (ARM IHI 0033). • ARM AMBA 3 APB Protocol Specification (ARM IHI 0024). • ARM CoreSight™ Components Technical Reference Manual (ARM DDI 0314). • ARM Debug Interface v5 Architecture Specification (ARM IHI 0031). • Cortex-M4 Lazy Stacking and Context Switching Application Note 298 (ARM DAI0298). Other publications • IEEE Standard [Test Access Port and Boundary-Scan Architecture ]1149.1-2001 (JTAG). • IEEE Standard [IEEE Standard for Binary Floating-Point Arithmetic] 754-2008. Preface About this book ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 9 Non-Confidential
Pc Feedback Feedback on this product If you have any commentsor sugestions about this product.contact your suppler and give The product name. The product revision or version An expla ation with as much information as you can provide.Include symptoms and diagnostic procedures if appropriate Feedback on content If you have comments on content then send an e-mail toerrrcmGive: The titl The number ARM 100166_0001_00_en. The page number(s)to which your comments refer A concise explanation of your comments. ARMalso welcomes general suggestions for additions and improvements Note ARM100166_0001_00_en coapy7gne20o9,2010,2018305AdMAWngses9ned 10
Feedback Feedback on this product If you have any comments or suggestions about this product, contact your supplier and give: • The product name. • The product revision or version. • An explanation with as much information as you can provide. Include symptoms and diagnostic procedures if appropriate. Feedback on content If you have comments on content then send an e-mail to errata@arm.com. Give: • The title. • The number ARM 100166_0001_00_en. • The page number(s) to which your comments refer. • A concise explanation of your comments. ARM also welcomes general suggestions for additions and improvements. Note ARM tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the represented document when used with any other PDF reader. Preface Feedback ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 10 Non-Confidential