4位二进制加法计数器74163 具有同步复位,同步置数和进位控制功能 library ieee, use ieee std logic arith. all entity k74163 is port( clk, clrl, ldl, enp, ent: in std logic: d in unsigned (3 downto 0); g out unsigned (3 downto 0); rco: out std logic) end K74163 architecture beh of k74 163 is signal iq: unsigned (3 downto 0) process(clk, ent, iq) if clk'event and clk='l'then if clrl=o then iq<=(others=>0) elsif (ent and enp)='I then iq<=iq d if if(iq=15)and(ent=I")then rco<=l else rco<=O nd if end process end beh 将上述程序中的iq=iq-1,就构成减法计数器4 位二进制加法计数器 74163 具有同步复位，同步置数和进位控制功能； library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity k74163 is port ( clk,clrl,ldl,enp,ent: in std_logic; d: in unsigned (3 downto 0); q: out unsigned (3 downto 0); rco:out std_logic); end k74163; architecture beh of k74163 is signal iq: unsigned (3 downto 0); begin process (clk,ent,iq) begin if clk'event and clk='1' then if clrl='0' then iq<= (others=>'0'); elsif ldl='0' then iq<=d; elsif (ent and enp)='1' then iq<=iq+1; end if; end if; if (iq=15) and (ent='1') then rco<='1'; else rco<='0'; end if; q<=iq; end process; end beh; 将上述程序中的 iq<=iq-1，就构成减法计数器；