aaa process( current state, X case current state Is when s0=> if x=o' then z<=o' next state<=s0 else z<='l. next state<=s2: end if when sl=> if xo' then z<=0, next state<=sO else z<=0, next state<=s2: end if when s2=> if xeo then z<='I next state<=s2 else z<=o'- next state<=s3: end if when s3=> if x=o' then z<=o'. next state<=s3 else z<='l next state<=sl: end end process aaa sync process be wait until clk'event and clkel current state<=next state end process sync, end beh counter计数器 计数器通常以ck信号为基本输入,对输入信号进行计数: 在clk每个周期中改变一次计数器状态,状态可以输出; 经过n次计数后,计数器将回到初始状态,并给出进位输 出信号 计数器的ⅤHDL设计的要点在于正确安排状态的变化次 序,以及满足类型及运算的相容性; 例1p708表8-14aaa:process(current_state,x) begin case current_state is when s0=> if x='0' then z<='0';next_state<=s0; else z<='1';next_state<=s2; end if; when s1=> if x='0' then z<='0';next_state<=s0; else z<='0';next_state<=s2; end if; when s2=> if x='0' then z<='1';next_state<=s2; else z<='0';next_state<=s3; end if; when s3=> if x='0' then z<='0';next_state<=s3; else z<='1';next_state<=s1; end if; end case; end process aaa; sync:process begin wait until clk'event and clk='1'; current_state<=next_state; end process sync; end beh; counter 计数器 计数器通常以 clk 信号为基本输入，对输入信号进行计数： 在 clk 每个周期中改变一次计数器状态，状态可以输出； 经过 n 次计数后，计数器将回到初始状态，并给出进位输 出信号； 计数器的 VHDL 设计的要点在于正确安排状态的变化次 序，以及满足类型及运算的相容性； 例 1 p.708 表 8-14