Sequential PLD Timing Parameters Sequential PLD Timing Parameters ◆ More features eac二XC ● a registered PLD utput is fed back to a register the same P ◆ Timing parameters e tpo: PD(propagation delay) from input to the comb. output e tco: PD from the rising edge of CLK to output tcF- PD from the rising edge of cLK to a macrocell's registered output that connect back to a feedback input e tsu&tH: setup time hold time of filip-flops Sequential PLD Timing Parameters GAL16V行地址杓 ◆ Internal feed back ◆行地址映射图 ●第0-31共32行,每行64位,对应64个积项 ●第32行 电子标签,Es >8个 Bytes以内任意字符,作为标识 EXternal feedback Input or served for Manufactur ● a registered PLD gistered PLD GAL16V行地址地构 GAL编霍 ◆行地址映射图 ◆结构控制字,各OLMC具体配置 ●第60行,82Bits结构控制字,控制各OLMC配置 ●GAL开发软件根据设计输入自动完成编译配置 64位乘积项止位 ●不必人工设置 Xor(n)}8位 ◆描述方式 Ac1(m}8位;Ac1位;Syn1位 ●逻辑方程 >1Bit,加密单元(ES不受影响 ●真值表 状态图 >Reserved for Manufacturer 电路图 ●第63行:整体擦除位6 33 Sequential PLD Timing Parameters ‹More features ‹Timing parameters z tPD: PD(propagation delay) from input to the comb. output z tCO: PD from the rising edge of CLK to output z tCF: PD from the rising edge of CLK to a macrocell’s registered output that connect back to a feedback input z tSU & tH : setup time & hold time of flip-flops tPD Input or feedback Combinational output tCF CLK Registered feedback tSU 1/ fmax Inernal feedback 34 Sequential PLD Timing Parameters ‹Internal feedback z a registered PLD output is fed back to a register in the same PLD tCF CLK Registered feedback tSU 1/ fmax Inernal feedback 35 Sequential PLD Timing Parameters ‹Internal feedback ‹External feedback z a registered PLD output is connected to the input of another registered PLD with similar timing tCO CLK Registered feedback Input or feedback tSU tH 1/ fmax External feedback tCF CLK Registered feedback tSU 1/ fmax Inernal feedback 36 GAL16V8行地址结构 ‹行地址映射图 z第0～31共32行，每行64位，对应64个积项 z第32行 ¾ 电子标签，ES ¾ 8个Bytes以内任意字符，作为标识 z第33～59 ¾ Reserved for Manufacturer 0 1 2 3 4 5 6 7 0 1 2 3 … … … … 30 31 I 1 O1 37 GAL16V8行地址结构 ‹行地址映射图 z第60行，82Bits结构控制字，控制各OLMC配置 模式，可由用户编程 ¾64位乘积项禁止位； ¾Xor(n)—8位； ¾AC1(n)—8位； AC0—1位；Syn—1位 z第61行 ¾1Bit，加密单元 (ES不受影响) z第62行 ¾Reserved for Manufacturer z第63行: 整体擦除位 38 GAL编程 ‹结构控制字，各OLMC具体配置 zGAL开发软件根据设计输入自动完成编译配置 z不必人工设置 ‹描述方式 z逻辑方程 z真值表 z状态图 z电路图