t VGs=0, Ips= Ipss. This equation and the corresponding transfer curve can actually the gate-to-channel pn junction is forward-biased and the depletion region wid s be extended up to the point where VGs=+.5 V. In the region where 0< VGs<+0.5 gion width leads to a corresponding expansion of the conducting channel and thus (,iN an increase in Ips above Ipss. As long as the gate-to-channel forward bias voltage is less than about 0.5, the pn junction will be essentially"off"and very little gate current v will flow. If VGs is increased much above +0.5 V, however, the gate-to-channel pn junction will turn"on"and there will be a substantial flow of gate voltage IG. This gate FIGURE 24. 12 Effect current will load down the signal source and produce a voltage drop across the signal source resistance, as shown in Fig. 24.12. This voltage drop can cause Vas to be much smaller than the signal source voltage Vin. As Vin increases, VGs will ultimately level off at a forward bias voltage of about +0.7 V, and the signal source will lose control over VGs, and hence over Ips. This can result in severe distortion of the input signal in the form of clipping, and thus this situation should be avoided. Thus, although it is possible to increase Ips above Ipss by allowing the gate-to-channel junction to become forward-biased by a small amount($0.5 V), the possible benefits are generally far outweighed by the risk of signal distortion. Therefore, JFETs are almost always operated with the gate-to-channel pn junction reverse-biased. Transfer Conductance The slope of the transfer curve, dIps/dVGs, is the dynamic forward transfer conductance, or mutual transfer maximum when IDs=Ipss. Since Ips =Ioss[ 1-(VGs/Vp), 8m can be obtained es as Ips increases, reaching a ductance, 8m. We see that 8m starts off at zero when Vas Vp and increase d we have that 8m=2l √ Insel pss_,ls-I The maximum value of gm is obtained when Vas=0(Ips= Ipss)and is given by gm(VGs=0)=8no=2Ips/(Vp) Small-Signal AC Voltage Gain Let's consider the CS amplifier circuit of Fig 24.13. The input ac signal is DD applied between gate and source, and the output ac voltage is taken between drain and source. Thus the source electrode of this triode device is common to input and output, hence the designation of this JFET configuration as a a good choice of the dc operating point or quiescent point(Q point) or an amplifier is in the middle of the active region at IDs= Ipss/2. This vgG allows for the maximum symmetrical drain current swing, from the qui- escent level of Ipso= Ipss/2, down to a minimum of IDs =0, and up to a maximum of Ips= Ipss. This choice for the Q point is also a good one from FIGURE 24.13 Common-souI the standpoint of allowing for an adequate safety margin for the location amplifier. c 2000 by CRC Press LLC© 2000 by CRC Press LLC At VGS = 0, IDS = IDSS . This equation and the corresponding transfer curve can actually be extended up to the point where VGS @ +0.5 V. In the region where 0 < VGS < +0.5 V, the gate-to-channel pn junction is forward-biased and the depletion region width is reduced below the width under zero bias conditions. This reduction in the depletion region width leads to a corresponding expansion of the conducting channel and thus an increase in IDS above IDSS . As long as the gate-to-channel forward bias voltage is less than about 0.5 V, the pn junction will be essentially “off” and very little gate current will flow. If VGS is increased much above +0.5 V, however, the gate-to-channel pn junction will turn “on” and there will be a substantial flow of gate voltage IG . This gate current will load down the signal source and produce a voltage drop across the signal source resistance, as shown in Fig. 24.12. This voltage drop can cause VGS to be much smaller than the signal source voltage Vin . As Vin increases, VGS will ultimately level off at a forward bias voltage of about +0.7 V, and the signal source will lose control over VGS , and hence over IDS . This can result in severe distortion of the input signal in the form of clipping, and thus this situation should be avoided. Thus, although it is possible to increase IDS above IDSS by allowing the gate-to-channel junction to become forward-biased by a small amount (£0.5 V), the possible benefits are generally far outweighed by the risk of signal distortion. Therefore, JFETs are almost always operated with the gate-to-channel pn junction reverse-biased. Transfer Conductance The slope of the transfer curve, dID S /dVGS , is the dynamic forward transfer conductance, or mutual transfer conductance, gm . We see that gm starts off at zero when VGS = VP and increases as IDS increases, reaching a maximum when IDS = IDSS . Since IDS = IDSS[1 – (VG S /VP)]2 , gm can be obtained as Since we have that The maximum value of gm is obtained when VGS = 0 (IDS = IDSS) and is given by gm(VGS = 0) = gm0 = 2ID S /(–VP). Small-Signal AC Voltage Gain Let’s consider the CS amplifier circuit of Fig. 24.13. The input ac signal is applied between gate and source, and the output ac voltage is taken between drain and source. Thus the source electrode of this triode device is common to input and output, hence the designation of this JFET configuration as a CS amplifier. A good choice of the dc operating point or quiescent point (Q point) for an amplifier is in the middle of the active region at IDS = IDSS /2. This allows for the maximum symmetrical drain current swing, from the qui￾escent level of IDSQ = IDSS /2, down to a minimum of IDS @ 0, and up to a maximum of IDS = IDSS . This choice for the Q point is also a good one from the standpoint of allowing for an adequate safety margin for the location FIGURE 24.12 Effect of forward bias on VGS. g dI dV I V V V m DS GS DSS GS P P = = - Ê Ë Á ˆ ¯ ˜ - 2 1 1 - Ê Ë Á ˆ ¯ ˜ = V V I I GS P DS DSS g I I I V I I V m DSS DS DSS P DS DSS P = - = × - 2 2 / FIGURE 24.13 Common-source amplifier