《电子工程师手册》学习资料（英文版）chapter 24 Transistors.pdf_大学文库

24 Transistors 24.1 Junction Field-Effect Transistors FET Biasing. Transfer Characteristics. JFET Outpu Resistance. Source Follower. Frequency and Time-Domain Response. Voltage-Variable Resistor 24.2 Bipolar Transistors Biasing the Bipolar Transistor. Small-Signal Operation. A Small Signal Equivalent Circuit. Low-Frequency Performance. The Emitter-Follower or Common-Collector(CC) Circuit. The Sidney Soclof Common-Emitter Bypass Capacitor CE. High-Frequency California State University Response. Complete Response. Design Comments. Integrated Circuits. The Degenerate Common-Emitter Stage. The Difference Amplifier. The Current Mirror. The Difference Stage with Current Joseph Watson Mirror Biasing. The Current Mirror as a load University of Wales, Swansea 24.3 The Metal-Oxide Semiconductor Field-Effect (MOSFET) John R. Brews Current-Voltage Characteristics. Important Device The University of arizona Parameters. Limitations upon Miniaturization 24.1 Junction Field-Effect Transistors A junction field-effect transistor, or JFET, is a type of transistor in which the current flow through the device between the drain and source electrodes is controlled by the voltage applied to the gate electrode. a simple physical model of the JFET is shown in Fig. 24. 1. In this JFET an n-type conducting channel exists between drain and source. The gate is a p* region that surrounds the n-type channel. The gate-to-channel pn junction is normally kept reverse-biased. As the reverse bias voltage between gate and channel increases, the depletion region width increases, as shown in Fig. 24.2. The depletion region extends mostly into the n-type channel because of the heavy doping on the p+ side. The depletion region is depleted of mobile charge carriers and thus cannot contribute to the conduction of current between drain and source. Thus as the gate voltage increases, he cross-sectional areas of the n-type channel available for current flow decreases. This reduces the current flow between drain and source. As the gate voltage increases, the channel gets further constricted, and the current flow gets smaller. Finally when the depletion regions meet in the middle of the channel, as shown in Fig 24.3, the channel is pinched off in its entirety between source and drain. At this point the current flow between drain and source is reduced to essentially zero. This voltage is called the pinch-off voltage, Vp. The inch-off voltage is also represented by Vas (off)as being the gate-to-source voltage that turns the drain-to- source current Ips off. We have been considering here an n-channel JFET. The complementary device is the p-channel JFET that has an t gate region surrounding a p-type channel. The operation of a p-channel JFET is the same as for an n-channel device, except the algebraic signs of all dc voltages and currents are reversed We have been considering the case for Vos small compared to the pinch-off voltage such that the channel sentially uniform from drain to source, as shown in Fig. 24. 4(a). Now let's see what happens as Vos increases As an example let's assume an n-channel JFET with a pinch-off voltage of Vp=-4 V. we will see what happens C 2000 by CRC Press LLC

© 2000 by CRC Press LLC 24 Transistors 24.1 Junction Field-Effect Transistors JFET Biasing • Transfer Characteristics • JFET Output Resistance • Source Follower • Frequency and Time-Domain Response • Voltage-Variable Resistor 24.2 Bipolar Transistors Biasing the Bipolar Transistor • Small-Signal Operation • A SmallSignal Equivalent Circuit • Low-Frequency Performance • The Emitter-Follower or Common-Collector (CC) Circuit • The Common-Emitter Bypass Capacitor CE • High-Frequency Response • Complete Response • Design Comments • Integrated Circuits • The Degenerate Common-Emitter Stage • The Difference Amplifier • The Current Mirror • The Difference Stage with Current Mirror Biasing • The Current Mirror as a Load 24.3 The Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) Current-Voltage Characteristics • Important Device Parameters • Limitations upon Miniaturization 24.1 Junction Field-Effect Transistors Sidney Soclof A junction field-effect transistor, or JFET, is a type of transistor in which the current flow through the device between the drain and source electrodes is controlled by the voltage applied to the gate electrode. A simple physical model of the JFET is shown in Fig. 24.1. In this JFET an n-type conducting channel exists between drain and source. The gate is a p+ region that surrounds the n-type channel. The gate-to-channel pn junction is normally kept reverse-biased. As the reverse bias voltage between gate and channel increases, the depletion region width increases, as shown in Fig. 24.2. The depletion region extends mostly into the n-type channel because of the heavy doping on the p+ side. The depletion region is depleted of mobile charge carriers and thus cannot contribute to the conduction of current between drain and source. Thus as the gate voltage increases, the cross-sectional areas of the n-type channel available for current flow decreases. This reduces the current flow between drain and source. As the gate voltage increases, the channel gets further constricted, and the current flow gets smaller. Finally when the depletion regions meet in the middle of the channel, as shown in Fig. 24.3, the channel is pinched off in its entirety between source and drain. At this point the current flow between drain and source is reduced to essentially zero. This voltage is called the pinch-off voltage, VP . The pinch-off voltage is also represented by VGS (off) as being the gate-to-source voltage that turns the drain-tosource current IDS off. We have been considering here an n-channel JFET. The complementary device is the p-channel JFET that has an n+ gate region surrounding a p-type channel. The operation of a p-channel JFET is the same as for an n-channel device, except the algebraic signs of all dc voltages and currents are reversed. We have been considering the case for VDS small compared to the pinch-off voltage such that the channel is essentially uniform from drain to source, as shown in Fig. 24.4(a). Now let’s see what happens as VDS increases. As an example let’s assume an n-channel JFET with a pinch-off voltage of VP = –4 V. We will see what happens Sidney Soclof California State University, Los Angeles Joseph Watson University of Wales, Swansea John R. Brews The University of Arizona

PtGATE N-TYPE CHANNEL P+ GATE FIGURE 24.1 、 PT GATE PtGATE N-TYPE CHANNEL FIGURE 24.2 FIGURE 24. 3 for the case of VGs =0 as Vs increases In Fig. 24. 4(a)the situation is shown for the case of Vns=0 in which the JFET is fully""and there is a uniform channel from source to drain. This is at point A on the Ins vs. Vos curve of Fig. 24.5. The drain-to-source conductance is at its maximum value of gs(on), and the drain-to- source resistance is correspondingly at its minimum value of Tas (on). Now let's consider the case of Vns=+l V, shown in Fig. 24.4(b). The gate-to-channel bias voltage at the source end is still VGs=0. The gate-to-channel bias voltage at the drain end is VGp= VGs-Vos=-1 V, so the depletion region will be wider at the drain end of the channel than at the source end. the channel will thus be narrower at the drain end than at the source end, and this will result in a decrease in the channel conductance ga and, correspondingly, an increase in the channel resistance ras. So the slope of the Ips vs. Vos curve that corresponds to the channel conductance will be smaller at Vns=1 V than it was at Vns =0, as shown at point B on the Ips vS. Vrs curve of Fig. 24.5 In Fig. 24.4(c)the situation for Vns =+2 V is shown. The gate-to-channel bias voltage at the source end is still VGs =0, but the gate-to-channel bias voltage at the drain end is now VGp=VGs-Vps=-2V, so the depletion region will now be substantially wider at the drain end of the channel than at the source end. This leads to a further constriction of the channel at the drain end, and this will again result in a decrease in the channel conductance ga and, correspondingly, an increase in the channel resistance ras. So the slope of the Ips vs. Vos urve will be smaller at Vns=2V than it was at Vns=1 V, as shown at point Con the Ips vS Vns curve of Fig. 24 In Fig. 24. 4(d)the situation for Vps =+3 V is shown, and this corresponds to point d on the IIs vs. Vps curve of Fig. 24.5 When Vns=+4 V, the gate-to-channel bias voltage will be VGD=Vo-Vns =0-4V=-4 V= Vp. As a result the channel is now pinched off at the drain end but is still wide open at the source end since VGs=0,as nown in Fig. 24.4(e). It is very important to note that the channel is pinched off just for a very short distance at the drain end so that the drain -to-source current i can still continue to flow this is not at all the same situation as for the case of Vas= Vp, where the channel is pinched off in its entirety, all the way from source to drain. When this happens, it is like having a big block of insulator the entire distance between source and drain, and Ips is reduced to essentially zero. The situation for Vns=+4 V=-Vp is shown at point E on the Ips curve of Fig. 24.5 For Vps >+4 V, the current essentially saturates and doesnt increase much with further increases in Vps. As Vps increases above +4 V, the pinched-off region at the drain end of the channel gets wider, which increases Tas. This increase in ras essentially counterbalances the increase in Vps such that Ips does not increase much This region of the Ins vS. Vps curve in which the channel is pinched off at the drain end is called the active region and is also known as the saturated region. It is called the active region because when the JFET is to be sed as an amplifier, it should be biased and operated in this region. The saturated value of drain current up in the active region for the case of VGs=0 is called the drain saturation current, Ipss(the third subscript S c 2000 by CRC Press LLC

© 2000 by CRC Press LLC for the case of VGS = 0 as VDS increases. In Fig. 24.4(a) the situation is shown for the case of VDS = 0 in which the JFET is fully “on” and there is a uniform channel from source to drain. This is at point A on the IDS vs. VDS curve of Fig. 24.5. The drain-to-source conductance is at its maximum value of gds (on), and the drain-tosource resistance is correspondingly at its minimum value of rds (on). Now let’s consider the case of VDS = +1 V, as shown in Fig. 24.4(b). The gate-to-channel bias voltage at the source end is still VGS = 0. The gate-to-channel bias voltage at the drain end is VGD = VGS –VDS = –1 V, so the depletion region will be wider at the drain end of the channel than at the source end. The channel will thus be narrower at the drain end than at the source end, and this will result in a decrease in the channel conductance gds and, correspondingly, an increase in the channel resistance rds . So the slope of the IDS vs. VDS curve that corresponds to the channel conductance will be smaller at VDS = 1 V than it was at VDS = 0, as shown at point B on the IDS vs. VDS curve of Fig. 24.5. In Fig. 24.4(c) the situation for VDS = +2 V is shown. The gate-to-channel bias voltage at the source end is still VGS = 0, but the gate-to-channel bias voltage at the drain end is now VGD = VGS – VDS = –2 V, so the depletion region will now be substantially wider at the drain end of the channel than at the source end. This leads to a further constriction of the channel at the drain end, and this will again result in a decrease in the channel conductance gds and, correspondingly, an increase in the channel resistance rds . So the slope of the IDS vs. VDS curve will be smaller at VDS = 2 V than it was at VDS = 1 V, as shown at point C on the IDS vs.VDS curve of Fig. 24.5. In Fig. 24.4(d) the situation for VDS = +3 V is shown, and this corresponds to point D on the IDS vs. VDS curve of Fig. 24.5. When VDS = +4 V, the gate-to-channel bias voltage will be VGD = VGS – VDS = 0 – 4 V = –4 V = VP . As a result the channel is now pinched off at the drain end but is still wide open at the source end since VGS = 0, as shown in Fig. 24.4(e). It is very important to note that the channel is pinched off just for a very short distance at the drain end so that the drain-to-source current IDS can still continue to flow. This is not at all the same situation as for the case of VGS = VP , where the channel is pinched off in its entirety, all the way from source to drain. When this happens, it is like having a big block of insulator the entire distance between source and drain, and IDS is reduced to essentially zero. The situation for VDS = +4 V = –VP is shown at point E on the IDS vs. VDS curve of Fig. 24.5. For VDS > +4 V, the current essentially saturates and doesn’t increase much with further increases in VDS . As VDS increases above +4 V, the pinched-off region at the drain end of the channel gets wider, which increases rds . This increase in rds essentially counterbalances the increase in VDS such that IDS does not increase much. This region of the IDS vs. VDS curve in which the channel is pinched off at the drain end is called the active region and is also known as the saturated region. It is called the active region because when the JFET is to be used as an amplifier, it should be biased and operated in this region. The saturated value of drain current up in the active region for the case of VGS = 0 is called the drain saturation current, IDSS (the third subscript S FIGURE 24.1 FIGURE 24.2 FIGURE 24.3

ne basic requirement is that the gate-to-channel bias voltage at the drain end of the channel,Vp, be greater than the pinch-off voltage ipss Ve For the example under consideration with Vp=-4 V, this means Vos -Vs 2+4V. Thus, for Vas =0, the active region will begin at D Vps=+4 V When VG =-1 V, the active region will begin at Vps -3v +3V, for now VGd=-4 V. when VGs =-2 V, the active region begins -Av at Vos =+2 V, and when Vos=-3V, the active region begins at Vps +1V. The dotted line in Fig. 24.6 marks the boundary between the nonsaturated and active regions. FIGURE 24.6 The upper boundary of the active region is marked by the onset of the avalanche breakdown of the gate-to-channel pn junction. When Vos=0, this occurs at Vp Since Vog= Vns- VGs and breakdown occurs when Vxg= BVpg, as Vos increases the breakdown voltage decreases, as given by BVDG= BVos-VGs. Thus BVms= BVD+ VGs. For example, if the gate-to-channel breakdown volta is 50 V, the Vos breakdown voltage will start off at 50 V when Vo=0 but decrease to 46V when Va=-4V. In the nonsaturated region Ins is a function of both Vas and Vps and in the lower portion of the nonsaturated region where Vos is small compared to Vp, Ips becomes an approximately linear function of Vps. This linear portion of the nonsaturated is called the voltage-variable resistance(VvR)region, for in this region the JFET acts like a linear resistance element between source and drain The resistance is variable in that it is controlled by the gate voltage. This region and VvR application will be discussed in a later section. The JFET can also be operated in this region as a switch, and this will also be discussed in a later section JFET Biasing Voltage Source Biasing Now we will consider the biasing of JFETs for operation in the active region. The simplest biasing method is shown in Fig. 24.7, in which a voltage source VaG is used to provide the quiescent gate-to-source bias voltage VGso In the active region the transfer equation for the JFET has been given as Ins=Ipss[1-(VGs/Vp))2,so for a quiescent drain current of Ipso the corresponding gate voltage will be given by Voso=Vp (1- Ioso/Ipss. For a Q point in the middle of the active region, we have that Ipso= Ipss/2, so VGso=Vp(1-/1/2)=0.293 Vp VGG= The voltage source method of biasing has several major drawbacks. Since Vp ill have the opposite polarity of the drain supply voltage Vop, the gate bias voltag will require a second power supply. For the case of an n-channel JFET, Vpp FIGURE 24.7 Voltage come from a positive supply voltage and VGG must come from a separate negative source biasing power supply voltage or battery. A second, and perhaps more serious, problem is the"open-loop"nature of this biasing method. The JFET parameters of Ipps and p will exhibit very substantial unit-to-unit variations, often by as much as a 2: 1 factor. There is also a significant temperature dependence of Ipos and Vp. These riations will lead to major shifts in the position of the Q point and the resulting DIPs distortion of the signal. A much better biasing method is shown in Fig. 24.8 Self Biasing RG Rs Ips.Rs The biasing circuit of Fig 24.8 is called a self-biasing circuit in that the gate-to- source voltage is derived from the voltage drop produced by the flow of drain current through the source biasing resistor Rs. It is a closed-loop system in that variations in the JFET parameters can be partially compensated for by the biasing FIGURE 24.8 Self-biasing circuit. The gate resistor R is used to provide a dc return path for the gate leakage current and is generally up in the megohm range. The voltage drop across Rs is given by Vs= Ips. Rs. The voltage drop across the gate resistor RG is VG=IG RG. Since IG is usually in the low nanoampere or even picoampere range, as long as RG is not extremely large c 2000 by CRC Press LLC

© 2000 by CRC Press LLC the basic requirement is that the gate-to-channel bias voltage at the drain end of the channel, VGD , be greater than the pinch-off voltage VP . For the example under consideration with VP = –4 V, this means that VGD = VGS – VDS must be more negative than –4 V. Therefore, VDS – VGS ³ +4 V. Thus, for VGS = 0, the active region will begin at VDS = +4 V. When VGS = –1 V, the active region will begin at VDS = +3 V, for now VGD = –4 V. When VGS = –2 V, the active region begins at VDS = +2 V, and when VGS = –3 V, the active region begins at VDS = +1 V. The dotted line in Fig. 24.6 marks the boundary between the nonsaturated and active regions. The upper boundary of the active region is marked by the onset of the avalanche breakdown of the gate-to-channel pn junction. When VGS = 0, this occurs at VDS = BVDS = BVDG. Since VDG = VDS – VGS and breakdown occurs when VDG = BVDG , as VGS increases the breakdown voltage decreases, as given by BVDG = BVDS – VGS . Thus BVDS = BVDG + VGS. For example, if the gate-to-channel breakdown voltage is 50 V, the VDS breakdown voltage will start off at 50 V when VGS = 0 but decrease to 46 V when VGS = –4 V. In the nonsaturated region IDS is a function of both VGS and VDS, and in the lower portion of the nonsaturated region where VDS is small compared to VP , IDS becomes an approximately linear function of VDS . This linear portion of the nonsaturated is called the voltage-variable resistance (VVR) region, for in this region the JFET acts like a linear resistance element between source and drain. The resistance is variable in that it is controlled by the gate voltage. This region and VVR application will be discussed in a later section. The JFET can also be operated in this region as a switch, and this will also be discussed in a later section. JFET Biasing Voltage Source Biasing Now we will consider the biasing of JFETs for operation in the active region. The simplest biasing method is shown in Fig. 24.7, in which a voltage source VGG is used to provide the quiescent gate-to-source bias voltage VGSQ . In the active region the transfer equation for the JFET has been given as IDS = IDSS [1 – (VGS /VP)]2 , so for a quiescent drain current of IDSQ the corresponding gate voltage will be given by VGSQ = VP (1 – . For a Q point in the middle of the active region, we have that IDSQ = IDSS /2, so VGSQ = VP (1 – ) = 0.293 VP . The voltage source method of biasing has several major drawbacks. Since VP will have the opposite polarity of the drain supply voltage VDD, the gate bias voltage will require a second power supply. For the case of an n-channel JFET, VDD will come from a positive supply voltage and VGG must come from a separate negative power supply voltage or battery. A second, and perhaps more serious, problem is the “open-loop” nature of this biasing method. The JFET parameters of IDDS and VP will exhibit very substantial unit-to-unit variations, often by as much as a 2:1 factor. There is also a significant temperature dependence of IDDS and VP . These variations will lead to major shifts in the position of the Q point and the resulting distortion of the signal. A much better biasing method is shown in Fig. 24.8. Self-Biasing The biasing circuit of Fig. 24.8 is called a self-biasing circuit in that the gate-tosource voltage is derived from the voltage drop produced by the flow of drain current through the source biasing resistor RS . It is a closed-loop system in that variations in the JFET parameters can be partially compensated for by the biasing circuit. The gate resistor RG is used to provide a dc return path for the gate leakage current and is generally up in the megohm range. The voltage drop across RS is given by VS = IDS · RS . The voltage drop across the gate resistor RG is VG = IG · RG. Since IG is usually in the low nanoampere or even picoampere range, as long as RG is not extremely large FIGURE 24.6 FIGURE 24.7 Voltage source biasing. FIGURE 24.8 Self-biasing. IDSQ IDSS § 1 § 2

© 2000 by CRC Press LLC the voltage drop across RG can be neglected, so VG @ 0. Thus, we have that VGS = VG – VS @ –VS = –IDS · RS . For example, if IDSS = 10 mA and VP = –4 V, and for a Q point in the middle of the active region with IDSQ = IDS S /2 = 5 mA, we have that VGSQ = 0.293VP = –1.17 V. Therefore the required value for the source biasing resistor is given by RS = –VGS /IDSQ = 1.17 V/5 mA = 234 W. This produces a more stable quiescent point than voltage source biasing, and no separate negative power supply is required. The closed-loop nature of this biasing circuit can be seen by noting that if changes in the JFET parameters were to cause IDS to increase, the voltage drop across RS would also increase. This will produce an increase in VGS (in the negative direction for an n-channel JFET), which will act to reduce the increase in IDS . Thus the net increase in IDS will be less due to the feedback voltage drop produced by the flow of IDS through RS . The same basic action would, of course, occur for changes in the JFET parameters that would cause IDS to decrease. Bias Stability Now let’s examine the stability of the Q point. We will start again with the basic transfer equation as given by IDS = IDSS [1 – (VGS /VP)]2 . From this equation the change in the drain current, DIDS , due to changes in IDSS , VGS , and VP can be written as Since VGS = –IDS · RS , DVGS = –RS · DIDS , we obtain that Collecting terms in DIDS on the left side gives Now solving this for DIDS yields From this we see that the shift in the quiescent drain current, DIDS , is reduced by the presence of RS by a factor of 1 + gm RS . If IDS = IDSS /2, then Since VGS = 0.293VP , the source biasing resistor will be RS = –VG S /IDS = –0.293 VP /IDS . Thus so 1 + gm RS = 1.83. Thus the sensitivity of IDS due to changes in VP and IDSS is reduced by a factor of 1.83. DD D D I gV g V V V I I I DS m GS m GS P P DS DSS =- + DSS D D DD I gR I g V V V I I I DS m S DS m GS P P DS DSS =- - + DSS D DD I gR g V V V I I I DS m S m GS P P DS DSS DSS ( ) 1 + =- + D D D I gV V V I I I g R DS m GS P P DS DSS DSS m S = - + + ( ) / 1 g I I V I I V I V m DS DSS P DS DS P DS P = × - = × - = - 2 22 2 2 g R I V V I m S DS P P DS = - ¥ - =¥ = 2 2 0 293 2 2 0 293 0 83 . .

VDD SVDD RG2 Rs IDs.Rs RG RsSIDsRs FIGURE 24.9 FIGURE 24.10 FIGURE 24.11 Transfer characteristi The equation for AIos can now be written in the following form for the fractional change in Ips △IDs-=0.83AV/Vp)+14△ Ipss/lpss 1.83 so Alps/Ips=-045AVp/Vp)+0.77(Alpss/Ipss), and thus a 10% change in Vp will result in approximately a 4.5% change in Ips, and a 10% change in Ipss will result in an 8%change in Ins. Thus, although the situation is improved with the self-biasing circuit using Rs, there will still be a substantial variation in the quiescent current with changes in the JFET parameters A further improvement in bias stability can be obtained by the use of the biasing methods of Figs. 24.9 and 4. 10. In Fig. 24.9 a gate bias voltage VaG is obtained from the Vpp supply voltage by means of the RG-Ra2 voltage divider. The gate-to-source voltage is now VGs=VG-Vs= VGG-IpsRs. So now for Rs we have Rs (VGG-VGs)/Ips. Since Vas is of opposite polarity to VGG, this will result in a larger value for Rs than before. This in turn will result in a larger value for the gm rs product and hence improved bias stability. If we continue with the preceding examples and now let VGG= Vpp/2=+10 V, we have that Rs=(VGG-vgs)Ips [+10V-(1.17V)]/5 mA= 2.234 kQ2, as compared to Rs=234 Q2 that was obtained before. For gm we have gmt 2/ Ios. IDss/(-Vp)=3.54 mS, so 8m Rs=3.54 mS. 2.234 kQ2=7.90. Since 1+ 8mRs=8.90, we now have an improvement by a factor of 8.9 over the open-loop voltage source biasing and by a factor of 4.9 over the self biasing method without the Vog biasing of the gate. Another biasing method that can lead to similar results is the method shown in Fig. 24.10. In this method the bottom end of the source biasing resistor goes to a negative supply voltage Vss instead of to ground. The gate-to-source bias voltage is now given by VGs= VG-Vs=0-(Ips. Rs Vss)so that for Rs we now have Rs Vos- Vss)/Ips. If Vss =-10V, and as before Ips =5 mA and VGs =-1 17V, we have Rs=11.7v/5 mA 2.34 kQ2, and thus gm Rs=7.9 as in the preceding example. So this method does indeed lead to results similar 10% change in Vp will be only 0.9%, and the change in Ips due to a 10% change in IDss will be only 16% to that for the Rs and VGg combination biasing. With either of these two methods the change in Ips due to a The biasing circuits under consideration here can be applied directly to the common-source(CS)amplifier configuration, and can also be used for the common-drain(CD), or source-follower, and common-gate(CG) Transfer Characteristics Transfer Equation ow we will consider the transfer characteristics of the JFET, which is a graph of the output current Ips vS the input voltage VGs in the active region. In Fig. 24. 11 a transfer characteristic curve for a JFET with Vp=-4 V and Ipss =+10 mA is given. This is approximately a square-law relationship as given by Ips=Ipss[1-(VGs/Vp) This equation is not valid for VGs beyond Ve (i.e, VGs< Vp), for in this region the channel is pinched off and c 2000 by CRC Press LLC

© 2000 by CRC Press LLC The equation for DIDS can now be written in the following form for the fractional change in IDS : so DID S /IDS = –0.45 (DVP /VP) + 0.77 (DIDS S /IDSS), and thus a 10% change in VP will result in approximately a 4.5% change in IDS , and a 10% change in IDSS will result in an 8% change in IDS . Thus, although the situation is improved with the self-biasing circuit using RS , there will still be a substantial variation in the quiescent current with changes in the JFET parameters. A further improvement in bias stability can be obtained by the use of the biasing methods of Figs. 24.9 and 24.10. In Fig. 24.9 a gate bias voltage VGG is obtained from the VDD supply voltage by means of the RG1–RG2 voltage divider. The gate-to-source voltage is now VGS = VG – VS = VGG – IDSRS . So now for RS we have RS = (VGG – VGS)/IDS . Since VGS is of opposite polarity to VGG, this will result in a larger value for RS than before. This in turn will result in a larger value for the gm RS product and hence improved bias stability. If we continue with the preceding examples and now let VGG = VDD /2 = +10 V, we have that RS = (VGG – VGS)/IDS = [+10V –(–1.17V)]/5 mA = 2.234 kW, as compared to RS = 234 W that was obtained before. For gm we have gm = = 3.54 mS, so gm RS = 3.54 mS · 2.234 kW = 7.90. Since 1 + gm RS = 8.90, we now have an improvement by a factor of 8.9 over the open-loop voltage source biasing and by a factor of 4.9 over the selfbiasing method without the VGG biasing of the gate. Another biasing method that can lead to similar results is the method shown in Fig. 24.10. In this method the bottom end of the source biasing resistor goes to a negative supply voltage VSS instead of to ground. The gate-to-source bias voltage is now given by VGS = VG –VS = 0 – (IDS · RS + VSS) so that for RS we now have RS = (–VGS – VSS)/IDS . If VSS = –10 V, and as before IDS = 5 mA and VGS = –1.17 V, we have RS = 11.7 V/5 mA = 2.34 kW, and thus gm RS = 7.9 as in the preceding example. So this method does indeed lead to results similar to that for the RS and VGG combination biasing. With either of these two methods the change in IDS due to a 10% change in VP will be only 0.9%, and the change in IDS due to a 10% change in IDSS will be only 1.6%. The biasing circuits under consideration here can be applied directly to the common-source (CS) amplifier configuration, and can also be used for the common-drain (CD), or source-follower, and common-gate (CG) JFET configurations. Transfer Characteristics Transfer Equation Now we will consider the transfer characteristics of the JFET, which is a graph of the output current IDS vs. the input voltage VGS in the active region. In Fig. 24.11 a transfer characteristic curve for a JFET with VP = –4 V and IDSS = +10 mA is given. This is approximately a square-law relationship as given by IDS = IDSS [1 – (VG S /VP)]2 . This equation is not valid for VGS beyond VP (i.e., VGS < VP), for in this region the channel is pinched off and IDS @ 0. FIGURE 24.9 FIGURE 24.10 FIGURE 24.11 Transfer characteristic. DI D D I V V I I DS DS P P DSS DSS = -0 83 + 1 41 1 83 . ( ) . ( ) . / / 2 IDS IDSS × –VP § ( )

t VGs=0, Ips= Ipss. This equation and the corresponding transfer curve can actually the gate-to-channel pn junction is forward-biased and the depletion region wid s be extended up to the point where VGs=+.5 V. In the region where 0< VGs<+0.5 gion width leads to a corresponding expansion of the conducting channel and thus (,iN an increase in Ips above Ipss. As long as the gate-to-channel forward bias voltage is less than about 0.5, the pn junction will be essentially"off"and very little gate current v will flow. If VGs is increased much above +0.5 V, however, the gate-to-channel pn junction will turn"on"and there will be a substantial flow of gate voltage IG. This gate FIGURE 24. 12 Effect current will load down the signal source and produce a voltage drop across the signal source resistance, as shown in Fig. 24.12. This voltage drop can cause Vas to be much smaller than the signal source voltage Vin. As Vin increases, VGs will ultimately level off at a forward bias voltage of about +0.7 V, and the signal source will lose control over VGs, and hence over Ips. This can result in severe distortion of the input signal in the form of clipping, and thus this situation should be avoided. Thus, although it is possible to increase Ips above Ipss by allowing the gate-to-channel junction to become forward-biased by a small amount($0.5 V), the possible benefits are generally far outweighed by the risk of signal distortion. Therefore, JFETs are almost always operated with the gate-to-channel pn junction reverse-biased. Transfer Conductance The slope of the transfer curve, dIps/dVGs, is the dynamic forward transfer conductance, or mutual transfer maximum when IDs=Ipss. Since Ips =Ioss[ 1-(VGs/Vp), 8m can be obtained es as Ips increases, reaching a ductance, 8m. We see that 8m starts off at zero when Vas Vp and increase d we have that 8m=2l √ Insel pss_,ls-I The maximum value of gm is obtained when Vas=0(Ips= Ipss)and is given by gm(VGs=0)=8no=2Ips/(Vp) Small-Signal AC Voltage Gain Let's consider the CS amplifier circuit of Fig 24.13. The input ac signal is DD applied between gate and source, and the output ac voltage is taken between drain and source. Thus the source electrode of this triode device is common to input and output, hence the designation of this JFET configuration as a a good choice of the dc operating point or quiescent point(Q point) or an amplifier is in the middle of the active region at IDs= Ipss/2. This vgG allows for the maximum symmetrical drain current swing, from the qui- escent level of Ipso= Ipss/2, down to a minimum of IDs =0, and up to a maximum of Ips= Ipss. This choice for the Q point is also a good one from FIGURE 24.13 Common-souI the standpoint of allowing for an adequate safety margin for the location amplifier. c 2000 by CRC Press LLC

© 2000 by CRC Press LLC At VGS = 0, IDS = IDSS . This equation and the corresponding transfer curve can actually be extended up to the point where VGS @ +0.5 V. In the region where 0 < VGS < +0.5 V, the gate-to-channel pn junction is forward-biased and the depletion region width is reduced below the width under zero bias conditions. This reduction in the depletion region width leads to a corresponding expansion of the conducting channel and thus an increase in IDS above IDSS . As long as the gate-to-channel forward bias voltage is less than about 0.5 V, the pn junction will be essentially “off” and very little gate current will flow. If VGS is increased much above +0.5 V, however, the gate-to-channel pn junction will turn “on” and there will be a substantial flow of gate voltage IG . This gate current will load down the signal source and produce a voltage drop across the signal source resistance, as shown in Fig. 24.12. This voltage drop can cause VGS to be much smaller than the signal source voltage Vin . As Vin increases, VGS will ultimately level off at a forward bias voltage of about +0.7 V, and the signal source will lose control over VGS , and hence over IDS . This can result in severe distortion of the input signal in the form of clipping, and thus this situation should be avoided. Thus, although it is possible to increase IDS above IDSS by allowing the gate-to-channel junction to become forward-biased by a small amount (£0.5 V), the possible benefits are generally far outweighed by the risk of signal distortion. Therefore, JFETs are almost always operated with the gate-to-channel pn junction reverse-biased. Transfer Conductance The slope of the transfer curve, dID S /dVGS , is the dynamic forward transfer conductance, or mutual transfer conductance, gm . We see that gm starts off at zero when VGS = VP and increases as IDS increases, reaching a maximum when IDS = IDSS . Since IDS = IDSS[1 – (VG S /VP)]2 , gm can be obtained as Since we have that The maximum value of gm is obtained when VGS = 0 (IDS = IDSS) and is given by gm(VGS = 0) = gm0 = 2ID S /(–VP). Small-Signal AC Voltage Gain Let’s consider the CS amplifier circuit of Fig. 24.13. The input ac signal is applied between gate and source, and the output ac voltage is taken between drain and source. Thus the source electrode of this triode device is common to input and output, hence the designation of this JFET configuration as a CS amplifier. A good choice of the dc operating point or quiescent point (Q point) for an amplifier is in the middle of the active region at IDS = IDSS /2. This allows for the maximum symmetrical drain current swing, from the quiescent level of IDSQ = IDSS /2, down to a minimum of IDS @ 0, and up to a maximum of IDS = IDSS . This choice for the Q point is also a good one from the standpoint of allowing for an adequate safety margin for the location FIGURE 24.12 Effect of forward bias on VGS. g dI dV I V V V m DS GS DSS GS P P = = - Ê Ë Á ˆ ¯ ˜ - 2 1 1 - Ê Ë Á ˆ ¯ ˜ = V V I I GS P DS DSS g I I I V I I V m DSS DS DSS P DS DSS P = - = × - 2 2 / FIGURE 24.13 Common-source amplifier

FIGURE 24.14 Transfer characteristi of the actual Q point due to the inevitable variations in device and component characteristics and values. This safety margin should keep the Q point well away from the extreme limits of the active region, and thus ensure operation of the JFET in the active region under most conditions. If Ipss =+10 mA, then a good choice for the Q point would thus be around +5.0 mA. If Vp=-4 V, then 2√5mA·10mA 3.54mA/V=3.54mS If a small ac signal voltage vas is superimposed on the dc gate bias voltage VGs, only a small segment of the transfer characteristic adjacent to the Q point will be traversed, as shown in Fig. 24.14. This small segment will be close to a straight line, and as a result the ac drain current ids will have a waveform close to that of the ac voltage applied to the gate. The ratio of in, to vGs will be the slope of the transfer curve as given by ia, / vgs dps/dvgs=8m. Thus ia,= 8mVGs If the net load driven by the drain of the JFET is the drain load resistor R, as shown in Fig. 24.13, then the ac drain current ids will produce an ac drain voltage of vas =-ids Rp Sin ids=8m,VGs, this becomes vas=-8m vs. Rp. The ac small-signal voltage gain from gate to drain thus becomes Av=vo/vin=vas /vs=-8mt Rp. The negative sign indicates signal inversion as is the case for a CS amplifier. If the dc drain supply voltage is VDp=+20 V, a quiescent drain-to-source voltage of Vpso= Vpp/2=+10 V will result in the JFET being biased in the middle of the active region. Since Inso =+5 mA in the example under consideration, the voltage drop across the drain load resistor Rp is 10 V. Thus Rp= 10 V/5 mA=2 kQ2. The ac mall-signal voltage gain Ay thus becomes Ay =-8mRp=-354 mS 2 kQ2=-707 Note that the voltage gain is relatively modest as compared to the much larger voltage gains that can be obtained in a bipolar-junction transistor(BJT) common-emitter amplifier. This is due to the lower transfer conductance of both JFETs and MOSFETs(metal-oxide semiconductor field-effect transistors) as compared to BJTs. For a BJT the transfer conductance is given by gm =Ic/Vr, where Ic is the quiescent collector current and Vr=klq= 25 mV is the thermal voltage. At Ic=5 mA, 8m=5 mA/25 mV=200 mS, as compared to only 3.5 mS for the JFET in this mple. With a net load of 2 kQ2, the BJT voltage gain will be -400 as compared to the JFET voltage gain of only 7. 1. Thus FETs do have the disadvantage of a much lower transfer conductance, and therefore vol gain, than BJTs operating under similar quiescent current levels, but they do have the major advantage much higher input impedance and a much lower input current. In the case of a ]FET the input signal is applied to the reverse-biased gate-to-channel pn junction and thus sees a very high impedance In the case of a common- emitter B]T amplifier, the input signal is applied to the forward-biased base-emitter junction, and the input impedance is given approximately by in =BE=1.5.B. V/Ic If Ic=5 mA and p=200, for example, then Ii=1500 Q2. This moderate input resistance value of 1.5 kQ2 is certainly no problem if the signal source resistance is less than around 100 Q2. However, if the source resistance is above 1 kQ, then there will be a substantial signal loss in the coupling of the signal from the signal source to the base of the transistor. If the source resistance is in the range of above 100 kQ, and certainly if it is above 1 MQ, then there will be severe signal attenuation lue to the BJT input impedance, and the FET amplifier will probably offer a greater overall voltage gain. Indeed, when high-impedance signal sources are encountered, a multistage amplifier with a FET input stage followed by cascaded B]T stages is often used c 2000 by CRC Press LLC

© 2000 by CRC Press LLC of the actual Q point due to the inevitable variations in device and component characteristics and values. This safety margin should keep the Q point well away from the extreme limits of the active region, and thus ensure operation of the JFET in the active region under most conditions. If IDSS = +10 mA, then a good choice for the Q point would thus be around +5.0 mA. If VP = –4 V, then If a small ac signal voltage vGS is superimposed on the dc gate bias voltage VGS , only a small segment of the transfer characteristic adjacent to the Q point will be traversed, as shown in Fig. 24.14. This small segment will be close to a straight line, and as a result the ac drain current ids will have a waveform close to that of the ac voltage applied to the gate. The ratio of ids to vGS will be the slope of the transfer curve as given by id s/vGS @ dID S /dVGS = gm . Thus ids @ gm vGS . If the net load driven by the drain of the JFET is the drain load resistor R D, as shown in Fig. 24.13, then the ac drain current ids will produce an ac drain voltage of vds = –ids · RD. Since ids = gm vGS , this becomes vds = –gm vGS · R D. The ac small-signal voltage gain from gate to drain thus becomes AV = vO /vin = vd s/vGS = –gm · RD . The negative sign indicates signal inversion as is the case for a CS amplifier. If the dc drain supply voltage is VDD = +20 V, a quiescent drain-to-source voltage of VDSQ = VDD /2 = +10 V will result in the JFET being biased in the middle of the active region. Since IDSQ = +5 mA in the example under consideration, the voltage drop across the drain load resistor RD is 10 V. Thus RD = 10 V/5 mA = 2 kW. The ac small-signal voltage gain AV thus becomes AV = –gm · RD = –3.54 mS · 2 kW = –7.07. Note that the voltage gain is relatively modest as compared to the much larger voltage gains that can be obtained in a bipolar-junction transistor (BJT) common-emitter amplifier. This is due to the lower transfer conductance of both JFETs and MOSFETs (metal-oxide semiconductor field-effect transistors) as compared to BJTs. For a BJT the transfer conductance is given by gm = IC /VT , where IC is the quiescent collector current and VT = kT/q @ 25 mV is the thermal voltage. At IC = 5 mA, gm = 5 mA/25 mV = 200 mS, as compared to only 3.5 mS for the JFET in this example. With a net load of 2 kW, the BJT voltage gain will be –400 as compared to the JFET voltage gain of only 7.1. Thus FETs do have the disadvantage of a much lower transfer conductance, and therefore voltage gain, than BJTs operating under similar quiescent current levels, but they do have the major advantage of a much higher input impedance and a much lower input current. In the case of a JFET the input signal is applied to the reverse-biased gate-to-channel pn junction and thus sees a very high impedance. In the case of a commonemitter BJT amplifier, the input signal is applied to the forward-biased base-emitter junction, and the input impedance is given approximately by rin = rBE @ 1.5 · b · VT /IC. If IC = 5 mA and b = 200, for example, then rin @ 1500 W. This moderate input resistance value of 1.5 kW is certainly no problem if the signal source resistance is less than around 100 W. However, if the source resistance is above 1 kW, then there will be a substantial signal loss in the coupling of the signal from the signal source to the base of the transistor. If the source resistance is in the range of above 100 kW, and certainly if it is above 1 MW, then there will be severe signal attenuation due to the BJT input impedance, and the FET amplifier will probably offer a greater overall voltage gain. Indeed, when high-impedance signal sources are encountered, a multistage amplifier with a FET input stage followed by cascaded BJT stages is often used. FIGURE 24.14 Transfer characteristic. g I I V m DS DSS P = × - = × = = 2 2 5 10 3 54 3 54 mA mA 4 V . . mA/V mS

AVDD RNET CCl 2 RGS RSS FIGURE 24.15 Effect of ras on Rnet FIGURE 24. 16 Active load circuit JFET Output Resistance Dynamic Drain-to-Source Condt For the JFET in the active region the drain current Ips is a strong function of the gate-to-source voltage VGs but is relatively independent of the drain-to-source voltage Vps. The transfer equation has previously been stated as Ins Ioss [1-(vGs/vp))2. The drain current will, however, increase slowly with increasing Vps. To take this dependence of Ips on Vps into account, the transfer equation can be modified to give where VA is a constant called the Early voltage and is a parameter of the transistor with units of volts. The early voltage V is generally in the range of 30 to 300 V for most JFETs. The variation of the drain current with drain voltage is the result of the channel length modulation effect in which the channel length decreases as the drain voltage increases. This decrease in the channel length results in an increase in the drain current. In BJTs a similar effect is the base width modulation effec The dynamic drain-to-source conductance is defined as gas, =dps/dvps and can be obtained from the modified transfer equation Ips=Ioss [1-(VGs/Vp)2[1+ Vps/Va as simply gds=Ios/Va. The reciprocal of &, is dynamic drain-to-source resistance ras, so ras=1/ gds=VA/IDs. If, for example, VA= 100 V, we have that ras =100 V/ID At Ips=1 mA, ras =100 V/l mA= 100 kQ, and at Ips= 10 mA, Tds =10 kQ2 Equivalent Circuit Model of CS Amplifier Stage A small-signal equivalent circuit model of a CS FET amplifier stage is shown in Fig. 24.15. The ac small-signal oltage gain is given by Ay =-8m Rnet where rnet=[rarp rl]is the net load driven by the drain for the ET and includes the dynamic drain-to-source resistance Tas. Since tas, is generally much larger than [RDRil,it will usually be the case that R =[RR, 1, and T, can be neglected. There are, however, some cases in which must be taken into account. This is especially true for the case in which an active load is used, as shown in Fig.24.16.For this case Rnet =[tasllralRi, and Tas can be a limiting factor in determining the voltage gain Consider an example for the active load circuit of Fig. 24.16 for the case of identical JFETs with the same quiescent current. Assume that RL > Tas so that Rnet [ramla]= VA/(2IpsQ). Let Ipso= Ipss/2, so 8m -2 IDss. oso/(Ip)=2/2loso/(Vp). The voltage gain is Vp If VA=100V and Vp=-2 V, we obtain Ay=-70, so we see that with active loads relatively large voltage gains can be obtained with Fets c 2000 by CRC Press LLC

© 2000 by CRC Press LLC JFET Output Resistance Dynamic Drain-to-Source Conductance For the JFET in the active region the drain current IDS is a strong function of the gate-to-source voltage VGS but is relatively independent of the drain-to-source voltage VDS . The transfer equation has previously been stated as IDS = IDSS [1 – (VG S /VP)]2 . The drain current will, however, increase slowly with increasing VDS . To take this dependence of IDS on VDS into account, the transfer equation can be modified to give where VA is a constant called the Early voltage and is a parameter of the transistor with units of volts. The early voltage VA is generally in the range of 30 to 300 V for most JFETs. The variation of the drain current with drain voltage is the result of the channel length modulation effect in which the channel length decreases as the drain voltage increases. This decrease in the channel length results in an increase in the drain current. In BJTs a similar effect is the base width modulation effect. The dynamic drain-to-source conductance is defined as gds = dID S /dVDS and can be obtained from the modified transfer equation IDS = IDSS [1 – (VG S /VP)]2 [1 + VD S /VA] as simply gds = ID S /VA. The reciprocal of gds is dynamic drain-to-source resistance rds , so rds = 1/gds = VA /IDS . If, for example, VA = 100 V, we have that rds = 100 V/IDS . At IDS = 1 mA, rds = 100 V/1 mA = 100 kW, and at IDS = 10 mA, rds = 10 kW. Equivalent Circuit Model of CS Amplifier Stage A small-signal equivalent circuit model of a CS FET amplifier stage is shown in Fig. 24.15. The ac small-signal voltage gain is given by AV = –gm · Rnet , where Rnet = [rds**RD **RL] is the net load driven by the drain for the FET and includes the dynamic drain-to-source resistance rds. Since rds is generally much larger than [RD**RL], it will usually be the case that Rnet @ [RD**RL], and rds can be neglected. There are, however, some cases in which rds must be taken into account. This is especially true for the case in which an active load is used, as shown in Fig. 24.16. For this case Rnet = [rds1**rds2**RL], and rds can be a limiting factor in determining the voltage gain. Consider an example for the active load circuit of Fig. 24.16 for the case of identical JFETs with the same quiescent current. Assume that RL >> rds so that Rnet @ [rds1**rds2] = VA/(2IDSQ). Let IDSQ = IDSS /2, so gm = – . The voltage gain is If VA = 100 V and VP = –2 V, we obtain AV = –70, so we see that with active loads relatively large voltage gains can be obtained with FETs. FIGURE 24.15 Effect of rds on Rnet. FIGURE 24.16 Active load circuit. I I V V V V DS DSS GS P DS A = - Ê Ë Á ˆ ¯ ˜ + Ê Ë Á ˆ ¯ ˜ 1 1 2 2 IDSS × IDSQ –VP § ( ) 2 2IDSQ –VP = § ( ) A g R I V V I V V V m DSQ P A DSQ A P = - × net = ¥ = 2 2 2 2