Blackwell, G.R. " Surface Mount Technology The Electrical Engineering Handbook Ed. Richard C. Dorf Boca raton crc Press llc. 2000
Blackwell, G.R. “Surface Mount Technology” The Electrical Engineering Handbook Ed. Richard C. Dorf Boca Raton: CRC Press LLC, 2000
26 Surface mount Technology 26.1 Introduction 26.2 Definition and Considerations Considerations in the Implementation of SMT 26.3 SMT Design, Assembly, and Test Overview 26.4 Surface Mount Device(SMD)Definitions 26.5 Substrate Design Guidelines 26.6 Thermal Design Considerations 26.7 Adhesive 26.8 Solder Paste and Joint Formation 26.9 Parts Inspection and Placement 6.10 Reflow Soldering Glenn r. blackwell 26.11 Cleanin Purdue University .6. 12 Prototype Systems 26.1 Introduction This section on surface mount technology(SMT)will familiarize the reader with the process steps in a successful SMT design. The new user of SMT is referred to Mims [1987] and Leibson [1987] for introductory material. Being successful with the implementation of SMT means the engineers involved must commit to the principles of concurrent engineering. It also means that a continuing commitment to a quality techniques is necessary, whether that is Taguchi, TQM, SPC, DOE, another technique, or a combination of several quality techniques, lest you too have quality problems with SMT(Fig. 26.1) 26.2 Definition and Considerations SMT is a collection of scientific and engineering methods needed to design, build, and test products made with electronic components that mount to the surface of the printed circuit board without holes for leads [ Higgins 1991]. This definition notes the breadth of topics necessary to understand SMT, and also clearly says that the successful implementation of SMT will require the use of concurrent engineering [ Classon, 1993; Shina, 1991] Concurrent engineering means that a team of design, manufacturing, test, and marketing people will concern hemselves with board layout, parts and parts placement issues, soldering, cleaning, test, rework, and packaging before any product is made. The careful control of all these issues improves both yield and reliability of the final product. In fact, SMT cannot be reasonably implemented without the use of concurrent engineering, and/or the principles contained in Design for Manufacturability(DFM)and Design for Testability(DFT), and therefore any facility that has not embraced these principles should do so if implementation of SmT is its goal c 2000 by CRC Press LLC
© 2000 by CRC Press LLC 26 Surface Mount Technology 26.1 Introduction 26.2 Definition and Considerations Considerations in the Implementation of SMT 26.3 SMT Design, Assembly, and Test Overview 26.4 Surface Mount Device (SMD) Definitions 26.5 Substrate Design Guidelines 26.6 Thermal Design Considerations 26.7 Adhesives 26.8 Solder Paste and Joint Formation 26.9 Parts Inspection and Placement Parts Placement 26.10 Reflow Soldering Post-Reflow Inspection 26.11 Cleaning 26.12 Prototype Systems 26.1 Introduction This section on surface mount technology (SMT) will familiarize the reader with the process steps in a successful SMT design. The new user of SMT is referred to Mims [1987] and Leibson [1987] for introductory material. Being successful with the implementation of SMT means the engineers involved must commit to the principles of concurrent engineering. It also means that a continuing commitment to a quality techniques is necessary, whether that is Taguchi, TQM, SPC, DOE, another technique, or a combination of several quality techniques, lest you too have quality problems with SMT (Fig. 26.1). 26.2 Definition and Considerations SMT is a collection of scientific and engineering methods needed to design, build, and test products made with electronic components that mount to the surface of the printed circuit board without holes for leads [Higgins, 1991]. This definition notes the breadth of topics necessary to understand SMT, and also clearly says that the successful implementation of SMT will require the use of concurrent engineering [Classon, 1993; Shina, 1991]. Concurrent engineering means that a team of design, manufacturing, test, and marketing people will concern themselves with board layout, parts and parts placement issues, soldering, cleaning, test, rework, and packaging, before any product is made. The careful control of all these issues improves both yield and reliability of the final product. In fact, SMT cannot be reasonably implemented without the use of concurrent engineering, and/or the principles contained in Design for Manufacturability (DFM) and Design for Testability (DFT), and therefore any facility that has not embraced these principles should do so if implementation of SMT is its goal. Glenn R. Blackwell Purdue University
Considerations in the Implementation of SMT Main reasons to consider implementation of SMT include: reduction in circuit board weight reduction in number of layers in the circuit board reduction in trace lengths on the circuit board, with DISTANCE orrespondingly shorter signal transit times and sOLDER LAND However, not all these reductions may occur in any given FIGURE 26.1 Placement misalignment of an SMT product redesign from through-hole technology(THT)to chip resistor( Source: Phillips Semiconductors, Surface SMT. Mount Process and Application Notes, Sunnyvale, Calif: Most companies that have not converted to SMT are Phillips Semiconductors, 1991. With permission. considering doing so. All is of course not golden in SMT and. During the assembly of a through-hole board, either the component leads go through the holes do not, and the component placement machines can typically detect the difference in force involved SMT board assembly, the placement machine does not have such direct feedback, and accuracy of final placement becomes a stochastic(probability-based)process, dependent on such items as component pad design, ccuracy of the PCB artwork and fabrication which affects the accuracy of trace location, accuracy of solder paste deposition location and deposition volume, accuracy of adhesive deposition location and volume if adhesive is used, accuracy of placement machine vision system(s), variations in component sizes from the assumed sizes, and thermal issues in the solder reflow process. In THT test, there is a through-hole at every potential test point, making it easy to align a bed-of-nails tester. In Smt designs, there are not holes corre- sponding to every device lead. The design team must consider form, fit and function, time-to-market, existing capabilities, testing, rework capabilities, and the cost and time to characterize a new process when deciding on a change of technologies 26.3 SMT Design, Assembly, and Test Overview Circuit design(not covered in this chapter) Substrate [typically Printed Circuit Board(PCB)) design Thermal design considerations Bare PCB fabrication and tests(not covered in this chapter) Application of adhesive, if necessary Application of solder 1 Placement of components in solder paste Reflowing of solder pa Cleaning, if necessary Testing of populated PCB(not covered in this chapter) Once circuit design is complete, substrate design and fabrication, most commonly of a printed circuit board (PCB),enters the process. Generally, PCB ass mbly configurations using surface mount devices(SMDs)are classified as shown in Fig. 26.2. Type I-only SMDs are used, typically on both sides of the board. No through-hole components are used. Top and bottom may contain both large and small active and passive SMDs. This type board uses refo Type II-a double-sided board, with SMDs on both sides. The top side may have all sizes of active and passive SMDs, as well as through-hole components, while the bottom side carries passive SMDs and
© 2000 by CRC Press LLC Considerations in the Implementation of SMT Main reasons to consider implementation of SMT include: • reduction in circuit board size • reduction in circuit board weight • reduction in number of layers in the circuit board • reduction in trace lengths on the circuit board, with correspondingly shorter signal transit times and potentially higher-speed operation However, not all these reductions may occur in any given product redesign from through-hole technology (THT) to SMT. Most companies that have not converted to SMT are considering doing so. All is of course not golden in SMT Land. During the assembly of a through-hole board, either the component leads go through the holes or they do not, and the component placement machines can typically detect the difference in force involved. During SMT board assembly, the placement machine does not have such direct feedback, and accuracy of final soldered placement becomes a stochastic (probability-based) process, dependent on such items as component pad design, accuracy of the PCB artwork and fabrication which affects the accuracy of trace location, accuracy of solder paste deposition location and deposition volume, accuracy of adhesive deposition location and volume if adhesive is used, accuracy of placement machine vision system(s), variations in component sizes from the assumed sizes, and thermal issues in the solder reflow process. In THT test, there is a through-hole at every potential test point, making it easy to align a bed-of-nails tester. In SMT designs, there are not holes corresponding to every device lead. The design team must consider form, fit and function, time-to-market, existing capabilities, testing, rework capabilities, and the cost and time to characterize a new process when deciding on a change of technologies. 26.3 SMT Design, Assembly, and Test Overview • Circuit design (not covered in this chapter) • Substrate [typically Printed Circuit Board (PCB)] design • Thermal design considerations • Bare PCB fabrication and tests (not covered in this chapter) • Application of adhesive, if necessary • Application of solder paste • Placement of components in solder paste • Reflowing of solder paste • Cleaning, if necessary • Testing of populated PCB (not covered in this chapter) Once circuit design is complete, substrate design and fabrication, most commonly of a printed circuit board (PCB), enters the process. Generally, PCB assembly configurations using surface mount devices (SMDs) are classified as shown in Fig. 26.2. Type I — only SMDs are used, typically on both sides of the board. No through-hole components are used. Top and bottom may contain both large and small active and passive SMDs. This type board uses reflow soldering only. Type II — a double-sided board, with SMDs on both sides. The top side may have all sizes of active and passive SMDs, as well as through-hole components, while the bottom side carries passive SMDs and FIGURE 26.1 Placement misalignment of an SMT chip resistor. (Source: Phillips Semiconductors, Surface Mount Process and Application Notes, Sunnyvale, Calif.: Phillips Semiconductors, 1991. With permission.)
Type I H Hh CommeNts Type I H Type Ill Intel does not recommond active devices be im in solder wan FIGURE 26. 2 Type I, Il, and III SMT circuit boards. Source: Intel Corporation, Packaging, Santa Clara, Calif: Intel Corporation, 1994. with permission. small active components such as transistors. This type board requires both reflow and wave soldering, and will require placement of bottom-side SMDs in adhesive Type Ill- top side has only through-hole components, which may be active and/or passive, while the bottom side has passive and small active SMDs. This type board uses wave soldering only, and also requires placement of the bottom-side SMDs in adhesive. It should be noted that with the ongoing increase in usage of various techniques to place IC dice directly on circuit boards, Type III in some articles means a mix of packaged SMT ICs and bare die on the same board. A Type I bare board will first have solder paste applied component pads on the board paste has been deposited, active and passive parts are placed in the paste For prototype and low-volume lines this can be done with manually guided X-Y tables using vacuum needles to hold the components, while in medium and high-volume lines automated placement equipment is used. This equipment will pick parts from c 2000 by CRC Press LLC
© 2000 by CRC Press LLC small active components such as transistors. This type board requires both reflow and wave soldering, and will require placement of bottom-side SMDs in adhesive. Type III — top side has only through-hole components, which may be active and/or passive, while the bottom side has passive and small active SMDs. This type board uses wave soldering only, and also requires placement of the bottom-side SMDs in adhesive. It should be noted that with the ongoing increase in usage of various techniques to place IC dice directly on circuit boards, Type III in some articles means a mix of packaged SMT ICs and bare die on the same board. A Type I bare board will first have solder paste applied to the component pads on the board. Once solder paste has been deposited, active and passive parts are placed in the paste. For prototype and low-volume lines this can be done with manually guided X–Y tables using vacuum needles to hold the components, while in medium and high-volume lines automated placement equipment is used. This equipment will pick parts from FIGURE 26.2 Type I, II, and III SMT circuit boards. (Source: Intel Corporation, Packaging, Santa Clara, Calif.: Intel Corporation, 1994. With permission.)
reels, sticks, or trays, then place the components at the appropriate pad locations on the board, hence the term pick and place"equipment. After all parts are placed in the solder paste, the entire assembly enters a reflow oven to raise the temperature of the assembly high enough to reflow the solder paste and create acceptable solder joints at the component d/pad transitions Reflow ovens most commonly use convection and Ir heat to heat the assembly above the point of solder liquidus, which for 63/37 tin-lead eutectic solder is 183.C. Due to the much higher thermal conductivity of the solder paste compared to the IC body, reflow soldering temperatures are reached at the leads/pads before the IC chip itself reaches damaging temperatures. The board is inverted and the process repeated. If mixed-technology Type II is being produced, the board will then be inverted, an adhesive will be dispensed at the centroid of each SMD, parts placed, the adhesive cured, the assembly re-righted, through-hole components mounted, and the circuit assembly will then be wave-soldered which will create acceptable solder joints for both the through-hole components and bottom-side SMDs A Type Ill board will first be inverted, adhesive dispensed, SMDs placed on the bottom-side of the board, the adhesive cured, the board re-righted, through-hole components placed, and the entire assembly wave- soldered. It is imperative to note that only passive components and small active SMDs can be successfully bottom-side wave-soldered without considerable experience on the part of the design team and the board assembly facility. It must also be noted that successful wave soldering of SMDs requires a dual-wave machine with one turbulent wave and one laminar wave It is common for a manufacturer of through-hole boards to convert first to a Type II or Type III substrate design before going to an all-SMD Type I design. This is especially true if amortization of through-hole insertion and wave-soldering equipment is necessary. Many factors contribute to the reality that most boards are mixed- technology Type II or Type III boards. While most components are available in SMT packages, through-hole onnectors are still commonly used for the additional strength the through-hole soldering process provides, and high-power devices such as three-terminal regulators are still commonly through-hole due to off-board heat-sinking demands. Both of these issues are actively being addressed by manufacturers and solutions exist which allow Type I boards with connectors and power devices [Holmes, 1993] Again, it is imperative that all members of the design, build, and test teams be involved from the design stage. Today's complex board designs mean that it is entirely possible to exceed the ability to adequately test a board if the test is not designed-in, or to robustly manufacture the board if in-line inspections and handling Or not adequately considered. Robustness of both test and manufacturing are only assured with full involvement of all parties to overall board design and productio It cannot be overemphasized that the speed with which packaging issues are moving requires anyone involved in SMT board or assembly issues to stay current and continue to learn about the processes. Subscribe to one or more of the industry-oriented journals noted in the"Further Information"section at the end of this Chapter, obtain any IC industry references, and purchase several SMT reference books. 26.4 Surface Mount Device(SMD)Definitions The new user of SMDs must rapidly learn the packaging sizes and types for SMDs Resistors, capacitors, and most other passive devices come in two-terminal packages which have end-terminations designed to rest on P SMD ICs come in a wide variety of packages, from 8-pin Small Outline Packages(SOLs)to 1000+ connection packages in a variety of sizes and lead configurations, as shown in Fig. 26.4. The most common commercial packages currently include Plastic Leaded Chip Carriers(PLCCs), Small Outline packages(SOs), Quad Flat Packs(QFPs), and Plastic Quad Flat Packs(PQFPs)also know as Bumpered Quad Flat Packs(BQFPs). Add in Tape Automated Bonding(TAB), Ball Grid Array(BGA)and other newer technologies, and the IC possibilities become overwhelming. Space prevents examples of all these technologies from being included here. The reader is referred to the standards of the Institute for Interconnecting and Packaging Electronic Circuits(IPc)to find the latest package standards, and to the proceedings of the most recent National Electronics Production and 'IPC, 7380 N. Lincoln Ave, Lincolnwood, IL 60646-1705, 708-677-2850. c 2000 by CRC Press LLC
© 2000 by CRC Press LLC reels, sticks, or trays, then place the components at the appropriate pad locations on the board, hence the term “pick and place” equipment. After all parts are placed in the solder paste, the entire assembly enters a reflow oven to raise the temperature of the assembly high enough to reflow the solder paste and create acceptable solder joints at the component lead/pad transitions. Reflow ovens most commonly use convection and IR heat sources to heat the assembly above the point of solder liquidus, which for 63/37 tin-lead eutectic solder is 183°C. Due to the much higher thermal conductivity of the solder paste compared to the IC body, reflow soldering temperatures are reached at the leads/pads before the IC chip itself reaches damaging temperatures. The board is inverted and the process repeated. If mixed-technology Type II is being produced, the board will then be inverted, an adhesive will be dispensed at the centroid of each SMD, parts placed, the adhesive cured, the assembly re-righted, through-hole components mounted, and the circuit assembly will then be wave-soldered which will create acceptable solder joints for both the through-hole components and bottom-side SMDs. A Type III board will first be inverted, adhesive dispensed, SMDs placed on the bottom-side of the board, the adhesive cured, the board re-righted, through-hole components placed, and the entire assembly wavesoldered. It is imperative to note that only passive components and small active SMDs can be successfully bottom-side wave-soldered without considerable experience on the part of the design team and the board assembly facility. It must also be noted that successful wave soldering of SMDs requires a dual-wave machine with one turbulent wave and one laminar wave. It is common for a manufacturer of through-hole boards to convert first to a Type II or Type III substrate design before going to an all-SMD Type I design. This is especially true if amortization of through-hole insertion and wave-soldering equipment is necessary. Many factors contribute to the reality that most boards are mixedtechnology Type II or Type III boards. While most components are available in SMT packages, through-hole connectors are still commonly used for the additional strength the through-hole soldering process provides, and high-power devices such as three-terminal regulators are still commonly through-hole due to off-board heat-sinking demands. Both of these issues are actively being addressed by manufacturers and solutions exist which allow Type I boards with connectors and power devices [Holmes, 1993]. Again, it is imperative that all members of the design, build, and test teams be involved from the design stage. Today’s complex board designs mean that it is entirely possible to exceed the ability to adequately test a board if the test is not designed-in, or to robustly manufacture the board if in-line inspections and handling are not adequately considered.Robustness of both test and manufacturing are only assured with full involvement of all parties to overall board design and production. It cannot be overemphasized that the speed with which packaging issues are moving requires anyone involved in SMT board or assembly issues to stay current and continue to learn about the processes. Subscribe to one or more of the industry-oriented journals noted in the “Further Information” section at the end of this Chapter, obtain any IC industry references, and purchase several SMT reference books. 26.4 Surface Mount Device (SMD) Definitions The new user of SMDs must rapidly learn the packaging sizes and types for SMDs. Resistors, capacitors, and most other passive devices come in two-terminal packages which have end-terminations designed to rest on substrate pads/lands (Fig. 26.3). SMD ICs come in a wide variety of packages, from 8-pin Small Outline Packages (SOLs) to 1000+ connection packages in a variety of sizes and lead configurations, as shown in Fig. 26.4. The most common commercial packages currently include Plastic Leaded Chip Carriers (PLCCs), Small Outline packages (SOs), Quad Flat Packs (QFPs), and Plastic Quad Flat Packs (PQFPs) also know as Bumpered Quad Flat Packs (BQFPs). Add in Tape Automated Bonding (TAB), Ball Grid Array (BGA) and other newer technologies, and the IC possibilities become overwhelming. Space prevents examples of all these technologies from being included here. The reader is referred to the standards of the Institute for Interconnecting and Packaging Electronic Circuits (IPC)1 to find the latest package standards, and to the proceedings of the most recent National Electronics Production and 1 IPC, 7380 N. Lincoln Ave, Lincolnwood, IL 60646-1705, 708-677-2850
End Ter 0603=0060"x0030 0805==0080×00501206=0.120"×0060 FIGURE 26.3 Example of passive component sizes(top view)( Productivity(NEPCON) Conferencel for information on industry uses of the latest SMT Pac overview of package styles is found in Appendix A of Hollomon [1995] and(for ICs only)in Signetics [1991b] which is being updated as of this writing Each IC manufacturer's data books will have packaging information for their products. The engineer should be familiar with the term"lead pitch", which means the center-to-center distance between IC leads Pitch may be in thousandths of an inch, also known as mils, or in millimeters. Common pitches are 0.050 in (50 mil pitch), 0.025 in. (25 mil pitch) frequently called"fine pitch, and 0.020 in. and smaller frequently called"ultra fine pitch". Metric equivalents are 1. 27 mm, 0.635 mm, and 0.508 mm and smaller. Conversions from metric to inches are easily approximated if one remembers that 1 mm approximately equals 40 mils For process control, design teams must consider the minimum and maximum package size variations allowed y their part suppliers, the moisture content of parts as-received, and the relative robustness of each lead type Incoming inspection should consist of both electrical and mechanical tests. Whether these are spot checks, lot checks, or no checks will depend on the relationship with the vendo 26.5 Substrate design guidelines As noted previously, substrate(typically PCB)design has an effect not only on board/component layout, but also on the actual manufacturing process. Incorrect land design or layout can negatively affect the placement process, the solder process, the test process or any combination of the three Substrate design must take into account the mix of SMDs that are available for use in manufacturing The considerations noted here as part of the design process are neither all-encompassing, nor in sufficient detail for a true SMT novice to adequately deal with all the issues involved in the process. They are intended to guide an engineer through the process, allowing him/her to access more detailed information as necessary. General references are noted at the end of this chapter, and specific references will be noted as applicable. In onferences such as the nepcon, and SMI are invaluable sources of information for both the and the experienced SMT engineer. Although these guidelines are noted as"steps", they are not necessarily in an absolute order, and may require several iterations back-and-forth among the steps to result in a final satisfactory process and product. After the circuit design(schematic capture)and analysis, Step l in the process is to determine whether all SMDs will be used in the final design making a Type I board, or whether a mix of SMDs and through-hole parts will be used, leading to a Type Il or Type III board. This decision will be governed by some or all of the Current parts stock Existence of current through-hole placement and/or wave solder equipment 2Surface Mount Technology Association, 5200 Wilson Rd, Suite 100, Minneapolis, MN 55424
© 2000 by CRC Press LLC Productivity (NEPCON) Conference1 for information on industry uses of the latest SMT packages. A good overview of package styles is found in Appendix A of Hollomon [1995] and (for ICs only) in Signetics [1991b] which is being updated as of this writing. Each IC manufacturer’s data books will have packaging information for their products. The engineer should be familiar with the term “lead pitch”, which means the center-to-center distance between IC leads. Pitch may be in thousandths of an inch, also known as mils, or in millimeters. Common pitches are 0.050 in. (50 mil pitch), 0.025 in. (25 mil pitch) frequently called “fine pitch”, and 0.020 in. and smaller frequently called “ultra- fine pitch”. Metric equivalents are 1.27 mm, 0.635 mm, and 0.508 mm and smaller. Conversions from metric to inches are easily approximated if one remembers that 1 mm approximately equals 40 mils. For process control, design teams must consider the minimum and maximum package size variations allowed by their part suppliers, the moisture content of parts as-received, and the relative robustness of each lead type. Incoming inspection should consist of both electrical and mechanical tests. Whether these are spot checks, lot checks, or no checks will depend on the relationship with the vendor. 26.5 Substrate Design Guidelines As noted previously, substrate (typically PCB) design has an effect not only on board/component layout, but also on the actual manufacturing process. Incorrect land design or layout can negatively affect the placement process, the solder process, the test process or any combination of the three. Substrate design must take into account the mix of SMDs that are available for use in manufacturing. The considerations noted here as part of the design process are neither all-encompassing, nor in sufficient detail for a true SMT novice to adequately deal with all the issues involved in the process. They are intended to guide an engineer through the process, allowing him/her to access more detailed information as necessary. General references are noted at the end of this chapter, and specific references will be noted as applicable. In addition, conferences such as the NEPCON, and SMI2 are invaluable sources of information for both the beginner and the experienced SMT engineer. Although these guidelines are noted as “steps”, they are not necessarily in an absolute order, and may require several iterations back-and-forth among the steps to result in a final satisfactory process and product. After the circuit design (schematic capture) and analysis, Step 1 in the process is to determine whether all SMDs will be used in the final design making a Type I board, or whether a mix of SMDs and through-hole parts will be used, leading to a Type II or Type III board. This decision will be governed by some or all of the following considerations: • Current parts stock • Existence of current through-hole placement and/or wave solder equipment 1 NEPCON, rep. by Reed Exhibition Co., Norwalk, CT. 2 Surface Mount Technology Association, 5200 Wilson Rd., Suite 100, Minneapolis, MN 55424. FIGURE 26.3 Example of passive component sizes (top view)(not to scale)
(Plastic Leaded Chip Camier) ual Row al outine Package) Quad Row hin Small ouing Packag时 <Qund Flatpack] FLATPACK FIGURE 26. 4 Examples of SMT plastic packages. Source: Intel Corporation, Packaging, Santa Clara Intel Corporation, 1994. with permissi
© 2000 by CRC Press LLC FIGURE 26.4 Examples of SMT plastic packages. (Source: Intel Corporation, Packaging, Santa Clara, Calif.: Intel Corporation, 1994. With permission.)
(a) FIGURE 26.5 (a)Footprint land and resist. Source: Phillips Semiconductors, Surface Mount Process and Application Notes, Sunnyvale, Calif. Phillips Semiconductors, 1991. With permission. )(b)QFP footprint. Source: Intel Corporation, Packaging, Santa Clara, Calif Intel Corporation, 1994. With permission Amortization of current through-hole placement and solder equipment Existence of reflow soldering equipment, or cost of new reflow soldering equipment Desired size of the final product Panellization of smaller Type I board Thermal issues related to high power circuit sections on the board It may be desirable to segment the board into areas based on function: RE, low power, high power, etc using all SMDs where appropriate, and mixed-technology components as needed. Power and connector portions of he circuit may point to the use of through-hole components, although as mentioned both these issues are ing addressed by circuit board material and connector manufacturers. Using one solder technique (reflow or wave) simplifies processing, and may outweigh other considerations. Step 2 in the SMT process is to define all the footprints of the SMDs under consideration for use in the design. The footprint is the copper pattern or land", on the circuit board upon which the SMd will be placed ootprint examples are shown in Figs. 26.5a and 26 5b, and footprint recommendations are available from IC manufacturers and in the appropriate data books. They are also available in various ECAd packages used for the design process, or in several references that include an overview of the SmT process[Electronic Packaging and Production, 1994. However, the reader is seriously cautioned about using the general references for anything other than the most common passive and active packages. Even the position of pin 1 may be different among IC manufacturers of the"same"chip. The footprint definition may also include the position of the solder resist pattern surrounding the copper pattern. Footprint definition sizing will vary depending on whether reflow or wave solder process is used. Wave solder footprints will require recognition of the direction of travel of the board through the wave, to minimize solder shadowing in the final fillet, as well as requirements for solder thieves. The copper footprint must allow for the formation of an appropriate, inspectable solder fillet. If done as part of the EDa process(electronic design automation, using appropriate electronic CAD software), the software will automatically assign copper directions to each component footprint, as well as appropriate coordinates and dimensions. These may need adjustment based on considerations related to wave soldering, test points, RF and/or power issues, and board production limitations. Allowing the software to select 5 mil traces when the board production facility to be used can only reliably do 10 mil traces would be inappropriat Likewise, the solder resist patterns must be governed by the production capabilities Final footprint and trace decisions will allow for optimal solder fillet formation ecessary trace and footprint area allow for adequate test points minimize board area, if appropriate set minimum inter-part clearances for placement and test equipment to safely access the board (Fig. 26.6) c 2000 by CRC Press LLC
© 2000 by CRC Press LLC • Amortization of current through-hole placement and solder equipment • Existence of reflow soldering equipment, or cost of new reflow soldering equipment • Desired size of the final product • Panellization of smaller Type I boards • Thermal issues related to high power circuit sections on the board It may be desirable to segment the board into areas based on function: RF, low power, high power, etc. using all SMDs where appropriate, and mixed-technology components as needed. Power and connector portions of the circuit may point to the use of through-hole components, although as mentioned both these issues are being addressed by circuit board material and connector manufacturers. Using one solder technique (reflow or wave) simplifies processing, and may outweigh other considerations. Step 2 in the SMT process is to define all the footprints of the SMDs under consideration for use in the design. The footprint is the copper pattern or “land”, on the circuit board upon which the SMD will be placed. Footprint examples are shown in Figs. 26.5a and 26.5b, and footprint recommendations are available from IC manufacturers and in the appropriate data books. They are also available in various ECAD packages used for the design process, or in several references that include an overview of the SMT process [Electronic Packaging and Production, 1994]. However, the reader is seriously cautioned about using the general references for anything other than the most common passive and active packages. Even the position of pin 1 may be different among IC manufacturers of the “same” chip. The footprint definition may also include the position of the solder resist pattern surrounding the copper pattern. Footprint definition sizing will vary depending on whether reflow or wave solder process is used. Wave solder footprints will require recognition of the direction of travel of the board through the wave, to minimize solder shadowing in the final fillet, as well as requirements for solder thieves. The copper footprint must allow for the formation of an appropriate, inspectable solder fillet. If done as part of the EDA process (electronic design automation, using appropriate electronic CAD software), the software will automatically assign copper directions to each component footprint, as well as appropriate coordinates and dimensions. These may need adjustment based on considerations related to wave soldering, test points, RF and/or power issues, and board production limitations. Allowing the software to select 5 mil traces when the board production facility to be used can only reliably do 10 mil traces would be inappropriate. Likewise, the solder resist patterns must be governed by the production capabilities. Final footprint and trace decisions will: • allow for optimal solder fillet formation • minimize necessary trace and footprint area • allow for adequate test points • minimize board area, if appropriate • set minimum inter-part clearances for placement and test equipment to safely access the board (Fig. 26.6) FIGURE 26.5 (a) Footprint land and resist. (Source: Phillips Semiconductors, Surface Mount Process and Application Notes, Sunnyvale, Calif.: Phillips Semiconductors, 1991.With permission.) (b) QFP footprint. (Source: Intel Corporation, Packaging, Santa Clara, Calif.: Intel Corporation, 1994. With permission.)
FIGURE 26.6 Minimum land-to-land clearance examples. Source: Intel Corporation ging, Santa Clara, Calif. Intel Corporation, 1994. with permission. allow adequate distance between components for post-reflow operator inspections allow room for adhesive dots on wave-soldered boards minimize solder bridging Decisions that will provide optimal footprints include a number of mathematical issues, including: component dimension tolerances board production capabilities, both artwork and physical tolerances across the board relative to a 0-0 how much artwork/board shrink or stretch is allowable solder deposition volume consistencies with respect to fillet sizes placement machine accuracies test probe location controls and bed-of-nails grid pitch Design teams should restrict wave-solder-side SMDs to passive components and While small SMT ICs can be successfully wave-soldered, this is inappropriate for an initial SMT mended by some IC manufacturers( Fig. 26.2) These decisions may require a statistical computer program, if available to the design team. The stochastic nature of the overall process suggests a statistical programmer will be of value. 26.6 Thermal design Considerations Thermal management issues remain major concerns in the successful design of an SMT board and product. Consideration must be taken of the variables affecting both board temperature and junction temperature of the IC. The reader is referred to Chapter 33 in this Handbook for the basics of Thermal Management, and to Bar-Cohen and Kraus[1988] for a more detailed treatment on thermal issues affecting ICs and PCB design. The design team must understand the basic heat transfer characteristics of most SMT IC packages [ Capillo, 1993. Since the silicon chip of an SMD is equivalent to the chip in an identical-function DIP package, the smaller SMD package means the internal lead frame metal has a smaller mass than the lead frame in a DIP package. This lesser ability to conduct heat away from the chip is somewhat offset by the leadframe of many SMDs being constructed of copper, which has a lower thermal resistance than the Kovar and Alloy 42 materials c 2000 by CRC Press LLC
© 2000 by CRC Press LLC • allow adequate distance between components for post-reflow operator inspections • allow room for adhesive dots on wave-soldered boards • minimize solder bridging Decisions that will provide optimal footprints include a number of mathematical issues, including: • component dimension tolerances • board production capabilities, both artwork and physical tolerances across the board relative to a 0–0 fiducial • how much artwork/board shrink or stretch is allowable • solder deposition volume consistencies with respect to fillet sizes • placement machine accuracies • test probe location controls and bed-of-nails grid pitch Design teams should restrict wave-solder-side SMDs to passive components and transistors. While small SMT ICs can be successfully wave-soldered, this is inappropriate for an initial SMT design, and is not recommended by some IC manufacturers (Fig. 26.2). These decisions may require a statistical computer program, if available to the design team. The stochastic nature of the overall process suggests a statistical programmer will be of value. 26.6 Thermal Design Considerations Thermal management issues remain major concerns in the successful design of an SMT board and product. Consideration must be taken of the variables affecting both board temperature and junction temperature of the IC. The reader is referred to Chapter 33 in this Handbook for the basics of Thermal Management, and to Bar-Cohen and Kraus [1988] for a more detailed treatment on thermal issues affecting ICs and PCB design. The design team must understand the basic heat transfer characteristics of most SMT IC packages [Capillo, 1993]. Since the silicon chip of an SMD is equivalent to the chip in an identical-function DIP package, the smaller SMD package means the internal lead frame metal has a smaller mass than the lead frame in a DIP package. This lesser ability to conduct heat away from the chip is somewhat offset by the leadframe of many SMDs being constructed of copper, which has a lower thermal resistance than the Kovar and Alloy 42 materials FIGURE 26.6 Minimum land-to-land clearance examples. (Source: Intel Corporation, Packaging, Santa Clara, Calif.: Intel Corporation, 1994. With permission.)
commonly used for DIP packages. However, with less metal and shorter lead lengths to transfer heat to ambient air, more heat is typically transferred to the circuit board itself. Several board thermal analysis software packages are available, and are highly recommended for boards that are expected to develop high thermal gradients Flotherm, 1995 Since all electronics components generate heat in use, and elevated temperatures negatively affect the reli ability and failure rate of semiconductors, it is important that heat generated by SMDs be removed as efficiently as possible. The design team needs to have expertise with the variables related to thermal transfer nction temperature: T thermal resistances: Oi, O a,e temperature sensitive parameter(TSP)method of determining Os thermal characteristics of substrate material SMt Packages have been developed to maximize heat transfer to the substrate. These include PLCCs with integral heat spreaders, the SOT-89 power transistor package, the dpak power transistor package, and many others. Analog ICs are also available in power packages. Note that all of these devices are designed primarily for processing with the solder paste process, and some specifically recommend against their use with wave solder applications. Heat sinks and heat pipes should also be considered for high-power ICs. In the conduction process, heat is transferred from one element to another by direct physical contact between the elements. Ideally the material to which heat is being transferred should not be adversely affected by the transfer. As an example, the glass transition temperature T, of FR-4 is 125.C. Heat transferred to the board has little or no detrimental affect as long as the board temperature stays at least 50oC below Tx. Good heat sink naterial exhibits high thermal conductivity, which is not a characteristic of fiberglass. Therefore, the traces must be depended on to provide the thermal transfer path [Choi et al., 1994]. Conductive heat transfer is also used in the transfer of heat from IC packages to heat sinks, which also requires use of thermal grease to fill all air gaps between the package and the" flat"surface of the sink. The previous discussion of lead properties of course does not apply to leadless devices such as Leadless Ceramic Chip Carriers(LCCCs). Design teams using these and similar packages must understand the better heat transfer properties of the alumina used in ceramic packages, and must match TCEs between the LCCC and the substrate, since there are no leads to bend and absorb mismatches of expansion Since the heat transfer properties of the system depend on substrate material properties, it is necessary to understand several of the characteristics of the most common substrate material, FR-4 fiberglass. The glas transition temperature has already been noted, and board designers must also understand that multi-layer FR 4 boards do not expand identically in the X-, Y-, and Z-directions as temperature increases. Plate-through holes will constrain z-axis expansion in their immediate board areas, while non-through-hole areas will expand further in the z-axis, particularly as the temperature approaches and exceeds Ts [Lee et al., 1984]. This uneq expansion can cause delamination of layers and plating fracture. If the design team knows that there will be a need for higher abilities to dissipate heat and/or a need for higher glass transition temperatures and lower coefficients of thermal expansion(TCe)than FR-4 possesses, many other materials are available, examples of which will follow. Note in Table 26.1 that copper-clad Invar has both variable Tg and variable thermal conductivity depending on the volume mix of copper and Invar in the substrate. Copper has a high TCE and Invar has a low TCE, so the TCE increases with the thickness of the copper layers. In addition to heat transfer considerations, board material decisions must also be based on the expected vibration, stress, and humidity in the application. Convective heat transfer involves transfer due to the motion of molecules, typically airflow over a he and depends on the relative temperatures of the two media involved. It also depends on the velocity of air flow over the boundary layer of the heat sink. Convective heat transfer is primarily effected when forced air flow is provided across a substrate, and when convection effects are maximized through the use of heat sinks. The rules that designers are familiar with when designing ThT heat-sink device designs also apply to SMT design. The design team must consider whether passive conduction and convection will be adequate to cool a populated substrate or whether forced-air cooling or liquid cooling will be needed. Passive conductive cooling c 2000 by CRC Press LLC
© 2000 by CRC Press LLC commonly used for DIP packages. However, with less metal and shorter lead lengths to transfer heat to ambient air, more heat is typically transferred to the circuit board itself. Several board thermal analysis software packages are available, and are highly recommended for boards that are expected to develop high thermal gradients [Flotherm, 1995]. Since all electronics components generate heat in use, and elevated temperatures negatively affect the reliability and failure rate of semiconductors, it is important that heat generated by SMDs be removed as efficiently as possible. The design team needs to have expertise with the variables related to thermal transfer: • junction temperature: Tj • thermal resistances: Qjc , Qca , Qcs, Qsa • temperature sensitive parameter (TSP) method of determining Qs • power dissipation: PD • thermal characteristics of substrate material SMT packages have been developed to maximize heat transfer to the substrate. These include PLCCs with integral heat spreaders, the SOT-89 power transistor package, the DPAK power transistor package, and many others. Analog ICs are also available in power packages. Note that all of these devices are designed primarily for processing with the solder paste process, and some specifically recommend against their use with wavesolder applications. Heat sinks and heat pipes should also be considered for high-power ICs. In the conduction process, heat is transferred from one element to another by direct physical contact between the elements. Ideally the material to which heat is being transferred should not be adversely affected by the transfer. As an example, the glass transition temperature Tg of FR-4 is 125°C. Heat transferred to the board has little or no detrimental affect as long as the board temperature stays at least 50°C below Tg. Good heat sink material exhibits high thermal conductivity, which is not a characteristic of fiberglass. Therefore, the traces must be depended on to provide the thermal transfer path [Choi et al., 1994]. Conductive heat transfer is also used in the transfer of heat from IC packages to heat sinks, which also requires use of thermal grease to fill all air gaps between the package and the “flat” surface of the sink. The previous discussion of lead properties of course does not apply to leadless devices such as Leadless Ceramic Chip Carriers (LCCCs). Design teams using these and similar packages must understand the better heat transfer properties of the alumina used in ceramic packages, and must match TCEs between the LCCC and the substrate, since there are no leads to bend and absorb mismatches of expansion. Since the heat transfer properties of the system depend on substrate material properties, it is necessary to understand several of the characteristics of the most common substrate material, FR-4 fiberglass. The glass transition temperature has already been noted, and board designers must also understand that multi-layer FR- 4 boards do not expand identically in the X-, Y-, and Z-directions as temperature increases. Plate-throughholes will constrain z-axis expansion in their immediate board areas, while non-through-hole areas will expand further in the z-axis, particularly as the temperature approaches and exceeds Tg [Lee et al., 1984]. This unequal expansion can cause delamination of layers and plating fracture. If the design team knows that there will be a need for higher abilities to dissipate heat and/or a need for higher glass transition temperatures and lower coefficients of thermal expansion (TCE) than FR-4 possesses, many other materials are available, examples of which will follow. Note in Table 26.1 that copper-clad Invar has both variable Tg and variable thermal conductivity depending on the volume mix of copper and Invar in the substrate. Copper has a high TCE and Invar has a low TCE, so the TCE increases with the thickness of the copper layers. In addition to heat transfer considerations, board material decisions must also be based on the expected vibration, stress, and humidity in the application. Convective heat transfer involves transfer due to the motion of molecules, typically airflow over a heat sink, and depends on the relative temperatures of the two media involved. It also depends on the velocity of air flow over the boundary layer of the heat sink. Convective heat transfer is primarily effected when forced air flow is provided across a substrate, and when convection effects are maximized through the use of heat sinks. The rules that designers are familiar with when designing THT heat-sink device designs also apply to SMT design. The design team must consider whether passive conduction and convection will be adequate to cool a populated substrate or whether forced-air cooling or liquid cooling will be needed. Passive conductive cooling
