《电子工程师手册》学习资料（英文版）chapter 33 Thermal Management of Electronics.pdf_大学文库

33 Thermal Management of electronics Motivation. Requirements 33.2 Heat Transfer Fundamentals Avram Bar -Cohen 33.3 Chip Module Thermal Resistance Definition· Internal resistance· External resistance· Total University of minnesota Resistance. Multichip Modules 33.1 Introduction Motivation In the thermal control of microelectronic components, it is necessary to provide an acceptable microclimate for a diversity of devices and packages, which vary widely in size, power dissipation, and sensitivity to temperature. Although the thermal management of all electronic components is motivated by a common set of concerns, this diversity often leads to the design and development of distinct thermal control systems for different types of electronic equipment. Moreover, due to substantial variations in the performance, cost, and environmental tions across product categories, the thermal control of similar components may require widely differing thermal management strategies. The prevention of catastrophic thermal failure, defined as an immediate, thermally induced, total loss of electronic function, must be viewed as the primary and foremost aim of electronics thermal control. Cata strophic failure may result from a significant deterioration in the performance of the component/system or from a loss of structural integrity at one of the relevant packaging levels. In early microelectronic systems, catastrophic failure was primarily functional and thought to result from changes in the bias voltage, thermal runaway produced by regenerative heating, and dopant migration, all occurring at elevated transistor junction temperatures. While these failure modes may still occur during the device development process, improved licon simulation tools and thermally compensated integrated circuits have largely quieted these concerns and ostantially broadened the operating temperature range of today's silicon-based logic and memory devices Similar concerns do still exist in the use of CMos devices for high-performance systems. Because of the dependence of CMOS circuit speed on temperature, it may be necessary to limit the maximum chip temperature to achieve a desired cycle time and/or to maintain timing margins in the system. More generally, however, thermal design in the 1990s is aimed at preventing thermally induced physical failures, through reduction of the temperature rise above ambient and minimization of temperature variations within the packaging structure(s). The use of many low-temperature materials and the structural complexity of chip packages and printed circuit boards has increased the risk of catastrophic failures associated with the vaporization of organic materials, the melting of solders, and thermal-stress fracture of leads, joints, and seals, as well as the fatigue-induced delamination and fracture or creep-induced deformation of encapsulants and c 2000 by CRC Press LLC

© 2000 by CRC Press LLC 33 Thermal Management of Electronics 33.1 Introduction Motivation • Requirements 33.2 Heat Transfer Fundamentals 33.3 Chip Module Thermal Resistance Definition • Internal Resistance • External Resistance • Total Resistance • Multichip Modules 33.1 Introduction Motivation In the thermal control of microelectronic components, it is necessary to provide an acceptable microclimate for a diversity of devices and packages, which vary widely in size, power dissipation, and sensitivity to temperature. Although the thermal management of all electronic components is motivated by a common set of concerns, this diversity often leads to the design and development of distinct thermal control systems for different types of electronic equipment. Moreover, due to substantial variations in the performance, cost, and environmental specifications across product categories, the thermal control of similar components may require widely differing thermal management strategies. The prevention of catastrophic thermal failure, defined as an immediate, thermally induced, total loss of electronic function, must be viewed as the primary and foremost aim of electronics thermal control. Catastrophic failure may result from a significant deterioration in the performance of the component/system or from a loss of structural integrity at one of the relevant packaging levels. In early microelectronic systems, catastrophic failure was primarily functional and thought to result from changes in the bias voltage, thermal runaway produced by regenerative heating, and dopant migration, all occurring at elevated transistor junction temperatures. While these failure modes may still occur during the device development process, improved silicon simulation tools and thermally compensated integrated circuits have largely quieted these concerns and substantially broadened the operating temperature range of today’s silicon-based logic and memory devices. Similar concerns do still exist in the use of CMOS devices for high-performance systems. Because of the dependence of CMOS circuit speed on temperature, it may be necessary to limit the maximum chip temperature to achieve a desired cycle time and/or to maintain timing margins in the system. More generally, however, thermal design in the 1990s is aimed at preventing thermally induced physical failures, through reduction of the temperature rise above ambient and minimization of temperature variations within the packaging structure(s). The use of many low-temperature materials and the structural complexity of chip packages and printed circuit boards has increased the risk of catastrophic failures associated with the vaporization of organic materials, the melting of solders, and thermal-stress fracture of leads, joints, and seals, as well as the fatigue-induced delamination and fracture or creep-induced deformation of encapsulants and Avram Bar-Cohen University of Minnesota

与e Stress Rati 80100120140 Temperature , C FIGURE 33 1 Exponential dependence of failure rate on component temperature laminates. To prevent catastrophic thermal failure, the designer must know the maximum allowable tempera- tures,acceptable internal temperature differences, and the power consumption/dissipation of the various omponents. This information can be used to select the appropriate fluid, heat transfer mode, and inlet temperature for the coolant and to thus establish the thermal control strategy early in the design process After the selection of an appropriate thermal control strategy, attention can be turned to meeting the desired system-level reliability and the target failure rates of each component and subassembly. Individual solid-state electronic devices are inherently reliable and can typically be expected to operate, at room temperature, for some 100,000 years, i.e., with a base failure rate of 1 FIt(failures in 10 h). However, since the number of devices in a typical logic component is rapidly approaching l million and since an electronic system may consist of many tens to several hundreds of such components, achieving a system Mean Time Between Failures of everal thousand hours in military equipment and 40,000-60,000 hours in commercial electronics is a most formidable task. Many of the failure mechanisms, which are activated by prolonged operation of electronic components, are related to the local temperature and/or temperature gradients, as well as the thermal history of the package Pecht et al., 1992]. Device-related functional failures often exhibit a strong relationship between failure rate and operating temperature. This dependence, illustrated in Fig. 33 1, is exponential in nature and commonly temperature is thought to double the component failure toe ue, empirically determined coefficients for each omponent type. In the normal operating range of mi ctronic components, a 10-20oC increase in chip rate, and even a 1C decrease may lower the predicted failure rate associated with such mechanisms by 2-4%[Morrison et al., 1982 Unfortunately, it is not generally possible to characterize thermally induced structural failures, which develol as a result of differential thermal expansion among the materials constituting an electronic package, in the form of an Arrhenius relation. Although these mechanical stresses may well increase as the temperature of the component is elevated, thermal stress failures are, by their nature, dependent on the details of the local temperature fields, as well as the assembly, attachment, and local operating history of the component. Further more,thermal stress generation in packaging materials and structures is exacerbated by power transients, as well as by the periodically varying environmental temperatures, experienced by most electronic systems, during both qualification tests and actual operation. However, stress variations in the elastic domain or in the range below the fatigue limit may have little effect on the component failure rate. Consequently, the minimization or elimination of thermally induced failures often requires careful attention to both the temperature and stress e 2000 by CRC Press LLC

© 2000 by CRC Press LLC laminates. To prevent catastrophic thermal failure, the designer must know the maximum allowable temperatures, acceptable internal temperature differences, and the power consumption/dissipation of the various components. This information can be used to select the appropriate fluid, heat transfer mode, and inlet temperature for the coolant and to thus establish the thermal control strategy early in the design process. After the selection of an appropriate thermal control strategy, attention can be turned to meeting the desired system-level reliability and the target failure rates of each component and subassembly. Individual solid-state electronic devices are inherently reliable and can typically be expected to operate, at room temperature, for some 100,000 years, i.e., with a base failure rate of 1 FIT (failures in 109 h). However, since the number of devices in a typical logic component is rapidly approaching 1 million and since an electronic system may consist of many tens to several hundreds of such components, achieving a system Mean Time Between Failures of several thousand hours in military equipment and 40,000–60,000 hours in commercial electronics is a most formidable task. Many of the failure mechanisms, which are activated by prolonged operation of electronic components, are related to the local temperature and/or temperature gradients, as well as the thermal history of the package [Pecht et al., 1992]. Device-related functional failures often exhibit a strong relationship between failure rate and operating temperature. This dependence, illustrated in Fig. 33.1, is exponential in nature and commonly represented in the form of an Arrhenius relation, with unique, empirically determined coefficients for each component type. In the normal operating range of microelectronic components, a 10–20°C increase in chip temperature is thought to double the component failure rate, and even a 1°C decrease may lower the predicted failure rate associated with such mechanisms by 2–4% [Morrison et al., 1982]. Unfortunately, it is not generally possible to characterize thermally induced structural failures, which develop as a result of differential thermal expansion among the materials constituting an electronic package, in the form of an Arrhenius relation. Although these mechanical stresses may well increase as the temperature of the component is elevated, thermal stress failures are, by their nature, dependent on the details of the local temperature fields, as well as the assembly, attachment, and local operating history of the component. Furthermore, thermal stress generation in packaging materials and structures is exacerbated by power transients, as well as by the periodically varying environmental temperatures, experienced by most electronic systems, during both qualification tests and actual operation. However, stress variations in the elastic domain or in the range below the fatigue limit may have little effect on the component failure rate. Consequently, the minimization or elimination of thermally induced failures often requires careful attention to both the temperature and stress FIGURE 33.1 Exponential dependence of failure rate on component temperature

fields in the electronic components and necessitate the empirical validation of any proposed thermostructural To initiate the development of a thermal design for a specified electronic product, it is first necessary to define the relevant packaging level. The commonly accepted categorization places the chip package, which houses and protects the chip, at the bottom of the packaging hierarchy(Level 1), the printed circuit board, which provides for chip-to-chip interconnect, as Level 2, the backplane, or motherboard, " which interconnects the printed circuit boards, as Level 3, and defines the box, rack, or cabinet, which houses the entire system, as Level 4 The primary thermal transport mechanisms and commonly used heat removal techniques vary substantially from one packaging level to the next. While Level 1 thermal packaging is primarily concerned with conducting heat from the chip to the package, at Level 2 attention must be devoted to heat spreading by conduction in the printed circuit board and convection of the heat tot he ambient air, and/or transport of the heat to the board edge. Many of todays electronic systems, as might be surmised from the frequently cited"computer-on-a-chip or "computer-on-a-board"terminology, can be adequately packaged at Level 1 or 2. Heat sinks, or finned surfaces protruding into the air stream, are often used at Level 1 and 2 to aid in the transfer of heat into the ambient air. When Level 3 and/or 4 are present, thermal packaging generally involves the use of active thermal control measures, such as air handling systems, refrigeration systems, or water channels, heat exchangers, and equirement Consideration of the Arrhenius relationship has resulted in peak allowable temperatures of 110-120@C for most military equipment [Morrison et al, 1982] and has led designers of commercial equipment to specify average chip operating temperatures in the 65-85C range[ Bar-Cohen, 1987, 1988]. Theoretical predictions of dramatic reductions in component failure rates have been used to justify the use of refrigerated avionics [ Morrison, 1982] and cryogenic electronics [Jaeger, 1986; Vacca et al., 1987]. To accomodate rising power dissipation, commercial chip operating temperatures are expected to increase past 100 C in the coming decade The stabilization of component temperature and minimization of the temperature differences between adjacent devices, components, and various packaging levels have long been known to reduce failure rates in electronic systems [Hilbert and Kube, 1969]. In layered structures, such as chip packages and printed circuit boards, and in the joints of surface mounted components, temperature nonuniformities, in all but the most clever designs, accentuate the differences in the thermal expansion coefficients among the various materials and can frequently result in thermal stresses that threaten the integrity of these components and joints [ Engle mier,1984; Suhir, 1988]. The growing integration on a single chip of functionally distinct and thermally diverse devices, as in the power-integrated chips of the late 1980s and in the microsensor, RE, and in optoelectronic chips under development today, can be expected to focus renewed attention on the minimization of transient temperature and stress fields produced by localized heat sources. Despite the precipitous drop in transistor switching energy from more than 10J in 1960 to nearly 10- in devices used during the late 1980s and down to 10-14 J in the early 1990s, the cooling requirements of microelectronic packages have not diminished. Because of increased device densities and higher operating speeds, chip heat removal requirements have actually risen from 0. 1 to 0.3 w, typical of the SSi devices used in the early 1960s, to 1 to 5 w in the LSI ECL components and VlSI CMOS devices of the mid-1980s, and to values in the range of 15 to 30 W for commercial equipment in the early 1990s Projections of current trends ggest that by the year 2000, the thermal designer will have to contend with chip power dissipations in excess f 150 W, producing surface heat fluxes of nearly 80 W/cm for the smaller chips and approximately 40 W/cm2 for the larger(2 x 2 cm)chips likely to be available in that time period. It may be anticipated that, by the turn of the century, substrate heat fluxes of more than 25 W/cm will be encountered in both large(30 X 30x 5 cm) and small(5×5×2cm) multichip modules The successful removal of these heat fluxes, in the presence of severe electrical, manufacturing cost, and reliability constraints, poses a formidable challenge to the packaging community. Nevertheless, it must be noted that the heat fluxes encountered in today's"cutting edge technology"chips already pose a significant challenge to the thermal packaging engineer. Chip heat fluxes in the mid-1980s typically ranged from 5 W/cm2to nearly e 2000 by CRC Press LLC

© 2000 by CRC Press LLC fields in the electronic components and necessitate the empirical validation of any proposed thermostructural design criteria. To initiate the development of a thermal design for a specified electronic product, it is first necessary to define the relevant packaging level. The commonly accepted categorization places the chip package, which houses and protects the chip, at the bottom of the packaging hierarchy (Level 1), the printed circuit board, which provides for chip-to-chip interconnect, as Level 2, the backplane, or “motherboard,” which interconnects the printed circuit boards, as Level 3, and defines the box, rack, or cabinet, which houses the entire system, as Level 4. The primary thermal transport mechanisms and commonly used heat removal techniques vary substantially from one packaging level to the next. While Level 1 thermal packaging is primarily concerned with conducting heat from the chip to the package, at Level 2 attention must be devoted to heat spreading by conduction in the printed circuit board and convection of the heat tot he ambient air, and/or transport of the heat to the board edge. Many of today’s electronic systems, as might be surmised from the frequently cited “computer-on-a-chip” or “computer-on-a-board” terminology, can be adequately packaged at Level 1 or 2. Heat sinks, or finned surfaces protruding into the air stream, are often used at Level 1 and 2 to aid in the transfer of heat into the ambient air. When Level 3 and/or 4 are present, thermal packaging generally involves the use of active thermal control measures, such as air handling systems, refrigeration systems, or water channels, heat exchangers, and pumps. Requirements Consideration of the Arrhenius relationship has resulted in peak allowable temperatures of 110–120°C for most military equipment [Morrison et al., 1982] and has led designers of commercial equipment to specify average chip operating temperatures in the 65–85°C range [Bar-Cohen, 1987, 1988]. Theoretical predictions of dramatic reductions in component failure rates have been used to justify the use of refrigerated avionics [Morrison, 1982] and cryogenic electronics [Jaeger, 1986; Vacca et al., 1987]. To accomodate rising power dissipation, commercial chip operating temperatures are expected to increase past 100°C in the coming decade. The stabilization of component temperature and minimization of the temperature differences between adjacent devices, components, and various packaging levels have long been known to reduce failure rates in electronic systems [Hilbert and Kube, 1969]. In layered structures, such as chip packages and printed circuit boards, and in the joints of surface mounted components, temperature nonuniformities, in all but the most clever designs, accentuate the differences in the thermal expansion coefficients among the various materials and can frequently result in thermal stresses that threaten the integrity of these components and joints [Englemier, 1984; Suhir, 1988]. The growing integration on a single chip of functionally distinct and thermally diverse devices, as in the power-integrated chips of the late 1980s and in the microsensor, RF, and in optoelectronic chips under development today, can be expected to focus renewed attention on the minimization of transient temperature and stress fields produced by localized heat sources. Despite the precipitous drop in transistor switching energy from more than 10–9 J in 1960 to nearly 10–13 J in devices used during the late 1980s and down to 10–14 J in the early 1990s, the cooling requirements of microelectronic packages have not diminished. Because of increased device densities and higher operating speeds, chip heat removal requirements have actually risen from 0.1 to 0.3 W, typical of the SSI devices used in the early 1960s, to 1 to 5 W in the LSI ECL components and VLSI CMOS devices of the mid-1980s, and to values in the range of 15 to 30 W for commercial equipment in the early 1990s. Projections of current trends suggest that by the year 2000, the thermal designer will have to contend with chip power dissipations in excess of 150 W, producing surface heat fluxes of nearly 80 W/cm2 for the smaller chips and approximately 40 W/cm2 for the larger (2 ¥ 2 cm) chips likely to be available in that time period. It may be anticipated that, by the turn of the century, substrate heat fluxes of more than 25 W/cm2 will be encountered in both large (30 ¥ 30 ¥ 5 cm) and small (5 ¥ 5 ¥ 2 cm) multichip modules. The successful removal of these heat fluxes, in the presence of severe electrical, manufacturing cost, and reliability constraints, poses a formidable challenge to the packaging community. Nevertheless, it must be noted that the heat fluxes encountered in today’s “cutting edge technology” chips already pose a significant challenge to the thermal packaging engineer. Chip heat fluxes in the mid-1980s typically ranged from 5 W/cm2 to nearly

30 W/cm, for both single-chip packages and multichip modules [Bar-Cohen, 1987]. Recently released com mercial computers often include chips dissipating 15 to 30 W/cm2[e. g, Kaneko et al., 1990; Pei et al., 1990] and laboratory prototypes have extended the chip heat flux range to nearly 65 W/cm?. These heat fluxes are comparable, at the upper end, to the thermal loading experienced by reentry vehicles and even, at the lower end, to heat fluxes imposed on rocket motor cases. The anticipated peak heat flux in the year 2000 of approx- imately 100 W/cm- is in the range of thermal loadings associated with nuclear blasts. Design Procedure Generation of an appropriate thermal design begins with tabulation of the specified critical temperatures(source and sink) and the heat generation rate. These parameters can be used to define the target thermal resistance, as Rtarget=(Tsource -Sink)/qgen [K/w] The electronics thermal control literature, as well as subsequent sections of this chapter, present much of the relevant thermal packaging information in the form of thermal resistances. At its most fundamental level, the hermal packaging task involves selecting a combination of heat removal mechanisms which yield an overall thermal resistance that is not greater than the target value. The implementation of such a system will assure that the heat source, typically a microprocessor or memory chip, will operate at an acceptable temperature. As will be discussed later in this chapter, in nearly all modes of heat transfer the geometry of the heat flow path, i.e., length and area, play an important role in determining the heat source temperature. Consequently, it is desirable to obtain the relevant geometric details(lengths, thicknesses, areas, volumes)at this early stage in the design process Combining the geometric information with the target thermal resistance, it is often convenient to define an area- specific or volume-specific target thermal resistance in units of K/(W/cm)and K/(W/cm), respectively When the target thermal resistance is known, first-order (or"back-of-the-envelope")calculations are performe to evaluate the severity of the thermal management problem. Although some designs can be completed at this stage, often more precise calculations are needed to verify that the proposed approach does indeed meet the target thermal resistance value. Such calculations can be performed analytically by drawing on the wealth of knowledge in the thermal sciences, numerically using commercial general purpose software, or with commercial software specifically tailored to the thermofluid and thermostructural configurations encountered in packaging. Due to the difficulty in predicting thermal contact resistances at lightly and variably loaded mechanical interfaces and in determining the convective resistances associated with irregular package and printed circuit board geometries, some experimental data is generally needed to establish key parameters or verify system performance The search for an adequate thermal packaging strategy generally begins with consideration of passive transfer modes-conduction, natural convection, and radiation, which require no external motive power and no moving parts. Due to its near-universal availability, air is the most common and preferred cooling fluid. Many electronic systems can be successfully cooled by passive means and especially by natural convection in air. When such passive means are incapable of properly controlling the heat source temperature, the designer must examine the use of active thermal control techniques, including blown air, pumped water, and circulated refrigerants. mmersion of the electronic components directly in dielectric liquids, which can then be pumped or allowed to circulate naturally, provides an additional, though less common, alternative 33.2 Heat Transfer fundamentals To determine the temperature differences encountered in the flow of heat within electronic systems, it is necessary to recognize several different heat transfer mechanisms and their governing relations. In a typical system, heat removal from the active regions of the chip(s) requires the use of several mechanisms, some operating in series and others in parallel, to transport the generated heat to the coolant. Thermal transport through solids is governed by the Fourier equation, which, in one-dimensional form, is q= kAdT/dx [w (33.1) e 2000 by CRC Press LLC

© 2000 by CRC Press LLC 30 W/cm2 , for both single-chip packages and multichip modules [Bar-Cohen, 1987]. Recently released commercial computers often include chips dissipating 15 to 30 W/cm2 [e.g., Kaneko et al., 1990; Pei et al., 1990], and laboratory prototypes have extended the chip heat flux range to nearly 65 W/cm2 . These heat fluxes are comparable, at the upper end, to the thermal loading experienced by reentry vehicles and even, at the lower end, to heat fluxes imposed on rocket motor cases. The anticipated peak heat flux in the year 2000 of approximately 100 W/cm2 is in the range of thermal loadings associated with nuclear blasts. Design Procedure Generation of an appropriate thermal design begins with tabulation of the specified critical temperatures (source and sink) and the heat generation rate. These parameters can be used to define the target thermal resistance, as Rtarget = (Tsource – Tsink)/qgen [K/W] The electronics thermal control literature, as well as subsequent sections of this chapter, present much of the relevant thermal packaging information in the form of thermal resistances. At its most fundamental level, the thermal packaging task involves selecting a combination of heat removal mechanisms which yield an overall thermal resistance that is not greater than the target value. The implementation of such a system will assure that the heat source, typically a microprocessor or memory chip, will operate at an acceptable temperature. As will be discussed later in this chapter, in nearly all modes of heat transfer the geometry of the heat flow path, i.e., length and area, play an important role in determining the heat source temperature. Consequently, it is desirable to obtain the relevant geometric details (lengths, thicknesses, areas, volumes) at this early stage in the design process. Combining the geometric information with the target thermal resistance, it is often convenient to define an areaspecific or volume-specific target thermal resistance in units of K/(W/cm2 ) and K/(W/cm3 ), respectively. When the target thermal resistance is known, first-order (or “back-of-the-envelope”) calculations are performed to evaluate the severity of the thermal management problem. Although some designs can be completed at this stage, often more precise calculations are needed to verify that the proposed approach does indeed meet the target thermal resistance value. Such calculations can be performed analytically by drawing on the wealth of knowledge in the thermal sciences, numerically using commercial general purpose software, or with commercial software specifically tailored to the thermofluid and thermostructural configurations encountered in packaging. Due to the difficulty in predicting thermal contact resistances at lightly and variably loaded mechanical interfaces and in determining the convective resistances associated with irregular package and printed circuit board geometries, some experimental data is generally needed to establish key parameters or verify system performance. The search for an adequate thermal packaging strategy generally begins with consideration of passive transfer modes—conduction, natural convection, and radiation, which require no external motive power and no moving parts. Due to its near-universal availability, air is the most common and preferred cooling fluid. Many electronic systems can be successfully cooled by passive means and especially by natural convection in air. When such passive means are incapable of properly controlling the heat source temperature, the designer must examine the use of active thermal control techniques, including blown air, pumped water, and circulated refrigerants. Immersion of the electronic components directly in dielectric liquids, which can then be pumped or allowed to circulate naturally, provides an additional, though less common, alternative. 33.2 Heat Transfer Fundamentals To determine the temperature differences encountered in the flow of heat within electronic systems, it is necessary to recognize several different heat transfer mechanisms and their governing relations. In a typical system, heat removal from the active regions of the chip(s) requires the use of several mechanisms, some operating in series and others in parallel, to transport the generated heat to the coolant. Thermal transport through solids is governed by the Fourier equation, which, in one-dimensional form, is expressible as q = kAdT/dx [W] (33.1)

to the fin base. In the analysis of such finned surfaces, it is thus common to define a fin efficiency, n, equal to the ratio of the average temperature rise of the fin(above the coolant) to the temperature rise of the fin base. Using this approach, heat transfer by a fin or fin structure can be expressed in the form a= hAn(To-T)IwI (33.9 where T, is the temperature of the fin base. The thermal resistance of a finned surface is given by(nha-and for a properly designed surface, the fin efficiency can be expected to lie between 0.5 and 0.8 The transfer of heat to a flowing gas or liquid, not undergoing a phase change, results in an increase in the mperature, according to q=ricp(Tout -Tin)=pec( Tout -Tin)[W] (33.10) where i is the mass flow rate of the coolant, p is the density, and e is the volumetric flow rate. Based on this relation, it is possible to define an effective flow resistance, ro, as R,=(mcp)-[K/wI (33.11) In a first-order thermal model, it is generally appropriate to relate the heat source temperature to the average (rather than the outlet) coolant temperature. In such calculations the flow resistance should be taken to equal one-half of the value given by Eq.(33. 11). These average flow resistances for the three common coolants in electronics thermal management, i.e., air, water, and FC-72(3M Trade Name), are shown in Figure 33.4 The expression of the governing heat transfer relations in the form of thermal resistances greatly simplifies the first-order thermal analysis of electronic systems. Following the established rules for resistance networks, thermal resistances that occur sequentially along a thermal path can be simply summed to establish the overall thermal resistance for that path. Similarly, the reciprocal of the effective overall resistance of several parallel heat transfer paths can be found by summing the reciprocals of the individual resistances. In refining the thermal design of an electronic system, prime attention should, then, be devoted to reducing the largest resistances along a specified thermal path and/or providing parallel paths for heat removal from a critical area While the thermal resistances associated with various paths and thermal transport mechanisms constitu the building blocks in performing a detailed thermal analysis, they have also found widespread application as figures-of-merit in evaluating and comparing the thermal efficacy of various packaging techniques and thermal anagement strategies. The determination of the relevant thermal resistances is, thus, the key task in the thermal design of an electronic system. 33.3 Chip Module Thermal Resistance Definition The thermal performance of chip packaging techniques is commonly compared on the basis of the overall Gjunction-to-coolant) thermal resistance, Rr. This packaging figure-of-merit is generally defined in a purely empirical fashion to equal Rr=(T-Tp)lq [K/wI (33.12) where T; and T are the junction and coolant(fluid)temperatures, respectively, and q is the chip heat dissipation. Unfortunately, however, most measurement techniques are incapable of detecting the actual junction tem- perature, i.e., the temperature of the small volume at the interface of p-type and n-type semiconductors, and hence, this term generally refers to the average rature or a representative temperature on the chip. Because e 2000 by CRC Press LLC

© 2000 by CRC Press LLC to the fin base. In the analysis of such finned surfaces, it is thus common to define a fin efficiency, h, equal to the ratio of the average temperature rise of the fin (above the coolant) to the temperature rise of the fin base. Using this approach, heat transfer by a fin or fin structure can be expressed in the form qf = hAh(To – Tf) [W] (33.9) where To is the temperature of the fin base. The thermal resistance of a finned surface is given by (hhA)–1 and for a properly designed surface, the fin efficiency can be expected to lie between 0.5 and 0.8. The transfer of heat to a flowing gas or liquid, not undergoing a phase change, results in an increase in the coolant temperature, according to q = m . cp(Tout – Tin) = rQ ˜cp(Tout – Tin) [W] (33.10) where m· is the mass flow rate of the coolant, r is the density, andQ ˜ is the volumetric flow rate. Based on this relation, it is possible to define an effective flow resistance, Rf , as Rf = (mcp · )–1 [K/W] (33.11) In a first-order thermal model, it is generally appropriate to relate the heat source temperature to the average (rather than the outlet) coolant temperature. In such calculations the flow resistance should be taken to equal one-half of the value given by Eq. (33.11). These average flow resistances for the three common coolants in electronics thermal management, i.e., air, water, and FC-72 (3M Trade Name), are shown in Figure 33.4. The expression of the governing heat transfer relations in the form of thermal resistances greatly simplifies the first-order thermal analysis of electronic systems. Following the established rules for resistance networks, thermal resistances that occur sequentially along a thermal path can be simply summed to establish the overall thermal resistance for that path. Similarly, the reciprocal of the effective overall resistance of several parallel heat transfer paths can be found by summing the reciprocals of the individual resistances. In refining the thermal design of an electronic system, prime attention should, then, be devoted to reducing the largest resistances along a specified thermal path and/or providing parallel paths for heat removal from a critical area. While the thermal resistances associated with various paths and thermal transport mechanisms constitute the building blocks in performing a detailed thermal analysis, they have also found widespread application as figures-of-merit in evaluating and comparing the thermal efficacy of various packaging techniques and thermal management strategies. The determination of the relevant thermal resistances is, thus, the key task in the thermal design of an electronic system. 33.3 Chip Module Thermal Resistance Definition The thermal performance of chip packaging techniques is commonly compared on the basis of the overall (junction-to-coolant) thermal resistance, RT . This packaging figure-of-merit is generally defined in a purely empirical fashion to equal RT = (Tj – Tf)/qc [K/W] (33.12) where Tj and Tf are the junction and coolant (fluid) temperatures, respectively, and qc is the chip heat dissipation. Unfortunately, however, most measurement techniques are incapable of detecting the actual junction temperature, i.e., the temperature of the small volume at the interface of p-type and n-type semiconductors, and, hence, this term generally refers to the average temperature or a representative temperature on the chip. Because