《电子工程师手册》学习资料（英文版）chapter 23 Semiconductor Manufacturing.pdf_大学文库

23 Semiconductor Manufacturing 23.1 Processes Thermal Oxidation. Diffusion.lon Implantation.Deposition Harold g. Parks Lithography and Pattern Transfer The University of Arizona, Tucson 3.2 Testing Wayne Needham Built-In Self-Test.Scan Direct Access Testing. Joint Test Action Group. Pattern Generation for Functional Test Using Unit Delay. Pattern Generation for Timing. Temperature, Voltage, and S. Rajaram Processing Effects. Fault Grading. Test Program Flow Lucent Technologies 23.3 Electrical Characterization of Interconnections Interconnection Metrics Interconnection Electrical Parameters Conor Rafferty 23.4 Process Modeling and Simulation Bell laboratories. Lucent lon Implantation. Diffusion.Oxidation. Etching 23.1Pr Harold g. parks Integrated circuit(IC) fabrication consists of a sequence of processing steps referred to as unit step processes that result in the devices contained on todays microchips. These unit step processes provide the methodology for introducing and transporting dopants to change the conductivity of the semiconductor substrate, growing thermal oxides for inter-and intra-level isolation, depositing insulating and conducting films, and patterning and etching the various layers in the formation of the IC. Many of these unit steps have essentially remained the same since discrete component processing, whereas many have originated and grown with the integrated circuit evolution from small-scale integration(SSI) with less than 50 components per chip through very large scale integration(VLSI) with up to one million devices per chip. As the ultra large scale integration(ULSI) with more than a million devices per chip, proceeds to billion-device chips shortly after the turn of the entury, new processes and further modification of the current unit step processes will be required. In this section the unit step processes for silicon IC processing as they exist today with an eye toward the future are presented. How they are combined to form the actual IC process will be discussed in a later section. Due to space limitations only silicon processes are discussed. This author does not feel this is a major limitation, as many of the steps are used in processing other types of semiconductors, and perhaps more than 98% of all ICs today and in he near future are and will be silicon. Furthermore, only the highlights of the unit steps can be presented in this space, with ample references provided for a more thorough presentation. Specifically, the referenced processing textbooks provide detailed discussion of all processes. Thermal Oxidation Silicon dioxide(Sio, layers are important in integrated circuit technology for surface passivation, as a diffusion barrier and as a surface dielectric. The fact that silicon readily forms a high-quality, dense, natural oxide is the major reason it is the dominant integrated circuit technology today. If a silicon wafer is exposed to air, it will c 2000 by CRC Press LLC

© 2000 by CRC Press LLC 23 Semiconductor Manufacturing 23.1 Processes Thermal Oxidation • Diffusion • Ion Implantation • Deposition • Lithography and Pattern Transfer 23.2 Testing Built-In Self-Test • Scan • Direct Access Testing • Joint Test Action Group • Pattern Generation for Functional Test Using Unit Delay • Pattern Generation for Timing • Temperature, Voltage, and Processing Effects • Fault Grading • Test Program Flow 23.3 Electrical Characterization of Interconnections Interconnection Metrics • Interconnection Electrical Parameters 23.4 Process Modeling and Simulation Ion Implantation • Diffusion • Oxidation • Etching • Deposition • Lithography • Summary and Future Trends 23.1 Processes Harold G. Parks Integrated circuit (IC) fabrication consists of a sequence of processing steps referred to as unit step processes that result in the devices contained on today’s microchips. These unit step processes provide the methodology for introducing and transporting dopants to change the conductivity of the semiconductor substrate, growing thermal oxides for inter- and intra-level isolation, depositing insulating and conducting films, and patterning and etching the various layers in the formation of the IC. Many of these unit steps have essentially remained the same since discrete component processing, whereas many have originated and grown with the integrated circuit evolution from small-scale integration (SSI) with less than 50 components per chip through very large scale integration (VLSI) with up to one million devices per chip. As the ultra large scale integration (ULSI) era, with more than a million devices per chip, proceeds to billion-device chips shortly after the turn of the century, new processes and further modification of the current unit step processes will be required. In this section the unit step processes for silicon IC processing as they exist today with an eye toward the future are presented. How they are combined to form the actual IC process will be discussed in a later section. Due to space limitations only silicon processes are discussed. This author does not feel this is a major limitation, as many of the steps are used in processing other types of semiconductors, and perhaps more than 98% of all ICs today and in he near future are and will be silicon. Furthermore, only the highlights of the unit steps can be presented in this space, with ample references provided for a more thorough presentation. Specifically, the referenced processing textbooks provide detailed discussion of all processes. Thermal Oxidation Silicon dioxide (SiO2) layers are important in integrated circuit technology for surface passivation, as a diffusion barrier and as a surface dielectric. The fact that silicon readily forms a high-quality, dense, natural oxide is the major reason it is the dominant integrated circuit technology today. If a silicon wafer is exposed to air, it will Harold G. Parks The University of Arizona, Tucson Wayne Needham Intel Corporation S. Rajaram Lucent Technologies Conor Rafferty Bell Laboratories, Lucent Technology

grow a thin(=45 A)oxide in a relatively short time. To achieve the thicknesses of SiO2 used in integrated circuit hnology(100 A to 2 um)alternative steps must be taken. Thermal oxidation is an extension of the natural oxide growth at an elevated temperature( 800 to 1200oC). The temperature is usually selected out of compro- mise,i.e, it must be high enough to grow the oxide in a reasonable time and it must be as low as practical to minimize crystal damage and unwanted diffusion of dopants already in the wafer. The Oxidation process Thermal oxidation is usually accomplished by placing wafers in a slotted quartz carrier which is inserted into a quartz furnace tube. The tube is surrounded by a resistance heater and has provisions for controlled flow of an inert gas such as nitrogen and the oxidant. a vented cap is placed over the input end of the tube. The gas flows in the back end of the tube, over the wafers, and is exhausted through the vented cap. The wafer zone has a flat temperature profile to within 1/2C and can handle up to 50 parallel stacked wafers. Modern furnaces are computer controlled and programmable Wafers are usually loaded, in an inert environment, ramped to temperature, and switched to the oxidant for a programmed time. When the oxidation is complete the gas is switched back to the inert gas and the temperature is ramped down to the unload temperature. All these mplications in the process are to minimize thermal stress damage to the wafers and the procedures can vary onsiderably. Detailed discussions of the equipment and procedures can be found in references[Sze, 1983] The two most common oxidizing environments are dry and wet. As the name implies, dry oxides are grown in dry O2 gas following the reaction Si+o et oxides were originally grown by bubbling the dry oxygen gas through water at 95C. Most"wet"oxides today are accomplished by the pyrogenic reaction of H, and o, gas to form steam, and are referred to as steam oxidations. In either case the reaction is essentially the same at the wafer: Si+H2O→SiO2+2H2 (23.2) The oxidation process can be modeled as shown in Fig. 23. 1 The position Xo represents the Si/SiO, interface which is a moving Oxide Silicon boundary. The volume density of oxidizing species in the bulk NG gas, N, is depleted at the oxide surface, Ns, due to an amount, No, being incorporated in the oxide layer. The oxidizing species then diffuses across the growing oxide layer where it reacts with the silicon at the moving interface to form SiO,. FG represents the flux of oxidant transported by diffusion from the bulk gas to the oxide surface. The oxidizing species that enters the Sio iffuses across the growing SiO, layer with a flux, For. A reaction takes place at the Si/SiO, interface that consumes some or all of NI the oxidizing species, as represented by the flux, Fr. In steady state these three flux terms are equal and can be used to solve for the concentrations N, and No in terms of the reaction rate and diffusion coefficient of the oxidizing species This in turn specifies the flux terms which can be used in the FIGURE 23. 1 Model of the oxidation process solution of the differential equation dx F for the oxide growth, x In this equation No is the number of oxidant molecules per unit volume of oxide. An excellent derivation of the growth equation is given in Grove [1967]. Here we give the result which can be c 2000 by CRC Press LLC

© 2000 by CRC Press LLC grow a thin (≈45 Å) oxide in a relatively short time. To achieve the thicknesses of SiO2 used in integrated circuit technology (100 Å to 2 µm) alternative steps must be taken. Thermal oxidation is an extension of the natural oxide growth at an elevated temperature (800 to 1200°C). The temperature is usually selected out of compromise, i.e., it must be high enough to grow the oxide in a reasonable time and it must be as low as practical to minimize crystal damage and unwanted diffusion of dopants already in the wafer. The Oxidation Process Thermal oxidation is usually accomplished by placing wafers in a slotted quartz carrier which is inserted into a quartz furnace tube. The tube is surrounded by a resistance heater and has provisions for controlled flow of an inert gas such as nitrogen and the oxidant. A vented cap is placed over the input end of the tube. The gas flows in the back end of the tube, over the wafers, and is exhausted through the vented cap. The wafer zone has a flat temperature profile to within 1/2°C and can handle up to 50 parallel stacked wafers. Modern furnaces are computer controlled and programmable. Wafers are usually loaded, in an inert environment, ramped to temperature, and switched to the oxidant for a programmed time. When the oxidation is complete the gas is switched back to the inert gas and the temperature is ramped down to the unload temperature. All these complications in the process are to minimize thermal stress damage to the wafers and the procedures can vary considerably. Detailed discussions of the equipment and procedures can be found in references [Sze, 1983]. The two most common oxidizing environments are dry and wet. As the name implies, dry oxides are grown in dry O2 gas following the reaction: Si + O2 → SiO2 (23.1) Wet oxides were originally grown by bubbling the dry oxygen gas through water at 95°C. Most “wet” oxides today are accomplished by the pyrogenic reaction of H2 and O2 gas to form steam, and are referred to as steam oxidations. In either case the reaction is essentially the same at the wafer: Si + H2O → SiO2 + 2H2 (23.2) The oxidation process can be modeled as shown in Fig. 23.1 The position X0 represents the Si/SiO2 interface which is a moving boundary. The volume density of oxidizing species in the bulk gas, NG, is depleted at the oxide surface, NS, due to an amount, N0, being incorporated in the oxide layer. The oxidizing species then diffuses across the growing oxide layer where it reacts with the silicon at the moving interface to form SiO2. FG represents the flux of oxidant transported by diffusion from the bulk gas to the oxide surface. The oxidizing species that enters the SiO2 diffuses across the growing SiO2 layer with a flux, Fox. A reaction takes place at the Si/SiO2 interface that consumes some or all of the oxidizing species, as represented by the flux, FI. In steady state these three flux terms are equal and can be used to solve for the concentrations NI and N0 in terms of the reaction rate and diffusion coefficient of the oxidizing species. This in turn specifies the flux terms which can be used in the solution of the differential equation: (23.3) for the oxide growth, x. In this equation Nox is the number of oxidant molecules per unit volume of oxide. An excellent derivation of the growth equation is given in Grove [1967]. Here we give the result which can be represented by: FIGURE 23.1 Model of the oxidation process. dx dt F Nox =

Oxidation rate depends on substrate orientation [Ghandhi, 1968]. This effect is related to the surf density of the substrate, i. e,, the higher the density, the faster the oxidation rate. Oxidation rate also on pressure. The linear and parabolic rates are dependent on the equilibrium concentration of the species in the SiO2 which is directly proportional to the partial pressure of the oxidant in the ambient. Oxide growth rate shows a doping dependence for heavily doped substrates(>102 cm-). Boron increases the parabolic rate constant and phosphorus enhances the linear rate constant Wolf and Tauber, 1986 Oxide Characteristics Dry oxides grow more slowly than wet oxides, resulting in higher density, higher breakdown field strengths, and more controlled growth, making them ideal for metal-oxide semiconductor(MOS)gate dielectrics Wet oxidation is used for forming thick oxides for field isolation and masking implants and diffusions. The slight degradation in oxide density is more than compensated for by the thickness in these application substrates have fewer dangling bonds at the surface, which results in lower fixed oxide charge and interface traps and therefore higher quality MOS devices. Conventional dopants(B, P, As, and Sb)diffuse slowly in both wet ai oxides and hence these oxides provide a good barrier for masking diffusions in integrated circuit fabrication High-pressure steam oxidations provide a means for growing relatively thick oxides in reasonable times at low temperatures to avoid dopant diffusion. Conversely, low-pressure oxidations show promise for forming controlled ultra thin gate growth for ULSI technologies. Chlorine added to gate oxides [Sze, 1988] has been shown to reduce mobile ions, reduce oxide defects, increase breakdown voltage, reduce fixed oxide charge and interface traps, reduce oxygen-induced stacking faults, and increase substrate minority carrier lifetime. Chlorine is introduced into dry oxidations in less tha 5%concentrations as anhydrous HCl gas or by trichloroethylene(TCE)or trichloroethane(TCA) Dopant Segregation and Redistribution Since silicon is consumed during the oxidation process, the dopant in the substrate will redistribute due to segregation[ Wolf and Tauber, 1986]. The boundary condition across the Si/SiO2 interface is that the chemical potential of the dopant is the same on both sides. This results in the definition of a segregation coefficient, m, as the ratio of the equilibrium concentration of dopant in Si to SiO. Depending on the value of m(i. e, less than or greater than 1)and the diffusion properties of the dopant SiO,, various redistributions are possible. For example, m=0. for boron and it is a slow diffuser in Sio2 o it tends to deplete from the Si surface and accumulate in the oxide at the Si/Sio2 interface. Phosphorus, on the other hand, has m=10, is also a slow diffuser in SiO2, and tends to pile up in the Si at the Si/Sio2 interface Antimony and arsenic behave similarly to phosphorus Diffusion Diffusion was the traditional way dopants were introduced into silicon wafers to create junctions and control the resistivity of layers. Ion implantation has now superseded diffusion for this purpose. The principles and concepts of diffusion theory, however, remain important since they describe the movement and transport of dopants and impurities during the high-temperature processing steps of integrated circuit manufacture. Diffusion mechanism Consider a silicon wafer with a high concentration of an impurity on its surface. At any temperature there ar a certain number of vacancies in the Si lattice. If the wafer is subjected to an elevated temperature, the number of vacancies in the silicon will increase and the impurity will enter the wafer moving from the high surface concentration to redistribute in the bulk. The redistribution mechanism is diffusion, and dependi impurity type it will either be substitutional or interstitial [Ghandhi, 1982] For substitutional diffusion the impurity atom substitutes for a silicon atom at a vacancy lattice site and then progresses into the wafer by hopping from lattice site to lattice site via the vacancies. Clearly, the hopping can e in a random direction; however, since the impurity is present initially in high concentration on the surface only, there is a net flow of the impurity from the surface into the bulk, c2000 by CRC Press LLC

© 2000 by CRC Press LLC Oxidation rate depends on substrate orientation [Ghandhi, 1968]. This effect is related to the surface atom density of the substrate, i.e., the higher the density, the faster the oxidation rate. Oxidation rate also depends on pressure. The linear and parabolic rates are dependent on the equilibrium concentration of the oxidizing species in the SiO2 which is directly proportional to the partial pressure of the oxidant in the ambient. Oxide growth rate shows a doping dependence for heavily doped substrates (>1020 cm–3). Boron increases the parabolic rate constant and phosphorus enhances the linear rate constant [Wolf and Tauber, 1986]. Oxide Characteristics Dry oxides grow more slowly than wet oxides, resulting in higher density, higher breakdown field strengths, and more controlled growth, making them ideal for metal-oxide semiconductor (MOS) gate dielectrics. Wet oxidation is used for forming thick oxides for field isolation and masking implants and diffusions. The slight degradation in oxide density is more than compensated for by the thickness in these applications. substrates have fewer dangling bonds at the surface, which results in lower fixed oxide charge and interface traps and therefore higher quality MOS devices. Conventional dopants (B, P, As, and Sb) diffuse slowly in both wet and dry oxides and hence these oxides provide a good barrier for masking diffusions in integrated circuit fabrication. High-pressure steam oxidations provide a means for growing relatively thick oxides in reasonable times at low temperatures to avoid dopant diffusion. Conversely, low-pressure oxidations show promise for forming controlled ultra thin gate growth for ULSI technologies. Chlorine added to gate oxides [Sze, 1988] has been shown to reduce mobile ions, reduce oxide defects, increase breakdown voltage, reduce fixed oxide charge and interface traps, reduce oxygen- induced stacking faults, and increase substrate minority carrier lifetime. Chlorine is introduced into dry oxidations in less than 5% concentrations as anhydrous HCl gas or by trichloroethylene (TCE) or trichloroethane (TCA). Dopant Segregation and Redistribution Since silicon is consumed during the oxidation process, the dopant in the substrate will redistribute due to segregation [Wolf and Tauber, 1986]. The boundary condition across the Si/SiO2 interface is that the chemical potential of the dopant is the same on both sides. This results in the definition of a segregation coefficient, m, as the ratio of the equilibrium concentration of dopant in Si to the equilibrium concentration of dopant in SiO2. Depending on the value of m (i.e., less than or greater than 1) and the diffusion properties of the dopant in SiO2, various redistributions are possible. For example, m ª 0.3 for boron and it is a slow diffuser in SiO2, so it tends to deplete from the Si surface and accumulate in the oxide at the Si/SiO2 interface. Phosphorus, on the other hand, has m ª 10, is also a slow diffuser in SiO2, and tends to pile up in the Si at the Si/SiO2 interface. Antimony and arsenic behave similarly to phosphorus. Diffusion Diffusion was the traditional way dopants were introduced into silicon wafers to create junctions and control the resistivity of layers. Ion implantation has now superseded diffusion for this purpose. The principles and concepts of diffusion theory, however, remain important since they describe the movement and transport of dopants and impurities during the high-temperature processing steps of integrated circuit manufacture. Diffusion Mechanism Consider a silicon wafer with a high concentration of an impurity on its surface. At any temperature there are a certain number of vacancies in the Si lattice. If the wafer is subjected to an elevated temperature, the number of vacancies in the silicon will increase and the impurity will enter the wafer moving from the high surface concentration to redistribute in the bulk. The redistribution mechanism is diffusion, and depending on the impurity type it will either be substitutional or interstitial [Ghandhi, 1982]. For substitutional diffusion the impurity atom substitutes for a silicon atom at a vacancy lattice site and then progresses into the wafer by hopping from lattice site to lattice site via the vacancies. Clearly, the hopping can be in a random direction; however, since the impurity is present initially in high concentration on the surface only, there is a net flow of the impurity from the surface into the bulk

In the case of interstitial diffusion the impurity diffuses by squeezing between the lattice atoms and taking residence in the interstitial space between lattice sites. Since this mechanism does not require the presence of a vacancy, it proceeds much faster than substitutional diffusion Conventional dopants such as B, P, As, and Sb diffuse by the substitutional method. This is beneficial in that the diffusion process is much slower and can therefore be controlled more easily in the manufacturing process. Many of the undesired impurities such as Fe, Cu, and other heavy metals diffuse by the interstitial mechanism and therefore the process is extremely fast. This again is beneficial in that at the temperatures used, and in the duration of fabri unwanted metals can diffuse completely through the Si wafer Gettering creates trapping sites on the back surface of the wafer for these impurities that would otherwise remain in the silicon and cause adverse device effects Regardless of the diffusion mechanism, it can be formalized mathematically in the same way by introducing a diffusion coefficient, D(cm2/sec), that accounts for the diffusion rate. The diffusion constants follow an behavi ng to the E where Do is the prefactor, EA the activation energy, k Boltzmanns constant, and T the absolute temperature. Conventional silicon dopants(substitutional diffusers) have diffusion coefficients on the order of 10-to 10-12 at 1100@C, whereas heavy metal interstitial diffusers(Fe, Au, and Cu) have diffusion coefficients of 10- to 10 at this temperature The diffusion process can be described using Ficks Laws. Ficks first law says that the flux of impurity, F crossing any plane is related to the impurity distribution, N(x, t)per cm, by (23.8) dx in the one-dimensional case. Ficks second law states that the time rate of change of the particle density in turn is related to the divergence of the particle flux: an dF 239) Combining these two equations gives an aaN a-N (23.10) in the case of a constant diffusion coefficient as is often assumed This partial differential equation can be solved by separation of variables or by Laplace transform techniques for specified boundary conditions For a constant source diffusion the impurity concentration at the surface of the wafer is throughout the diffusion process. Solution of Eq (23. 10)under these boundary conditions, asst infinite wafer, results in a complementary error function diffusion profile: c2000 by CRC Press LLC

© 2000 by CRC Press LLC In the case of interstitial diffusion the impurity diffuses by squeezing between the lattice atoms and taking residence in the interstitial space between lattice sites. Since this mechanism does not require the presence of a vacancy, it proceeds much faster than substitutional diffusion. Conventional dopants such as B, P, As, and Sb diffuse by the substitutional method. This is beneficial in that the diffusion process is much slower and can therefore be controlled more easily in the manufacturing process. Many of the undesired impurities such as Fe, Cu, and other heavy metals diffuse by the interstitial mechanism and therefore the process is extremely fast. This again is beneficial in that at the temperatures used, and in the duration of fabrication processes, the unwanted metals can diffuse completely through the Si wafer. Gettering creates trapping sites on the back surface of the wafer for these impurities that would otherwise remain in the silicon and cause adverse device effects. Regardless of the diffusion mechanism, it can be formalized mathematically in the same way by introducing a diffusion coefficient, D (cm2 /sec), that accounts for the diffusion rate. The diffusion constants follow an Arrhenius behavior according to the equation: (23.7) where D0 is the prefactor, EA the activation energy, k Boltzmann’s constant, and T the absolute temperature. Conventional silicon dopants (substitutional diffusers) have diffusion coefficients on the order of 10–14 to 10–12 at 1100°C, whereas heavy metal interstitial diffusers (Fe, Au, and Cu) have diffusion coefficients of 10–6 to 10–5 at this temperature. The diffusion process can be described using Fick’s Laws. Fick’s first law says that the flux of impurity, F, crossing any plane is related to the impurity distribution, N(x,t) per cm3 , by: (23.8) in the one-dimensional case. Fick’s second law states that the time rate of change of the particle density in turn is related to the divergence of the particle flux: (23.9) Combining these two equations gives: (23.10) in the case of a constant diffusion coefficient as is often assumed. This partial differential equation can be solved by separation of variables or by Laplace transform techniques for specified boundary conditions. For a constant source diffusion the impurity concentration at the surface of the wafer is held constant throughout the diffusion process. Solution of Eq. (23.10) under these boundary conditions, assuming a semiinfinite wafer, results in a complementary error function diffusion profile: (23.11) D D E kT A = -È Î Í Í ˘ ˚ ˙ ˙ 0 exp F D N x = ¶ ¶ ¶ ¶ ¶ ¶ N t F x = ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ N t x D N x D N x = Ê Ë Á ˆ ¯ ˜ = 2 2 N N x Dt (,) x t = Ê Ë Á ˆ ¯ 0 ˜ 2 erfc

Here, No is the impurity concentration at the surface of the wafer, x the distance into the wafer, and t the diffusion time. As time progresses the impurity profile penetrates deeper into the wafer while maintaining a constant surface concentration. The total number of impurity atoms/cm? in the wafer is the dose,Q,and continually increases with time Q Nadx 2N (23.12) For a limited source diffusion an impulse of impurity of dose Q is assumed to be deposited on the wafer surface. Solution of Eq.(23. 10)under these boundary conditions, assuming a semi-infinite wafer with no loss of impurity, results in a gaussian diffusion profile: (23.13) 2VDt In this case, as time progresses the impurity penetrates more deeply into the wafer and the surface concentration falls so as to maintain a constant dose in the wafer Practical diffusions Most real diffusions follow a two-step procedure, where the dopant is applied to the wafer with a short constant source diffusion then driven in with a limited source diffusion The reason for this is that in order to control the dose, a constant source diffusion must be done at the solid solubility limit of the impurity in the Si, which is on the order of 1020 for most dopants. If only a constant source diffusion were done, this would result in only very high surface concentrations. Therefore, to achieve lower concentrations, a short constant source diffusion to get a controlled dose of impurities in a near surface layer is done first. This diffusion is known as the predeposition or predep step. Then the source is removed and the dose is diffused into the wafer, simulating a limited source diffusion in the subsequent drive-in step. If the Dt product for the drive-in step is much greater than the Dt product for the predep, profile is very close to Gaussian. In this case the dose can be calculated by Eq (23.12)for the predep diffusion coefficient. This dose is then used in the limited source Eq (23. 13)to describe the final prof on the time and diffusion coefficient for the drive-in. If these Dt criteria are not met, then an integral solution exists for the evaluation of the resulting profiles [Ghandhi, 1968 Further profile considerations a wafer typically goes through many temperature cycles during fabrication, which can alter the impurity profile calculating a total Dt product r s that take place at different times and temperatures are accounted for by The effects of many thermal the diffusion that is equal to the sum of the individual process Dt products ∑ Here D, and t, are the diffusion coefficient and time that pertain to the ith process step Many diffusions are used to form junctions by diffusing an impurity opposite in type to the substrate. At the metallurgical junction, x,, the impurity diffusion profile has the same concentration as the substrate. For a junction with a surface concentration No and substrate doping N the metallurgical junction for a Gaussian x:=2 Dt In (23.15) c2000 by CRC Press LLC

© 2000 by CRC Press LLC Here, N0 is the impurity concentration at the surface of the wafer, x the distance into the wafer, and t the diffusion time. As time progresses the impurity profile penetrates deeper into the wafer while maintaining a constant surface concentration. The total number of impurity atoms/cm2 in the wafer is the dose, Q, and continually increases with time: (23.12) For a limited source diffusion an impulse of impurity of dose Q is assumed to be deposited on the wafer surface. Solution of Eq. (23.10) under these boundary conditions, assuming a semi-infinite wafer with no loss of impurity, results in a Gaussian diffusion profile: (23.13) In this case, as time progresses the impurity penetrates more deeply into the wafer and the surface concentration falls so as to maintain a constant dose in the wafer. Practical Diffusions Most real diffusions follow a two-step procedure, where the dopant is applied to the wafer with a short constant source diffusion, then driven in with a limited source diffusion. The reason for this is that in order to control the dose, a constant source diffusion must be done at the solid solubility limit of the impurity in the Si, which is on the order of 1020 for most dopants. If only a constant source diffusion were done, this would result in only very high surface concentrations. Therefore, to achieve lower concentrations, a short constant source diffusion to get a controlled dose of impurities in a near surface layer is done first. This diffusion is known as the predeposition or predep step. Then the source is removed and the dose is diffused into the wafer, simulating a limited source diffusion in the subsequent drive-in step. If the Dt product for the drive-in step is much greater than the Dt product for the predep, the resulting profile is very close to Gaussian. In this case the dose can be calculated by Eq. (23.12) for the predep time and diffusion coefficient. This dose is then used in the limited source Eq. (23.13) to describe the final profile based on the time and diffusion coefficient for the drive-in. If these Dt criteria are not met, then an integral solution exists for the evaluation of the resulting profiles [Ghandhi, 1968]. Further Profile Considerations A wafer typically goes through many temperature cycles during fabrication, which can alter the impurity profile. The effects of many thermal cycles that take place at different times and temperatures are accounted for by calculating a total Dt product for the diffusion that is equal to the sum of the individual process Dt products: (23.14) Here Di and ti are the diffusion coefficient and time that pertain to the ith process step. Many diffusions are used to form junctions by diffusing an impurity opposite in type to the substrate. At the metallurgical junction, xj , the impurity diffusion profile has the same concentration as the substrate. For a junction with a surface concentration N0 and substrate doping NB the metallurgical junction for a Gaussian profile is (23.15) Q N dx N Dt = = x t • Ú (,) 2 0 0 p N Q Dt x Dt (,) x t = exp – Ê Ë Á ˆ ¯ ˜ È Î Í Í ˘ ˚ ˙ ˙ p 2 2 ( ) Dt D ti i i tot = Â x Dt N N j B = Ê Ë Á ˆ ¯ ˜ 2 0 ln

and for a complementary error function profile is x ;=2v Dt erfc (23.16) ffected by the diffusion by using an oxide mask and making a cut in it where specific diffusion is to s are So far we have considered just vertical diffusion. In practical IC fabrication, usually only small Hence, we also have to be concerned with lateral diffusion of the dopant so as not to affect adjacent devices. Two-dimensional numerical solutions exist for solving this problem [Jaeger, 1988]; however, a useful rule thumb is that the lateral junction, y, is 0.8 Another parameter of interest is the sheet resistance of the diffused layer. This has been numerically evaluated for various profiles and presented as general-purpose graphs known as Irvin's curves For a given profile type, such as n-type Gaussian, Irvin's curves plot surface dopant concentration versus the product of sheet resistance and junction depth with substrate doping as a parameter. Thus, given a calculated diffusion profile one coul estimate the sheet resistivity for the diffused layer. Alternatively, given the measured junction depth and sheet resistance, one could estimate the surface concentration for a given profile and substrate doping. Most processing books [e.g. Jaeger, 1988] contain Irvin's curves Ion Implantation Diffusion places severe limits on device design, such as hard to control low-dose diffusions, no tailored profiles, and appreciable lateral diffusion at mask edges. Ion implantation overcomes all of these drawbacks and is an alternative approach to diffusion used in the majority of production doping applications today. Although many different elements can be implanted, IC manufacture is primarily interested in B, P, As, and Sb Ion Implant Technology A schematic drawing of an ion implanter is shown in Fig 23. 3. The ion source operates at relatively high voltage (20-25 kV) and for conventional dopants is usually a gaseous type which extracts the ions from a plasma The ions are mass separated with a 90 degree analyzer magnet that directs the selected species through resolving aperture focused and accelerated to the desired implant energy. At the other end of the implanter is the target chamber where the wafer is placed in the beam path. The beam line following the final accelerator and the target chamber are held at or near ground potential for safety reasons. After final acceleration the beam is bent slightly off axis to trap neutrals and is asynchronously scanned in the X and Y directions over the wafer to maintain dose uniformity. This is often accompanied by rotation and sometimes translation of the target The implant parameters of interest are the ion species, implant energy, and dose. The ion species can consist of singly ionized elements, doubly ionized elements, or ionized molecules. The molecular species are of interest in forming shallow junctions with light ions, i.e, B, using BF=. The beam energy is (23.17) where n represents the ionization state(1 for singly and 2 for doubly ionized species), q the electronic charge, and V the total acceleration potential (source acceleration tube)seen by the beam. The dose, Q, from the implanter is dt (23.18) where I is the beam current in amperes, A the wafer area in cm?, t, the implant time in sec, and n the ionization state c2000 by CRC Press LLC

© 2000 by CRC Press LLC and for a complementary error function profile is (23.16) So far we have considered just vertical diffusion. In practical IC fabrication, usually only small regions are affected by the diffusion by using an oxide mask and making a cut in it where specific diffusion is to occur. Hence, we also have to be concerned with lateral diffusion of the dopant so as not to affect adjacent devices. Two-dimensional numerical solutions exist for solving this problem [Jaeger, 1988]; however, a useful rule of thumb is that the lateral junction, yj , is 0.8xj . Another parameter of interest is the sheet resistance of the diffused layer. This has been numerically evaluated for various profiles and presented as general-purpose graphs known as Irvin’s curves. For a given profile type, such as n-type Gaussian, Irvin’s curves plot surface dopant concentration versus the product of sheet resistance and junction depth with substrate doping as a parameter. Thus, given a calculated diffusion profile one could estimate the sheet resistivity for the diffused layer. Alternatively, given the measured junction depth and sheet resistance, one could estimate the surface concentration for a given profile and substrate doping.Most processing books [e.g., Jaeger, 1988] contain Irvin’s curves. Ion Implantation Diffusion places severe limits on device design, such as hard to control low-dose diffusions, no tailored profiles, and appreciable lateral diffusion at mask edges. Ion implantation overcomes all of these drawbacks and is an alternative approach to diffusion used in the majority of production doping applications today. Although many different elements can be implanted, IC manufacture is primarily interested in B, P, As, and Sb. Ion Implant Technology A schematic drawing of an ion implanter is shown in Fig. 23.3. The ion source operates at relatively high voltage (ª20–25 kV) and for conventional dopants is usually a gaseous type which extracts the ions from a plasma. The ions are mass separated with a 90 degree analyzer magnet that directs the selected species through a resolving aperture focused and accelerated to the desired implant energy. At the other end of the implanter is the target chamber where the wafer is placed in the beam path. The beam line following the final accelerator and the target chamber are held at or near ground potential for safety reasons. After final acceleration the beam is bent slightly off axis to trap neutrals and is asynchronously scanned in the X and Y directions over the wafer to maintain dose uniformity. This is often accompanied by rotation and sometimes translation of the target wafer also. The implant parameters of interest are the ion species, implant energy, and dose. The ion species can consist of singly ionized elements, doubly ionized elements, or ionized molecules. The molecular species are of interest in forming shallow junctions with light ions, i.e., B, using BF2 +. The beam energy is E = nqV (23.17) where n represents the ionization state (1 for singly and 2 for doubly ionized species), q the electronic charge, and V the total acceleration potential (source + acceleration tube) seen by the beam. The dose, Q, from the implanter is (23.18) where I is the beam current in amperes, A the wafer area in cm2 , tI the implant time in sec, and n the ionization state. x Dt N N j B = Ê Ë Á ˆ ¯ ˜ - 2 1 0 erfc Q I nqA dt t I = Ú0

which can be related to the implant conditions by Eq (23.18 Implant doses can range from 100 to 108 per cm2 and can be controlled within a few percent. The mathematical representation of the implant profile just 2 presented really pertains to an amorphous substrate. Si wafers are crystalline and therefore present the opportunity 0.o1 for the ions to travel much deeper into the substrate by a process known as channeling. The regular arrangement of atoms in the crystalline lattice leaves large amounts of open space that appear as channels into the bulk when viewed from he major orientation directions, i. e, ,, and . Practical implants are usually done through a thin FIGURE 23.5 Implant straggle for B, P, and As oxide with the wafers tilted off normal by a small angle(typ- based on LSS calculations. ally 7 degrees)and rotated by 30 degrees to make the surface atoms appear more random. Implants with these conditions agree well with the projected range curves of Fig. 23.4, indicating the wafers do appear Actual implant profiles deviate from the simple Gaussian profiles described in the previous paragraphs Light ns tend to backscatter from target atoms and fill in the distribution on the surface side of the peak. Heavy atoms tend to forward scatter from the target atoms and fill in the profile on the substrate side of the pea This behavior has been modeled with distributions such as the Pearson Type-IV distribution [Jaeger, 1988] However, for implant energies below 200 keV and first-order calculations, the Gaussian model will more than Masking and Junction Formation Usually it is desired to implant species only in selected areas of the wafer to alter or create device properties, and hence the implant must be masked. This is done by putting a thick layer of silicon dioxide, silicon nitride, or photoresist on the wafer and patterning and opening the layer where the implant is desired. To prevent significant alteration of the substrate doping in the mask regions the implant concentration at the Si/mask interface, Xo, must be less than 1/10 of the substrate doping, No Under these conditions Eq.(23 19)can be solved for the required mask thickness as: 10N Rp +△R。2ln (23.21) NB This implies that the range and straggle are known for the mask material being used. These are available in the terature [Gibbons et al., 1975] but can also be reasonably approximated by making the calculations for Si. Sio2 is assumed to have the same stopping power as Si and thus would have the same mask thickness. Silicon nitride has more stopping power than Sio, and therefore requires only 85% of calculated mask thickness, whereas photoresist is less effective for stopping the ions and requires 1. 8 times the equivalent Si thickness Analogous to the mask calculations is junction formation. Here, the metallurgical junction, x;, occurs when ne opposite type implanted profile is equal to the substrate doping, NE Solving Eq (23. 19)for these conditions x=±△R,2l (23.22) Note that both roots may be applicable depending on the depth of the implant. c2000 by CRC Press LLC

© 2000 by CRC Press LLC which can be related to the implant conditions by Eq. (23.18). Implant doses can range from 1010 to 1018 per cm2 and can be controlled within a few percent. The mathematical representation of the implant profile just presented really pertains to an amorphous substrate. Silicon wafers are crystalline and therefore present the opportunity for the ions to travel much deeper into the substrate by a process known as channeling. The regular arrangement of atoms in the crystalline lattice leaves large amounts of open space that appear as channels into the bulk when viewed from the major orientation directions, i.e, , , and . Practical implants are usually done through a thin oxide with the wafers tilted off normal by a small angle (typically 7 degrees) and rotated by 30 degrees to make the surface atoms appear more random. Implants with these conditions agree well with the projected range curves of Fig. 23.4, indicating the wafers do appear amorphous. Actual implant profiles deviate from the simple Gaussian profiles described in the previous paragraphs. Light ions tend to backscatter from target atoms and fill in the distribution on the surface side of the peak. Heavy atoms tend to forward scatter from the target atoms and fill in the profile on the substrate side of the peak. This behavior has been modeled with distributions such as the Pearson Type-IV distribution [Jaeger, 1988]. However, for implant energies below 200 keV and first- order calculations, the Gaussian model will more than suffice. Masking and Junction Formation Usually it is desired to implant species only in selected areas of the wafer to alter or create device properties, and hence the implant must be masked. This is done by putting a thick layer of silicon dioxide, silicon nitride, or photoresist on the wafer and patterning and opening the layer where the implant is desired. To prevent significant alteration of the substrate doping in the mask regions the implant concentration at the Si/mask interface, X0 , must be less than 1/10 of the substrate doping, NB. Under these conditions Eq. (23.19) can be solved for the required mask thickness as: (23.21) This implies that the range and straggle are known for the mask material being used. These are available in the literature [Gibbons et al., 1975] but can also be reasonably approximated by making the calculations for Si. SiO2 is assumed to have the same stopping power as Si and thus would have the same mask thickness. Silicon nitride has more stopping power than SiO2 and therefore requires only 85% of calculated mask thickness, whereas photoresist is less effective for stopping the ions and requires 1.8 times the equivalent Si thickness. Analogous to the mask calculations is junction formation. Here, the metallurgical junction, xj , occurs when the opposite type implanted profile is equal to the substrate doping, NB. Solving Eq. (23.19) for these conditions gives the junction depth as: (23.22) Note that both roots may be applicable depending on the depth of the implant. XR R N N p p p B 0 2 10 = + Ê Ë Á ˆ ¯ D ˜ ln XR R N N jp p p B = ± Ê Ë Á ˆ ¯ D ˜ 2 ln FIGURE 23.5 Implant straggle for B, P, and As based on LSS calculations