Carpenter, G.L., Choma, Jr,J. Amplifiers The Electrical Engineering Handbook Ed. Richard C. Dorf Boca raton crc Press llc. 2000
Carpenter, G.L., Choma, Jr., J. “Amplifiers” The Electrical Engineering Handbook Ed. Richard C. Dorf Boca Raton: CRC Press LLC, 2000
28 amplifiers DC Operating Point. Graphical Approach.Power Amplifiers Gordon L. Carpenter 8.2 Small Signal Analysis Hybrid-Pi Equivalent Circuit. Hybrid-Pi Equivalent Circuit of a MonolithicBt.commOnEmitterAmplifier.design hn Choma, ]r Considerations for the Common Emitter Amplifier. Common Base Amplifier. Design Considerations for the Common Base University of Southern california Amplifier.commonCollectorAmplifier 28.1 Large Signal Analysis Gordon L. Carpenter Large signal amplifiers are usually confined to using bipolar transistors as their solid state devices because of the large linear region of amplification required. One exception to this is the use of VMOS for large por outputs due to their ability to have a large linear region. There are three basic configurations of amplifiers common emitter(CE)amplifiers, common base(CB)amplifiers, and common collection(CC)amplifiers. The basic configuration of each is shown in Fig. 28.1 In an amplifier system, the last stage of a voltage amplifier string has to be considered as a large signal amplifier, and generally EF amplifiers are used as large signal amplifiers. This then requires that the dc bias or dc operating point (quiescent point) be located near the center of the load line in order to get the maximum output voltage swing. Small signal analysis can be used to evaluate the amplifier for voltage gain, current gain, input impedance, and output impedance, all of which are discussed later. DC Operating Point Each transistor connected in a particular amplifier configuration has a set of characteristic curves, as show When amplifiers are coupled together with capacitors, the configuration is as shown in Fig. 28. 3. The load resistor is really the input im of the next stage. To be able to evaluate this amplifier, a dc equivalent circuit needs to be developed n in Fig. 28.4. This will result in the following dc bias equation Assume h >>1 R where beta(heE) is the current gain of the transistor and vae is the conducting voltage across the base-emitter junction. This equation is the same for all amplifier configurations. Looking at Fig. 28.3, the input circuit can be reduced to the dc circuit shown in Fig. 28.4 using circuit analysis techniques, resulting in the following c 2000 by CRC Press LLC
© 2000 by CRC Press LLC 28 Amplifiers 28.1 Large Signal Analysis DC Operating Point • Graphical Approach • Power Amplifiers 28.2 Small Signal Analysis Hybrid-Pi Equivalent Circuit • Hybrid-Pi Equivalent Circuit of a Monolithic BJT • Common Emitter Amplifier • Design Considerations for the Common Emitter Amplifier • Common Base Amplifier • Design Considerations for the Common Base Amplifier • Common Collector Amplifier 28.1 Large Signal Analysis Gordon L. Carpenter Large signal amplifiers are usually confined to using bipolar transistors as their solid state devices because of the large linear region of amplification required. One exception to this is the use of VMOS for large power outputs due to their ability to have a large linear region. There are three basic configurations of amplifiers: common emitter (CE) amplifiers, common base (CB) amplifiers, and common collection(CC) amplifiers. The basic configuration of each is shown in Fig. 28.1. In an amplifier system, the last stage of a voltage amplifier string has to be considered as a large signal amplifier, and generally EF amplifiers are used as large signal amplifiers. This then requires that the dc bias or dc operating point (quiescent point) be located near the center of the load line in order to get the maximum output voltage swing. Small signal analysis can be used to evaluate the amplifier for voltage gain, current gain, input impedance, and output impedance, all of which are discussed later. DC Operating Point Each transistor connected in a particular amplifier configuration has a set of characteristic curves, as shown in Fig. 28.2. When amplifiers are coupled together with capacitors, the configuration is as shown in Fig. 28.3. The load resistor is really the input impedance of the next stage. To be able to evaluate this amplifier, a dc equivalent circuit needs to be developed as shown in Fig. 28.4. This will result in the following dc bias equation: where beta (hFE) is the current gain of the transistor and VBE is the conducting voltage across the base-emitter junction. This equation is the same for all amplifier configurations. Looking at Fig. 28.3, the input circuit can be reduced to the dc circuit shown in Fig. 28.4 using circuit analysis techniques, resulting in the following equations: I V V R R h CQ BB BE B E FE = - + >> beta Assume 1 Gordon L. Carpenter California State University, Long Beach John Choma, Jr. University of Southern California
Rc RB Re o RE (a)Common en (b)Common collector (c)Common base (emitter follower FIGURE 28. 1 Amplifier circuits. (Source: C J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed, Redwood City, Calif. Benjamin-Cummings, 1991, P 80. With permission. Load line 0.3 0.2(mA) Cutoff res FIGURE 28. 2 Transistor characteristic curves. Source: C J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed, Redwood City, Calif. Benjamin-Cummings, 1991, P. 82. with permission. Rc E R Re RI ie FIGURE 28.3 Amplifier circuit. Source: C ]. Savant, M. FIGURE 28.4 Amplifier equivalent circuit. Source: C ]. oden, and G. Carpenter, Electronic Design, Circuits and Savant, M. Roden, and G. Carpenter, Electronic Design, ystems, 2nd ed, Redwood City, Calif. Benjamin-Cum Circuits and Systems, 2nd ed, Redwood City, Calif. Ben- mings,1991,P. 92. With permission min-Cummings, 1991,P. 82. With permission c 2000 by CRC Press LLC
© 2000 by CRC Press LLC FIGURE 28.1 Amplifier circuits. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 80. With permission.) FIGURE 28.2 Transistor characteristic curves. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 82. With permission.) FIGURE 28.3 Amplifier circuit. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 92. With permission.) FIGURE 28.4 Amplifier equivalent circuit. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 82. With permission.)
VBB= VTH= VCC(RI/(R,+ R2) RB=RTH=rIIR2 or this biasing system, the Thevenin equivalent resistance and the Thevenin equivalent voltage can be deter- mined. For design with the biasing system shown in Fig. 28.3, then R=RB/(l-VBB/VaO R2=RB(Vcc/VE Graphical Approach To understand the graphical approach, a clear understanding of the dc and ac load lines is necessary. The dc load line is based on the Kirchhoffs equation from the dc power source to ground(all capacitors open CC- VCE+ icR DC where roc is the sum of the resistors in the collector-emitter loop The ac load line is the loop, assuming the transistor is the ac source and the source voltage is zero, where Rar is the sum of series resistors in that loop with all the capacitors shorted. The load lines then can be constructed on the characteristic curves as shown in Fig. 28.5. From this it can be seen that to get the maximum output voltage swing, the quiescent point, or Q point, should be located in the middle of the ac load line. To place the Q point in the middle of the ac load line, Ico can be determined from the equation Ioo= vccl(nc +.d) icQ =lc ac load line with slope load line with slope Vce Vcc EQ IGURE 28.5 Load lines. (Source: C J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd d, Redwood City, Calif. Benjamin-Cummings, 1991, P. 94. With permission. c 2000 by CRC Press LLC
© 2000 by CRC Press LLC VBB = VTH = VCC (R1)/(R1 + R2) RB = RTH = R1//R2 For this biasing system, the Thévenin equivalent resistance and the Thévenin equivalent voltage can be determined. For design with the biasing system shown in Fig. 28.3, then: R1 = RB /(1 – VBB /VCC) R2 = RB (VC C /VBB) Graphical Approach To understand the graphical approach, a clear understanding of the dc and ac load lines is necessary. The dc load line is based on the Kirchhoff’s equation from the dc power source to ground (all capacitors open) VCC = vCE + iC RDC where RDC is the sum of the resistors in the collector-emitter loop. The ac load line is the loop, assuming the transistor is the ac source and the source voltage is zero, then V¢ CC = vce + iC Rac where Rac is the sum of series resistors in that loop with all the capacitors shorted. The load lines then can be constructed on the characteristic curves as shown in Fig. 28.5. From this it can be seen that to get the maximum output voltage swing, the quiescent point, or Q point, should be located in the middle of the ac load line. To place the Q point in the middle of the ac load line, ICQ can be determined from the equation ICQ = VCC /(RDC + Rac) FIGURE 28.5 Load lines. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 94. With permission.)
Extreme nonlinear region (saturation region) in middle of load line ct FIGURE 28.6 Q point in middle of load line. Source: C ] Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed,, Redwood City, Calif Benjamin-Cummings, 1991, P 135. With permission. To minimize distortion caused by the cutoff and saturation regions, the top 5%and the bottom 5% are discarded. This then results in the equation( Fig. 28.6 Vo(peak to peak)=2(0.9)IcQ(rc/R If, however, the Q point is not in the middle of the ac load line, the output voltage swing will be reduced. Below the middle of the ac load line[Fig. 28.7(a)] )=2(l-0.05Iox)Rc∥/R2 Above the middle of the ac load line [Fig. 28.7(b): Vo(peak to peak)=2(0.95 IoMax-Ico)Rc/RL These values allow the highest allowable input signal to be used to avoid any distortion by dividing the voltage gain of the amplifier into the maximum output voltage swing. The preceding equations are the same for the CB configuration For the EF configurations, the Rc is changed to Re in the equations ac load line elector load line (a)l below middle of ac load line (b)Ico above middle of ac load line FIGURE 28. 7 Reduced output voltage swing. (Source: C. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed, Redwood City, Calif Benjamin-Cummings, 1991, P. 136. With permission
© 2000 by CRC Press LLC To minimize distortion caused by the cutoff and saturation regions, the top 5% and the bottom 5% are discarded. This then results in the equation (Fig. 28.6): Vo (peak to peak) = 2 (0.9) ICQ (RC //RL) If, however, the Q point is not in the middle of the ac load line, the output voltage swing will be reduced. Below the middle of the ac load line [Fig. 28.7(a)]: Vo (peak to peak) = 2 (ICQ – 0.05 I CMax) RC //RL Above the middle of the ac load line [Fig. 28.7(b)]: Vo (peak to peak) = 2 (0.95 I CMax – ICQ) RC //RL These values allow the highest allowable input signal to be used to avoid any distortion by dividing the voltage gain of the amplifier into the maximum output voltage swing. The preceding equations are the same for the CB configuration. For the EF configurations, the RC is changed to RE in the equations. FIGURE 28.6 Q point in middle of load line. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 135. With permission.) FIGURE 28.7 Reduced output voltage swing. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 136. With permission.)
FIGURE 28.8 Complementary symmetry power amplifier. Source: C J. Savant, M. Roden, and G. Carpenter, Electroni Design, Circuits and Systems, 2nd ed, Redwood City, Calif. Benjamin-Cummings, 1991, P. 248. with permission.) Power Amplifiers Emitter followers can be used as power amplifiers. Even though they have less than unity voltage gain they can rovide high current gain. Using the standard linear EF amplifier for a maximum output voltage swing provides less than 25% efficiency(ratio of power in to power out). The dc current carrying the ac signal is where the loss of efficiency occurs. To avoid this power loss, the Q point is placed at Ico equal to zero, thus using the majority of the power for the output signal. This allows the efficiency to increase to as much as 70%. Full signal amplification requires one transistor to amplify the positive portion of the input signal and another transistor to amplify the negative portion of the input signal. In the past, this was referred to as push-pull operation. A better system is to use an NPn transistor for the positive part of the input signal and a PnP transistor for the negative part. This type of operation is referred to as Class B complementary symmetry operation(Fig. 28. 8) In Fig. 28.8, the dc voltage drop across R, provides the voltage to bias the transistor at cutoff. Because these are power transistors, the temperature will change based on the amount of power the transistor is absorbing This means the base-emitter junction voltage will have to change to keep Ico=0. To compensate for this change in temperature, the R, resistors are replaced with diodes or transistors connected as diodes with the same turn on characteristics as the power transistors. This type of configuration is referred to as the complementary compensated(CSDC)amplifier and is shown in Fig. 28.9. To avoid crossover distortion, small resistors can be placed in series with the diodes so that Ico can be raised slightly above zero to get increased amplification in the cutoff region. Another problem that needs to be addressed is the possibility of thermal runaway. This can be easily solved by placing small resistors in series with the emitters of the power transistors. For example, if the load is an 8-Q2 speaker, the resistors should not be greater than 0.47 2 to avoid output To design this type of amplifier, the dc current in the bias circuit must be large enough so that the diodes remain on during the entire input signal. This requires the de diode current to be equal to or larger than the zero to peak current of the input signal,or D≥l(0 to peak) (VcC2-VBE/R2=IB(O ) V(O to peak)/R
© 2000 by CRC Press LLC Power Amplifiers Emitter followers can be used as power amplifiers. Even though they have less than unity voltage gain they can provide high current gain. Using the standard linear EF amplifier for a maximum output voltage swing provides less than 25% efficiency (ratio of power in to power out). The dc current carrying the ac signal is where the loss of efficiency occurs. To avoid this power loss, the Q point is placed at ICQ equal to zero, thus using the majority of the power for the output signal. This allows the efficiency to increase to as much as 70%. Full signal amplification requires one transistor to amplify the positive portion of the input signal and another transistor to amplify the negative portion of the input signal. In the past, this was referred to as push-pull operation. A better system is to use an NPN transistor for the positive part of the input signal and a PNP transistor for the negative part. This type of operation is referred to as Class B complementary symmetry operation (Fig. 28.8). In Fig. 28.8, the dc voltage drop across R1 provides the voltage to bias the transistor at cutoff. Because these are power transistors, the temperature will change based on the amount of power the transistor is absorbing. This means the base-emitter junction voltage will have to change to keep ICQ = 0. To compensate for this change in temperature, the R1 resistors are replaced with diodes or transistors connected as diodes with the same turnon characteristics as the power transistors. This type of configuration is referred to as the complementary symmetry diode compensated (CSDC) amplifier and is shown in Fig. 28.9. To avoid crossover distortion, small resistors can be placed in series with the diodes so that ICQ can be raised slightly above zero to get increased amplification in the cutoff region. Another problem that needs to be addressed is the possibility of thermal runaway. This can be easily solved by placing small resistors in series with the emitters of the power transistors. For example, if the load is an 8-W speaker, the resistors should not be greater than 0.47 W to avoid output signal loss. To design this type of amplifier, the dc current in the bias circuit must be large enough so that the diodes remain on during the entire input signal. This requires the dc diode current to be equal to or larger than the zero to peak current of the input signal, or ID ³ Iac (0 to peak) (VCC /2 – VBE)/R2 = IB (0 to peak) + VL (0 to peak)/R2 FIGURE 28.8 Complementary symmetry power amplifier. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 248. With permission.)
VRn< R2 D, C? D2 RL R2 FIGURE 28.9 Complimentary symmetry diode compensated power amplifier. Source: C.J. Savant, M. Roden, and G Carpenter, Electronic Design, Circuits and Systems, 2nd ed, Redwood City, Calif. Benjamin-Cummings, 1991, P. 251. With Nonconducting RI R R2 BZL -B FIGURE 28.10 AC equivalent circuit of the CSDC amplifier. Source: C J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed, Redwood City, Calif. Benjamin-Cummings, 1991, P 255. With permission. When designing to a specific power, both Ig and Vi can be determined. This allows the selection of the value of R, and the equivalent circuit shown in Fig. 28. 10 can be developed. Using this equivalent circuit, both the input resistance and the current gain can be shown. R is the forward resistance of the diodes Rin=(r+ R2)//[R+(r2//Beta ruI P。= ICma r2/2 The power rating of the transistors to be used in this circuit should be greater than d(pIrI) C1=1/(2Pif。wR2) C2=10/2Pif。(Rn+R) where R, is the output impedance of the previous stage and fow is the desired low frequency cutoff of the amplifier Related Topics 24.1 Junction Field-Effect Transistors. 30.1 Power Semiconductor Devices c 2000 by CRC Press LLC
© 2000 by CRC Press LLC When designing to a specific power, both IB and VL can be determined. This allows the selection of the value of R2 and the equivalent circuit shown in Fig. 28.10 can be developed. Using this equivalent circuit, both the input resistance and the current gain can be shown. Rf is the forward resistance of the diodes. Rin = (Rf + R2)//[Rf + (R2 //Beta RL)] Po = ICmaxRL/2 The power rating of the transistors to be used in this circuit should be greater than Prating = V2 C C/(4Pi2RL) C1 = 1/(2Pi flowRL ) C2 = 10/[2Pi flow(Rin + Ri )] where Ri is the output impedance of the previous stage and f low is the desired low frequency cutoff of the amplifier. Related Topics 24.1 Junction Field-Effect Transistors • 30.1 Power Semiconductor Devices FIGURE 28.9 Complimentary symmetry diode compensated power amplifier. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 251. With permission.) FIGURE 28.10 AC equivalent circuit of the CSDC amplifier. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 255. With permission.)
References PR Gray and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, New York: Wiley, 1984 . Millman and A grabel, Microelectronics, New York: McGraw-Hill, 1987. P.O. Neudorfer and M. Hassul, Introduction to Circuit Analysis, Needham Heights, Mass. Allyn and Bacon, 1990 C J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed, Redwood City, Calif. D L. Schilling and C. Belove, Electronic Circuits, New York: McGraw-Hill, 1989 28.2 Small Signal analysis John Choma, r This section introduces the reader to the analytical methodologies that underlie the design of small signal, alog bipolar junction transistor(BJT) amplifiers. Analog circuit and system design entails complementin basic circuit analysis skills with the art of architecting a circuit topology that produces acceptable input-to- utput(I/O) electrical characteristics. Because design is not the inverse of analysis, analytically proficient engineers are not necessarily adept at design. However, circuit and system analyses that conduce an insightful understanding of meaningful topological structures arguably foster design creativity. Accordingly, this section focuses more on the problems of interpreting analytical results in terms of their circuit performance implica tions than it does on enhancing basic circuit analysis skills. Insightful interpretation breeds engineering understanding. In turn, such an understanding of the electrical properties of circuits promotes topological refinements and innovations that produce reliable and manufacturable, high performance electronic circuits Hybrid-Pi Equivalent Circuit In order for a BJT to function properly in linear amplifier applications, it must operate in the forward active region of its volt-ampere characteristic curves. Two conditions ensure B]T operation in the forward domain. First, the applied emitter-base terminal voltage must forward bias the intrinsic emitter-base junction diode at all times. Second, the instantaneous voltage established across the base-collector terminals of the transistor must preclude a forward biased intrinsic base-collector diode. The simultaneous satisfaction of these two conditions requires appropriate biasing subcircuits, and it imposes restrictions on the amplitudes of applied nput si ignals [Clarke and Hess, 1978] The most commonly used BJT equivalent circuit for investigating the dynamical responses to small input signals is the hybrid-pi model offered in Fig. 28.11 [Sedra and Smith, 1987 ]. In this model, R, R, and R respectively, represent the internal base, collector, and emitter resistances of the considered BJT. Although these series resistances vary somewhat with quiescent operating point [de Graaf, 1969), they can be viewed as constants in first-order manual analyses A COLLECTOR c EMITTER FIGURE 28. 11 The small signal equivalent circuit(hybrid-pi model)of a bipolar junction transistor. c 2000 by CRC Press LLC
© 2000 by CRC Press LLC References P.R. Gray and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, New York: Wiley, 1984. J. Millman and A. Grabel, Microelectronics, New York: McGraw-Hill, 1987. P.O. Neudorfer and M. Hassul, Introduction to Circuit Analysis, Needham Heights, Mass.: Allyn and Bacon, 1990. C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991. D.L. Schilling and C. Belove, Electronic Circuits, New York: McGraw-Hill, 1989. 28.2 Small Signal Analysis John Choma, Jr. This section introduces the reader to the analytical methodologies that underlie the design of small signal, analog bipolar junction transistor (BJT) amplifiers. Analog circuit and system design entails complementing basic circuit analysis skills with the art of architecting a circuit topology that produces acceptable input-tooutput (I/O) electrical characteristics. Because design is not the inverse of analysis, analytically proficient engineers are not necessarily adept at design. However, circuit and system analyses that conduce an insightful understanding of meaningful topological structures arguably foster design creativity. Accordingly, this section focuses more on the problems of interpreting analytical results in terms of their circuit performance implications than it does on enhancing basic circuit analysis skills. Insightful interpretation breeds engineering understanding. In turn, such an understanding of the electrical properties of circuits promotes topological refinements and innovations that produce reliable and manufacturable, high performance electronic circuits and systems. Hybrid-Pi Equivalent Circuit In order for a BJT to function properly in linear amplifier applications, it must operate in the forward active region of its volt–ampere characteristic curves. Two conditions ensure BJT operation in the forward domain. First, the applied emitter-base terminal voltage must forward bias the intrinsic emitter-base junction diode at all times. Second, the instantaneous voltage established across the base-collector terminals of the transistor must preclude a forward biased intrinsic base-collector diode. The simultaneous satisfaction of these two conditions requires appropriate biasing subcircuits, and it imposes restrictions on the amplitudes of applied input signals [Clarke and Hess, 1978]. The most commonly used BJT equivalent circuit for investigating the dynamical responses to small input signals is the hybrid-pi model offered in Fig. 28.11 [Sedra and Smith, 1987]. In this model, Rb , Rc , and Re , respectively, represent the internal base, collector, and emitter resistances of the considered BJT. Although these series resistances vary somewhat with quiescent operating point [de Graaf, 1969], they can be viewed as constants in first-order manual analyses. FIGURE 28.11 The small signal equivalent circuit (hybrid-pi model) of a bipolar junction transistor
The emitter-base junction diffusion resistance, Ra, is the small signal resistance of the emitter-base junction diode. It represents the inverse of the slope of the common emitter static input characteristic curves. Analyticall HEENEVr 28.1) where hFE is the static common emitter current gain of the B]T, Npis the emitter-base junction injection coefficient, Vr is the Boltzmann voltage corresponding to an absolute junction operating temperature of T, and Ico is the quiescent collector current. The expression for the resistance, Ro, which accounts for conductivity modulation in the neutral base, is (28.2) Iool l where VAr is the forward Early voltage, VcEo is the quiescent voltage developed across the internal collector emitter terminals, and IkF symbolizes the forward knee current. The knee current is a measure of the onset high injection effects[Gummel and Poon, 1970] in the base. In particular, a collector current numerically equal to IKF implies that the forward biasing of the emitter-base junction promotes a net minority carrier charge injected into the base from the emitter that is equal to the background majority charge in the neutral base. The Early voltage is an inverse measure of the slope of the common emitter output characteristic curves. The final low frequency parameter of the hybrid-pi model is the forward transconductance gm. This parameter, which is a measure of the forward small signal gain available at a quiescent operating point, is given by (28.3) Two capacitances, Cx and CHs are incorporated in the small signal model to provide a first-order approxi mation of steady-state transistor behavior at high signal frequencies. The capacitance, Cr, is the net capacitance of the emitter-base junction diode and is given by +t where the first term on the right-hand side represents the depletion component and the second term is the diffusion component of Cr. In Eq (28. 4), t, is the average forward transit time of minority carriers in the field neutral base, Ce is the zero bias value of emitter-base junction depletion capacitance, VJE is the built-in potential ction, Ve is the forward eloped across the intrinsic emitter-base j the grading coefficient of the junction. The capacitance, CH, has only a depletion component, owing to the reverse c 2000 by CRC Press LLC
© 2000 by CRC Press LLC The emitter-base junction diffusion resistance, Rp, is the small signal resistance of the emitter-base junction diode. It represents the inverse of the slope of the common emitter static input characteristic curves. Analytically, Rp is given by (28.1) where hFE is the static common emitter current gain of the BJT, NF is the emitter-base junction injection coefficient, VT is the Boltzmann voltage corresponding to an absolute junction operating temperature of T, and ICQ is the quiescent collector current. The expression for the resistance, Ro, which accounts for conductivity modulation in the neutral base, is (28.2) where VAF is the forward Early voltage, V¢ CEQ is the quiescent voltage developed across the internal collectoremitter terminals, and IKF symbolizes the forward knee current. The knee current is a measure of the onset of high injection effects [Gummel and Poon, 1970] in the base. In particular, a collector current numerically equal to IKF implies that the forward biasing of the emitter-base junction promotes a net minority carrier charge injected into the base from the emitter that is equal to the background majority charge in the neutral base. The Early voltage is an inverse measure of the slope of the common emitter output characteristic curves. The final low frequency parameter of the hybrid-pi model is the forward transconductance, gm. This parameter, which is a measure of the forward small signal gain available at a quiescent operating point, is given by (28.3) Two capacitances, Cp and Cm, are incorporated in the small signal model to provide a first-order approximation of steady-state transistor behavior at high signal frequencies. The capacitance, Cp , is the net capacitance of the emitter-base junction diode and is given by (28.4) where the first term on the right-hand side represents the depletion component and the second term is the diffusion component of Cp . In Eq. (28.4), tf is the average forward transit time of minority carriers in the fieldneutral base, CJE is the zero bias value of emitter-base junction depletion capacitance, VJE is the built-in potential of the junction, VE is the forward biasing voltage developed across the intrinsic emitter-base junction, and MJE is the grading coefficient of the junction. The capacitance, Cm, has only a depletion component, owing to the reverse R h NV I FE F T CQ p = R V V I I I o CEQ AF CQ CQ KF = ¢ + - Ê Ë Á ˆ ¯ ˜ 1 g I N V I I V V m CQ F T CQ KF CEQ AF = - + Ê Ë Á Á Á Á ˆ ¯ ˜ ˜ ˜ ˜ ¢ 1 1 C C V V V g JE E JE T M f m JE p t= - - Ê Ë Á ˆ ¯ ˜ + 1 2
gain.(b)High frequency small signal modelos t to the evaluation of the short circuit, common emitter, small signal current FIGURE 28. 12 (a)Schematic diagram pertin (or at most zero)bias impressed across the internal base-collector junction. Accordingly, its analytical form is analogous to the first term on the right-hand side of Eq(28.4). Specifically, (285) where the physical interpretation of Crc, VIc, and Mrc is analogous to CIE, VIE, and MIE, respectively A commonly invoked figure of merit for assessing the high speed, small signal performance attributes of B]T is the common emitter, short circuit gain-bandwidth product, Or, which is given by (286) The significance of Eq (28.6)is best appreciated by studying the simple circuit diagram of Fig. 28. 12(a), which depicts the grounded emitter configuration of a B]T biased for linear operation at a quiescent base current of for sn a quiescent collector-emitter voltage of VcEg. Note that the battery supplying Vceo grounds the collector for small signal conditions. The small signal model of the circuit at hand is resultantly seen to be the topology offered in Fig. 28.12(b), where igs and ics, respectively, denote the signal components of the net instantaneous base current, ig, and the net instantaneous collector current, i For negligibly small internal collector(R)and emitter(R )resistances, it can be shown that the small signal short circuit, high frequency common emitter current gain, Pa (jo), is expressible as 阝a(ji (287) where Bac, the low frequency value of Badjo), or simply the low frequency beta, is c 2000 by CRC Press LLC
© 2000 by CRC Press LLC (or at most zero) bias impressed across the internal base-collector junction. Accordingly, its analytical form is analogous to the first term on the right-hand side of Eq. (28.4). Specifically, (28.5) where the physical interpretation of CJ C, VJ C, and MJC is analogous to CJE , VJE , and MJE , respectively. A commonly invoked figure of merit for assessing the high speed, small signal performance attributes of a BJT is the common emitter, short circuit gain-bandwidth product, wT , which is given by (28.6) The significance of Eq. (28.6) is best appreciated by studying the simple circuit diagram of Fig. 28.12(a), which depicts the grounded emitter configuration of a BJT biased for linear operation at a quiescent base current of IB Q and a quiescent collector-emitter voltage of VCEQ . Note that the battery supplying VCEQ grounds the collector for small signal conditions. The small signal model of the circuit at hand is resultantly seen to be the topology offered in Fig. 28.12(b), where iBS and iCS , respectively, denote the signal components of the net instantaneous base current, iB, and the net instantaneous collector current, iC. For negligibly small internal collector (Rc) and emitter (Re) resistances, it can be shown that the small signal, short circuit, high frequency common emitter current gain, bac(jw), is expressible as (28.7) where bac, the low frequency value of bac(jw), or simply the low frequency beta, is FIGURE 28.12 (a) Schematic diagram pertinent to the evaluation of the short circuit, common emitter, small signal current gain. (b) High frequency small signal model of the circuit in part (a). C C V V V JC C JC T MJC m = - - Ê Ë Á ˆ ¯ ˜ 1 2 w p m T mg C C = + b w b w w w m b ac CS BS ac m j i i j C g j ( )D = - Ê Ë Á ˆ ¯ ˜ + 1 1