【例94】 工工 BRARY工EEE; USE IEEE STD LOGIC 1164.ALL: ENTITY p check工S PoRT a: IN STD LOGIC VECTOR (7 DOWNTo 0) Y: OUT STD LOGIC )i END p check; ARCHITECTURE opt of p check IS SIGNAL tmp: STD LOG工c BEG工N PROCESS (a) BEG工N tmp <=10 FOR n IN 0 TO 7 LOOP tmp < tmp XOR a(n)i END工ooP y < tmp; END PROCESS END optKX 康芯科技 【例9-4】 LIBRARY IEEE； USE IEEE.STD_LOGIC_1164.ALL； ENTITY p_check IS PORT ( a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); y : OUT STD_LOGIC ); END p_check； ARCHITECTURE opt OF p_check IS SIGNAL tmp ：STD_LOGIC ； BEGIN PROCESS(a) BEGIN tmp <='0'; FOR n IN 0 TO 7 LOOP tmp <= tmp XOR a(n); END LOOP ; y <= tmp; END PROCESS; END opt;