Exercise on 6.1, 4-bit Asyn Student ID Clock Counter plot count and Name Date: check delay (Submit this at the end of the lecture Write the port declaration Plot Q(1),Q(2),Q 3 including delays Count(o) Count(1) Count(2) Count(3) D(2 D(3) FF 少FF 少FF PFF cloc k ck'to(0)ck" Q(ck" TQ(2)ck"TQ(3) δt= time delay at one ff reset k CIoc Q(0)-t Q(1) Q(2) VHDL 6. examples of FSM ver. 8aExercise on 6.1, 4-bit Asyn. Clock Counter. Plot count, and check delay • Write the port declaration. • Plot Q(1),Q(2),Q(3) including delays VHDL 6. examples of FSM ver.8a 7 FF FF FF FF clock Count(0) Count(1) Count(2) Count(3) reset clock Q(0) Q(1) Q(2) Q(3) t= time delay at one FF ck Q(0) ck Q(1)ck Q(2) ck Q(3) D(0) D(1) D(2) D(3) Student ID: __________________ Name: ______________________ Date:_______________ (Submit this at the end of the lecture.) t