library IEEE; -(vivado 2014 34 ok) use IEEE std logic_1164.all; entity asyn_ counter is port( clk: in std logic reset: in std logic counto, count1, count2, count3: inout std logic); end asyn counter; architecture Behavioral of asyn counter is process(reset, clk, counto, count1, count2 )begin if reset =1 then counto<=0: count1<=0 count2<=0; count3<= 0 else if(rising_edge(clk) then counto < not counto; d if if(rising_edge(counto)) then count1 < not count 1 nd if; if(rising_edge(count 1 )) then count2<= not count 2: end if: if(rising_edge count2 ) then count3<= not count3: end if: end if: end process; end behavioral: VHDL 6. examples of FSM ver. 8a• library IEEE; --(vivado 2014.34 ok) • use IEEE.std_logic_1164.all; • entity asyn_counter is • port( clk: in std_logic; • reset: in std_logic; • count0,count1, count2, count3: inout std_logic); • end asyn_counter; • architecture Behavioral of asyn_counter is • begin • process(reset, clk, count0, count1, count2) begin • if reset ='1' then • count0<= '0'; count1<= '0'; • count2<= '0'; count3<= '0'; • else • if(rising_edge(clk)) then count0 <= not count0; • end if; • if(rising_edge(count0)) then count1 <= not count1; • end if; • if(rising_edge(count1)) then count2<= not count2; • end if; • if(rising_edge(count2)) then count3<= not count3; • end if; • end if; • end process; • end Behavioral; VHDL 6. examples of FSM ver.8a 6