4-bit asynchronous clock down counter(Moore) CLK in STD logic: RESET in STD logiC: CoUNTO, CoUNT1, CoUNT2, COUNT3: inout STD LOGIC; architecture Behavioral of asyn_counter is_ Asynchronous clocks process(reset, clk, counfo, count1, count2)begin if reset= 1' then Each line is countO<=0 count1<=0 an Flip-Flop count2<0 count3<=0 else if(rising_edge(clk ))then counto not counto end if if(rising_edge(counto))then count1 < not count1 ena if(rising_edge(count1 ))then count2< not count2 end if eage( coun nt2)then count3<= not count3 if nd if. end process A 4-BIT DOWN COUNTER end behavioral VHDL 6. examples of FSM ver. 8a4-bit Asynchronous clock down counter (Moore) CLK: in STD_LOGIC; RESET: in STD_LOGIC; COUNT0, COUNT1 , COUNT2 , COUNT3 : inout STD_LOGIC; VHDL 6. examples of FSM ver.8a 5 Each line is an Flip-Flop Asynchronous clocks A 4-bit down counter