Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 PINNING Pin configuration DATA0>山 园vou3 ATA<3>4 DATA<4> 6 23 XTAL1 DATA7>回 回 RESET N ALE 10 19 EOT_N DMACK N SUSPEND12 17 DMREQ 16 WR_N INT_N 14 图RDN Pin Description N SYMBOL TYPE DESCRIPTION PINSYMBOLTYPE DESCRIPTION 1 DATA <0> 102 Bit0 of bi-directional data 15 RD_N Read Strobe(Active Low). Slew-rate controlled 16 WR N I Write Strobe(Active Low). DATA <1> 102 Bit 1 of bi-directional data. 3|DATA<2>102 2 of bi-directional data 18DMACK_N IDMA Acknowledge(Active Low). Slew-rate controlled End of DMA Transfer(Active Low) 4DATA <3>102 Bit 3 of bi-directional data. Double up as vbus sensing. EOTN Slew-rate controlled 19 EOT_N I is only valid when asserted together vith dMAcK N and either RD n or 6DATA <4> 102Bit 4 of bi-directional data. 20 RESET N Slew-rate controlled Built-in Power-On-Reset circuit 7DATA <5>102 Bit 5 of bi-directional data. present on chip, so pin can be tied HIGH to Vo 8 DATA <6> 102 Bit 6 of bi-directional data. 21[cL OD8GoodLink LED indicator(Active Low) Slew-rate controlled CRystal Connection 1(6 MHz) 9 DATA <7> 102 Bit 7 of bi-directional data 23XTAL2 o Crystal Connection 2(6 MHz). If Slew-rate controlled extenal clock signal Address Latch Enable The falling dge is used to close the latch of the XTAi, Is connected to XTAL1, ther 10ALE 24v Voltage supply(4.0-5.5v). address/ data bus. Permanently tied low for separate address/ data bus 3 perate the Ic at3su甲py Chip Select(Active Low) A USB D-data line 12 SUSPEND 1, OD4 Device is in Suspend state. 26 AUSB D+ data line 27V 3CLKOUT 02 Programmable Output Clock P3.3V regulated output To opera (slew-rate controlled) the IC at 3. 3v, supply a 3. 3V to both Vcc and VouT33 pins 14 INT_N OD4 Interrupt(Active Low). NOT struction: A0=0 selects the data 28A0 phase. This bit is a don't care in a OD4 Output Open Drain with 4 mA drive OD8 Output Open Drain with 8 mA drive configuration and should be tied high 102 Input and Output with 2 mA drive Output with 4mA drivePhilips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 7 PINNING Pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 17 18 19 20 21 22 23 24 25 26 27 DATA<0> 28 DATA<1> DATA<2> DATA<3> GND DATA<4> DATA<5> DATA<6> DATA<7> ALE CS_N A0 VOUT3.3 D+ D– VDD XTAL2 XTAL1 RESET_N GL_N EOT_N DMACK_N SUSPEND DMREQ CLKOUT 13 16 WR_N INT_N 14 15 RD_N SV01019 Pin Description PIN SYMBOL TYPE DESCRIPTION 1 DATA <0> IO2 Bit 0 of bi-directional data. Slew-rate controlled. 2 DATA <1> IO2 Bit 1 of bi-directional data. Slew-rate controlled. 3 DATA <2> IO2 Bit 2 of bi-directional data. Slew-rate controlled. 4 DATA <3> IO2 Bit 3 of bi-directional data. Slew-rate controlled. 5 GND P Ground. 6 DATA <4> IO2 Bit 4 of bi-directional data. Slew-rate controlled. 7 DATA <5> IO2 Bit 5 of bi-directional data. Slew-rate controlled. 8 DATA <6> IO2 Bit 6 of bi-directional data. Slew-rate controlled. 9 DATA <7> IO2 Bit 7 of bi-directional data. Slew-rate controlled. 10 ALE I Address Latch Enable. The falling edge is used to close the latch of the address information in a multiplexed address/ data bus. Permanently tied low for separate address/ data bus configuration. 11 CS_N I Chip Select (Active Low). 12 SUSPEND I,OD4 Device is in Suspend state. 13 CLKOUT O2 Programmable Output Clock (slew-rate controlled). 14 INT_N OD4 Interrupt (Active Low). NOTE: 1. O2 : Output with 2 mA drive OD4 : Output Open Drain with 4 mA drive OD8 : Output Open Drain with 8 mA drive IO2 : Input and Output with 2 mA drive O4 : Output with 4mA drive PIN SYMBOL TYPE DESCRIPTION 15 RD_N I Read Strobe (Active Low). 16 WR_N I Write Strobe (Active Low). 17 DMREQ O4 DMA Request. 18 DMACK_N I DMA Acknowledge (Active Low). 19 EOT_N I End of DMA Transfer (Active Low). Double up as Vbus sensing. EOT_N is only valid when asserted together with DMACK_N and either RD_N or WR_N. 20 RESET_N I Reset (Active Low and asynchronous). Built-in Power-On-Reset circuit present on chip, so pin can be tied HIGH to VCC. 21 GL_N OD8 GoodLink LED indicator (Active Low) 22 XTAL1 I Crystal Connection 1 (6 MHz) 23 XTAL2 O Crystal Connection 2 (6 MHz). If external clock signal, instead of crystal, is connected to XTAL1, then XTAL2 should be floated. 24 VCC P Voltage supply (4.0 – 5.5V). To operate the IC at 3.3V, supply 3.3V to both VCC and VOUT3.3 pins. 25 D– A USB D– data line 26 D+ A USB D+ data line 27 VOUT3.3 P 3.3V regulated output. To operate the IC at 3.3V, supply a 3.3V to both VCC and VOUT3.3 pins 28 A0 I Address bit. A0=1 selects command instruction; A0=0 selects the data phase. This bit is a don’t care in a multiplexed address and data bus configuration and should be tied high