INTEGRATED CIRCUITS DATA SHEET PDIUSBD12 USB interface device with parallel bus Product specification 1999Jan08 Supersedes data of 1998 Sep 24 Philips Semiconductors E PHILIPS
PDIUSBD12 USB interface device with parallel bus Product specification Supersedes data of 1998 Sep 24 1999 Jan 08 INTEGRATED CIRCUITS
Philips semiconductors Product specification USB interface device with parallel bus PDIUSBD12 FEATURES DE SCRIPTION The PDIUSBD12 is a cost and feature-optimized USB device. It normally used in microcontroller-based systems and communicates High performance USB interface device with integrated SIE, with the system microcontroller over the high speed FIFO memory, transceiver and voltage regulator general-purpose parallel interface. It also supports local DMA Compliant with most Device Class specifications transfer High-speed (2 Mbytes) parallel interface to any external This modular approach to implementing a USB interface allows the designer to choose the optimum system microcontroller from the available wide variety. This flexibility cuts down the development e Fully autonomous DMA operation time, risks, and costs by allowing the use of the existing architecture and minimize firmware investments This results the fastest way e Integrated 320 bytes of multi-configuration FIFO memory to develop the most cost-effective USB peripheral solution Double buffering scheme for main endpoint increases throughput The PDIUSBD 12 fully conforms to the USB specification Rev. 1.1 and eases real time data transfer it is also designed to be compliant with most device class 1MByte/s data transfer rate achievable in Bulk mode, 1Mbit/s data specifications: Imaging Class, Mass Storage Devices, transfer rate achievable in isochronous mode Communication Devices, Printing Devices, and Human Interface Devices. As such, the PDIUSBD12 is ideally suited for many peripherals like Printer, Scanner, External Mass Storage(Zip Drive). Digital Still Camera, etc. It offers an immediate cost reduction for Controllable Lazy Clock output during suspend applications that currently use SCSI implementations Software controllable connection to the USB bus( SoftConnectTM The PDIUSBD12 low suspend power consumption along with the Good USB connection indicator that blinks with traffic Lazy clock output allows for easy implementation of equipment that is compliant to the ACPl, OnNOW, and USB power management requirements. The low operating power allows the implementation of Programmable clock frequency output bus-powered peripherals Complies with the ACPL, OnNOW, and USB power management requirements ble quency cryst oscillator, and integration of termination features contribute to significant cost savings in the system 0 Available in So28 and TSSOP28 pin packages implementation and at the same time ease the implementation of advanced USB functionality into the peripherals ● Full industrial grade operation from-40to+85°C Higher than 8kV in-circuit ESD protection lowers cost of extra Full-scan design with high fault coverage(99%)ensures high e Operation with dual voltages: 3.3+0.3v or extended 5V supply range of 3.6-5.5V e Multiple interrupt modes to facilitate both bulk and isochronous transfers ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICANORTH AMERICAPKGDWG# 28-pin plastic so 40°cto+85°C PDIUSBD12 D PDIUSBD12 D sOT136-1 28-pin plastic TSSOP -40°cto+85°C PDIUSBD12 PW PDUSBD12PWDHSOT361-1 1999Jan08 853-211020620
Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 2 853–2110 20620 FEATURES • Complies with the Universal Serial Bus specification Rev. 1.1 • High performance USB interface device with integrated SIE, FIFO memory, transceiver and voltage regulator • Compliant with most Device Class specifications • High-speed (2 Mbytes/s) parallel interface to any external microcontroller/microprocessor • Fully autonomous DMA operation • Integrated 320 bytes of multi-configuration FIFO memory • Double buffering scheme for main endpoint increases throughput and eases real time data transfer • 1MByte/s data transfer rate achievable in Bulk mode, 1Mbit/s data transfer rate achievable in Isochronous mode • Bus-powered capability with very good EMI performance • Controllable LazyClock output during suspend • Software controllable connection to the USB bus (SoftConnect) • Good USB connection indicator that blinks with traffic (GoodLink) • Programmable clock frequency output • Complies with the ACPI, OnNOW, and USB power management requirements • Internal power-on reset and low voltage reset circuit • Available in SO28 and TSSOP28 pin packages • Full industrial grade operation from –40 to +85°C • Higher than 8kV in-circuit ESD protection lowers cost of extra components • Full-scan design with high fault coverage (>99%) ensures high quality • Operation with dual voltages: 3.3 ± 0.3V or extended 5V supply range of 3.6 – 5.5V • Multiple interrupt modes to facilitate both bulk and isochronous transfers DESCRIPTION The PDIUSBD12 is a cost and feature-optimized USB device. It is normally used in microcontroller-based systems and communicates with the system microcontroller over the high speed general-purpose parallel interface. It also supports local DMA transfer. This modular approach to implementing a USB interface allows the designer to choose the optimum system microcontroller from the available wide variety. This flexibility cuts down the development time, risks, and costs by allowing the use of the existing architecture and minimize firmware investments. This results in the fastest way to develop the most cost-effective USB peripheral solution. The PDIUSBD12 fully conforms to the USB specification Rev. 1.1. It is also designed to be compliant with most device class specifications: Imaging Class, Mass Storage Devices, Communication Devices, Printing Devices, and Human Interface Devices. As such, the PDIUSBD12 is ideally suited for many peripherals like Printer, Scanner, External Mass Storage (Zip Drive), Digital Still Camera, etc. It offers an immediate cost reduction for applications that currently use SCSI implementations. The PDIUSBD12 low suspend power consumption along with the LazyClock output allows for easy implementation of equipment that is compliant to the ACPI, OnNOW, and USB power management requirements. The low operating power allows the implementation of bus-powered peripherals. In addition, it also incorporates features like SoftConnect, GoodLink, programmable clock output, low frequency crystal oscillator, and integration of termination resistors. All of these features contribute to significant cost savings in the system implementation and at the same time ease the implementation of advanced USB functionality into the peripherals. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 28-pin plastic SO –40°C to +85°C PDIUSBD12 D PDIUSBD12 D SOT136-1 28-pin plastic TSSOP –40°C to +85°C PDIUSBD12 PW PDUSBD12PW DH SOT361-1
Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 BLOCK DIAGRAM 6 MHz UPSTREAM INTEGRATED BIT CLOCK 1.5k9 ANALOG PHILIPS MEMORY VOLTAGE REGULATOR NOTE. This is a conceptual block diagram and does not include each individual signa Analog Transceiver SoftconnectTw The integrated transceiver interfaces directly to the USB cables The connection to the USB is accomplished by bringing D+(for hrough termination resistors high-speed USB device) high through a 1.5 kQ pull-up resistor. In Voltage Regulator the PDIUSBD12, the 1.5 k@2 pull-up resistor is integrated on-chip and is not connected to Vcc by default. The connection is A 3. 3v regulator is integrated on-chip to supply og established through a command sent by the external/system transceiver. This voltage is also provided as ar connect to microcontroller. This allows the system microcontroller to complete the external 1.5 k]2 pull-up resistor. Altematively, USBD12 its initialization sequence before deciding to establish connection to provides Soft Connectm technology with integrated 1.5 k@2 pull-up the USB. Re-initialization of the usb bus connection can also be performed without requiring to pull out the cable PLL The PDIUSBD12 will check for USB VBUS availability before the A 6 MHz to 48 MHz clock multiplier PLL (Phase-Locked Loop) is connection can be established. VBUS sensing is provided through integrated on-chip. This allows for the use of low-cost 6 MHz crystal EOT N pin. See the pin description for details. Sharing of VBUs EMI is also minimized due to the lower frequency crystal. No sensing and EOT N can be easily accomplished by using VBUS external components are needed for the operation of the PLL. voltage as the pull up voltage for the normally open-drain output of the dma controller pir ecove It should be noted that the tolerance of the intemal resistors is The bit clock recovery circuit recovers the clock from the incomin k ugher(25%)than that specified by the USB specification(5%) USB data stream using 4X over-sampling principle. It is able to track jitter and frequency drift specified by the USB specification. However, the overall VsE voltage specification for the connection can still be met with good margin. The decision to make sure of this Philips Serial Interface Engine(PSI) feature lies with the users he Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention SoftconnectM is a patent pending technology from Philips The functions of this block include: synchronization patten recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation, PID verification/generation, address ecognition, and hands
Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 3 BLOCK DIAGRAM PARALLEL AND DMA INTERFACE ANALOG TX/RX PHILIPS SIE INTEGRATED RAM BIT CLOCK RECOVERY MEMORY MANAGEMENT UNIT 6 MHz D+ D– UPSTREAM PORT PLL SoftConnect D+ 3.3V 1.5k SV00859 VOLTAGE REGULATOR NOTE: * This is a conceptual block diagram and does not include each individual signal. Analog Transceiver The integrated transceiver interfaces directly to the USB cables through termination resistors. Voltage Regulator A 3.3V regulator is integrated on-chip to supply the analog transceiver. This voltage is also provided as an output to connect to the external 1.5 kΩ pull-up resistor. Alternatively, the PDIUSBD12 provides SoftConnect technology with integrated 1.5 kΩ pull-up resistor. PLL A 6 MHz to 48 MHz clock multiplier PLL (Phase-Locked Loop) is integrated on-chip. This allows for the use of low-cost 6 MHz crystal. EMI is also minimized due to the lower frequency crystal. No external components are needed for the operation of the PLL. Bit Clock Recovery The bit clock recovery circuit recovers the clock from the incoming USB data stream using 4X over-sampling principle. It is able to track jitter and frequency drift specified by the USB specification. Philips Serial Interface Engine (PSIE) The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. The functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation, PID verification/generation, address recognition, and handshake evaluation/generation. SoftConnect The connection to the USB is accomplished by bringing D+ (for high-speed USB device) high through a 1.5 kΩ pull-up resistor. In the PDIUSBD12, the 1.5 kΩ pull-up resistor is integrated on-chip and is not connected to VCC by default. The connection is established through a command sent by the external/system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establish connection to the USB. Re-initialization of the USB bus connection can also be performed without requiring to pull out the cable. The PDIUSBD12 will check for USB VBUS availability before the connection can be established. VBUS sensing is provided through EOT_N pin. See the pin description for details. Sharing of VBUS sensing and EOT_N can be easily accomplished by using VBUS voltage as the pull up voltage for the normally open-drain output of the DMA controller pin. It should be noted that the tolerance of the internal resistors is higher (25%) than that specified by the USB specification (5%). However, the overall VSE voltage specification for the connection can still be met with good margin. The decision to make sure of this feature lies with the users. SoftConnect is a patent pending technology from Philips Semiconductors
Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 GoodLinkTM Parallel and DMA Interface Good USB connection indication is provided through GoodLinkTM A generic parallel interface is defined for ease-of-use, speed, and technology. During enumeration, the LED indicator will blink ON allows direct interfacing to major microcontrollers. To a momentarily corresponding to the enumeration traffic. When the microcontroller, the PDIUSBD12 appears as a memory device with PDIUSBD12 is successfully enumerated and configured, the LED 8-bit data bus and 1 address bit(occupying 2 locations). The indicator will be permanently ON. Subsequent successful (with PDIUSBD12 supports both multiplexed and non-multiplexed acknowledgement) transfer to and from the PDIUSBD12 will blink address and data bus. The PDIUSBD12 also supports DMA (Direct OFF the LED During suspend, the LED will be OFF. Memory Access)transfer which allows the main endpoint(endpoint This feature provides a user-friendly indicator on the status of the 2)to directly transfer to and from the local shared memory. Both USB device. the connected hub and the usB traffic. it is a useful single cycle and burst mode DMA transfers are supported field diagnostics tool to isolate faulty equipment. This feature helps Example of parallel interface to a dedicated 80c51 lower field support and hotline costs. In this example, the ALE is permanently tied LOW to signify a emory Management Unit(MMU)and eparate address and data bus configuration. The A0 pin of the Integrated RAM PDIUSBD12 connects to any of the 80C51 WO port. This port The MMU and the integrated RAM buffer the difference in speed controls command or data phase to the PDIUSBD12. The between USB, running in bursts of 12 Mbits/s and the parallel multiplexed address and data bus of the 80C51 can now be connected directly to the data bus of the PDIUSBD 12. The address interface to the microcontroller this allows the microcontroller to read and write USB packets at its own speed phase will simply be ignored by the PDIUSBD12. The crystal input of the 80C51 can be supplied by the CLKoUT output of the PDIUSBD12 80c51 INT N DATA [7: 0 P.70.0yA:0 RD N CLKOUT XTAL1 CS N
Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 4 GoodLink Good USB connection indication is provided through GoodLink technology. During enumeration, the LED indicator will blink ON momentarily corresponding to the enumeration traffic. When the PDIUSBD12 is successfully enumerated and configured, the LED indicator will be permanently ON. Subsequent successful (with acknowledgement) transfer to and from the PDIUSBD12 will blink OFF the LED. During suspend, the LED will be OFF. This feature provides a user-friendly indicator on the status of the USB device, the connected hub and the USB traffic. It is a useful field diagnostics tool to isolate faulty equipment. This feature helps lower field support and hotline costs. Memory Management Unit (MMU) and Integrated RAM The MMU and the integrated RAM buffer the difference in speed between USB, running in bursts of 12 Mbits/s and the parallel interface to the microcontroller. This allows the microcontroller to read and write USB packets at its own speed. Parallel and DMA Interface A generic parallel interface is defined for ease-of-use, speed, and allows direct interfacing to major microcontrollers. To a microcontroller, the PDIUSBD12 appears as a memory device with 8-bit data bus and 1 address bit (occupying 2 locations). The PDIUSBD12 supports both multiplexed and non-multiplexed address and data bus. The PDIUSBD12 also supports DMA (Direct Memory Access) transfer which allows the main endpoint (endpoint 2) to directly transfer to and from the local shared memory. Both single cycle and burst mode DMA transfers are supported. Example of parallel interface to a dedicated 80C51 In this example, the ALE is permanently tied LOW to signify a separate address and data bus configuration. The A0 pin of the PDIUSBD12 connects to any of the 80C51 I/O port. This port controls command or data phase to the PDIUSBD12. The multiplexed address and data bus of the 80C51 can now be connected directly to the data bus of the PDIUSBD12. The address phase will simply be ignored by the PDIUSBD12. The crystal input of the 80C51 can be supplied by the CLKOUT output of the PDIUSBD12. PDIUSBD12 80C51 INT_N A0 DATA [7:0] WR_N RD_N CLKOUT CS_N ALE XTAL1 –RD/P3.7 –WR/P3.6 P [0.7:0.0]/AD [7:0] ANY I/O PORT (e.g. P3.3) –INTO/P3.2 SV00870
Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 DMA TRANSFER Direct Memory Address(DMA) allows an efficient transfer of a block transfer(bulk and interrupt), the buffer needs to be completely filled of data between the host and the local shared memory. Using a up by the DMA write operation before the data is sent to the host. controller. data transfer between the pdiusbd12 main The only exception is at the end of DMA transfer when the reception oint(endpoint 2)and the local shared memory can happen of EOT N will stop DMA write operation and the buffer content will autonomously without local CPU intervention. be sent to the host on the next iN token Preceding any DMA transfer, the local CPU receives from the host For isochronous transfer the local cpu and dma controller has to the necessary setup information and programs the DMA controller guarantee that they are able to sink or source the maximum packet accordingly. Typically, the DMA controller is setup for demand size in one USB frame(1 ms) transfer mode and the byte count register and the address counter are programmed with the right values. In this mode, transfers occur The assertion of DMACK N will automatically selects the main only when the PDIUSBD12 requests them and terminated when the endpoint(endpoint 2) regardless of the current selected endpoint byte count register reaches zero. After the DMA controller has been The DMA operation of the PDIUSBD12 can be interleaved with programmed, the dMa enable bit of the PDIUSBD12 is set by the normal l/o access to other endpoints local cpu to initiate the transfer DMA operation can be terminated by resetting the DMA enable The PDIUSBD12 can be programmed for single cycle DMA or burst register bit or the assertion of EOT N together with DMACK N and mode DMA In single cycle DMA, the DMREQ is deactivated for either rd n or Wr n every single acknowledgement by the DMACK_N before be for PDIUSBD12 supports DMA transfer in a single address mode and it can also work in dual address mode of the dma controller. In the the number of bursts programmed in the device before retuming single address mode, DMA transfer is done via the DREQ, inactive. This process continues until the PDIUSBD12 receives a DMACK N, EOT N. WR N and Rd N control lines. In the dual DMA termination notice through EOT N. This will generate an interrupt to notify the local CPU that DMA operation is completed. address mode, DMREQ, DMACK N and EoT N are Not usec instead CS_N, WR N and RD_N control signals are used. The vO For DMA read operation, the dMREQ will only be activated mode Transfer Protocol of pdiusbd 12 needs to be followed the whenever the buffer is full signifying that the host has successfully source of the DMAC is accessed during the read cycle, and the transferred a packet to the PDIUSBD12. With the double buffering destination accessed during the write cycle. Transfer needs to be scheme, the host can start filling up the second buffer while the first done in two separate bus cycles, storing the data temporarly in the buffer is being read out. This parallel processing increases effective DMAC oughput. For the case when the host does not fill up the buffer ompletely (less than 64 bytes or 128 bytes for single direction ISo ENDPOINT DESCRIPTION configuration), the DMREQ will be deactivated at the last byte of the The PDIUSBD12 endpoints are generic enough to be used by buffer regardless of the current DMA burst count. It will be asserted various device classes ranging from Imaging, Printer, Mass Storage again on the next packet with a refreshed DMA burst count. and Communication device classes. The PDIUSBD12 endpoints can Similarly, for DMA write operation, the DMRI be configured for 4 modes depending on the"Set Mode" command whenever the buffer is not full. when the but The 4 modes are: packet is sent over to the host on the next IN Mode 0(Non-ISO Mode): no Isochronous transfer be reactivated if the transfer was successful. also the double Mode 1(ISO-OUT Mode ): Isochronous output only buffering scheme here will improve throughput For non-isochronous Mode 2(ISo-IN Mode): Isochronous input only tra Mode 3(So-IO Mode) sychronous input and ou
Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 5 DMA TRANSFER Direct Memory Address (DMA) allows an efficient transfer of a block of data between the host and the local shared memory. Using a DMA controller, data transfer between the PDIUSBD12 main endpoint (endpoint 2) and the local shared memory can happen autonomously without local CPU intervention. Preceding any DMA transfer, the local CPU receives from the host the necessary setup information and programs the DMA controller accordingly. Typically, the DMA controller is setup for demand transfer mode and the byte count register and the address counter are programmed with the right values. In this mode, transfers occur only when the PDIUSBD12 requests them and terminated when the byte count register reaches zero. After the DMA controller has been programmed, the DMA enable bit of the PDIUSBD12 is set by the local CPU to initiate the transfer. The PDIUSBD12 can be programmed for single cycle DMA or burst mode DMA. In single cycle DMA, the DMREQ is deactivated for every single acknowledgement by the DMACK_N before being asserted again. In burst mode DMA, the DMREQ is held active for the number of bursts programmed in the device before returning inactive. This process continues until the PDIUSBD12 receives a DMA termination notice through EOT_N. This will generate an interrupt to notify the local CPU that DMA operation is completed. For DMA read operation, the DMREQ will only be activated whenever the buffer is full signifying that the host has successfully transferred a packet to the PDIUSBD12. With the double buffering scheme, the host can start filling up the second buffer while the first buffer is being read out. This parallel processing increases effective throughput. For the case when the host does not fill up the buffer completely (less than 64 bytes or 128 bytes for single direction ISO configuration), the DMREQ will be deactivated at the last byte of the buffer regardless of the current DMA burst count. It will be asserted again on the next packet with a refreshed DMA burst count. Similarly, for DMA write operation, the DMREQ remains active whenever the buffer is not full. When the buffer is filled up, the packet is sent over to the host on the next IN token and DMREQ will be reactivated if the transfer was successful. Also, the double buffering scheme here will improve throughput. For non-isochronous transfer (bulk and interrupt), the buffer needs to be completely filled up by the DMA write operation before the data is sent to the host. The only exception is at the end of DMA transfer when the reception of EOT_N will stop DMA write operation and the buffer content will be sent to the host on the next IN token. For isochronous transfer, the local CPU and DMA controller has to guarantee that they are able to sink or source the maximum packet size in one USB frame (1 ms). The assertion of DMACK_N will automatically selects the main endpoint (endpoint 2) regardless of the current selected endpoint. The DMA operation of the PDIUSBD12 can be interleaved with normal I/O access to other endpoints. DMA operation can be terminated by resetting the DMA enable register bit or the assertion of EOT_N together with DMACK_N and either RD_N or WR_N. PDIUSBD12 supports DMA transfer in a single address mode and it can also work in dual address mode of the DMA controller. In the single address mode, DMA transfer is done via the DREQ, DMACK_N, EOT_N, WR_N and RD_N control lines. In the dual address mode, DMREQ, DMACK_N and EOT_N are NOT used, instead CS_N, WR_N and RD_N control signals are used. The I/O mode Transfer Protocol of PDIUSBD12 needs to be followed. The source of the DMAC is accessed during the read cycle, and the destination accessed during the write cycle. Transfer needs to be done in two separate bus cycles, storing the data temporarily in the DMAC. ENDPOINT DESCRIPTION The PDIUSBD12 endpoints are generic enough to be used by various device classes ranging from Imaging, Printer, Mass Storage and Communication device classes. The PDIUSBD12 endpoints can be configured for 4 modes depending on the “Set Mode” command. The 4 modes are: Mode 0 (Non-ISO Mode): no Isochronous transfer Mode 1 (ISO-OUT Mode): Isochronous output only transfer Mode 2 (ISO-IN Mode): Isochronous input only transfer Mode 3 (ISO-IO Mode): Isochronous input and output transfer
Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 MODE O(NON-ISO MODE ENDPOINT ENDPOINT DIRECTION MAX PACKET SIZE NUMBER TRANSFER TYPE ENDPOINT TYPE Default Generic Out Generic 1 Generic Out OUT MODE 1(ISO-OUT MODE) ENDPOINT ENDPOINT TRANSFER TYPE ENDPOINT TYPE DIRECTION MAX PACKET SIZE NUMBER INDEX (BYTES) Control out OUT 0 Control Generic Out Generic OUT Generic In Generic Isochronous OUT MODE 2(ISO-IN MODE) ENDPOINT ENDPOINT TRANSFER TYPE ENDPOINT TYPE DIRECTION MAX PACKET SIZE (BYTES) 0 Control out OUT Control in Default Generic Out Gene OUT 16 1 Generic Isochronous 1284 MODE 3(ISo-IO MODE ENDPOINT ENDPOINT MAX PACKET SIZE NUMBER INDEX TRANSFER TYPE ENDPOINT TYPE DIRECTION YYTES Control Out OUT ontrol in Default 012345 Generic Out OUT 1 Generic Generic In sychronous out OUT 6 Isochronous In 1. Generic endpoint can be used either as Bulk or Interrupt endpoint 2. The main endpoint (endpoint number 2) is double-buffered to ease synchronization with the real time applications and to increase 3. DMA access is for the main endpoint (endpoint number 2)only. 4. Denotes double buffering The size shown is for a single buffer. MAIN ENDPOINT The main endpoint (endpoint number 2) is special in a few ways. It is the primary endpoint for sinking or sourcing relatively large data. As such, it implements a host of features to ease the task of transferring large data: 1. Double buffering. This allows parallel operation between USB access and local CPU access thus increasing throughput Buffer switching is handled au cally. This results in transparent buffer operatio ports for DMA (Direct Memory Access)operation. This can be interleaved with normal l/O operation to other endpoints 3. Automatic pointer handling during DMA operation. No local CPU intervention is necessary when 'crossing the buffer boundary. 4. Configurable for either isochronous transfer or non-isochronous(bulk and interrupt) transfer
Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 6 MODE 0 (NON-ISO MODE): ENDPOINT NUMBER ENDPOINT INDEX TRANSFER TYPE ENDPOINT TYPE DIRECTION MAX. PACKET SIZE (BYTES) 0 0 Control Out Default OUT 16 0 1 Control In Default IN 16 1 2 Generic Out Generic OUT 16 1 3 Generic In Generic IN 16 2 4 Generic Out Generic OUT 644 2 5 Generic In Generic IN 644 MODE 1 (ISO-OUT MODE): ENDPOINT NUMBER ENDPOINT INDEX TRANSFER TYPE ENDPOINT TYPE DIRECTION MAX. PACKET SIZE (BYTES) 0 0 Control Out Default OUT 16 0 1 Control In Default IN 16 1 2 Generic Out Generic OUT 16 1 3 Generic In Generic IN 16 2 4 Isochronous Out Isochronous OUT 1284 MODE 2 (ISO-IN MODE): ENDPOINT NUMBER ENDPOINT INDEX TRANSFER TYPE ENDPOINT TYPE DIRECTION MAX. PACKET SIZE (BYTES) 0 0 Control Out Default OUT 16 0 1 Control In Default IN 16 1 2 Generic Out Generic OUT 16 1 3 Generic In Generic IN 16 2 5 Isochronous In Isochronous IN 1284 MODE 3 (ISO-IO MODE): ENDPOINT NUMBER ENDPOINT INDEX TRANSFER TYPE ENDPOINT TYPE DIRECTION MAX. PACKET SIZE (BYTES) 0 0 Control Out Default OUT 16 0 1 Control In Default IN 16 1 2 Generic Out Generic OUT 16 1 3 Generic In Generic IN 16 2 4 Isochronous Out Isochronous OUT 644 2 5 Isochronous In Isochronous IN 644 NOTES: 1. Generic endpoint can be used either as Bulk or Interrupt endpoint 2. The main endpoint (endpoint number 2) is double-buffered to ease synchronization with the real time applications and to increase throughput. 3. DMA access is for the main endpoint (endpoint number 2) only. 4. Denotes double buffering. The size shown is for a single buffer. MAIN ENDPOINT The main endpoint (endpoint number 2) is special in a few ways. It is the primary endpoint for sinking or sourcing relatively large data. As such, it implements a host of features to ease the task of transferring large data: 1. Double buffering. This allows parallel operation between USB access and local CPU access thus increasing throughput. Buffer switching is handled automatically. This results in transparent buffer operation. 2. Supports for DMA (Direct Memory Access) operation. This can be interleaved with normal I/O operation to other endpoints. 3. Automatic pointer handling during DMA operation. No local CPU intervention is necessary when ‘crossing’ the buffer boundary. 4. Configurable for either isochronous transfer or non-isochronous (bulk and interrupt) transfer
Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 PINNING Pin configuration DATA0>山 园vou3 ATA4 DATA 6 23 XTAL1 DATA7>回 回 RESET N ALE 10 19 EOT_N DMACK N SUSPEND12 17 DMREQ 16 WR_N INT_N 14 图RDN Pin Description N SYMBOL TYPE DESCRIPTION PINSYMBOLTYPE DESCRIPTION 1 DATA 102 Bit0 of bi-directional data 15 RD_N Read Strobe(Active Low). Slew-rate controlled 16 WR N I Write Strobe(Active Low). DATA 102 Bit 1 of bi-directional data. 3|DATA102 2 of bi-directional data 18DMACK_N IDMA Acknowledge(Active Low). Slew-rate controlled End of DMA Transfer(Active Low) 4DATA 102 Bit 3 of bi-directional data. Double up as vbus sensing. EOTN Slew-rate controlled 19 EOT_N I is only valid when asserted together vith dMAcK N and either RD n or 6DATA 102Bit 4 of bi-directional data. 20 RESET N Slew-rate controlled Built-in Power-On-Reset circuit 7DATA 102 Bit 5 of bi-directional data. present on chip, so pin can be tied HIGH to Vo 8 DATA 102 Bit 6 of bi-directional data. 21[cL OD8GoodLink LED indicator(Active Low) Slew-rate controlled CRystal Connection 1(6 MHz) 9 DATA 102 Bit 7 of bi-directional data 23XTAL2 o Crystal Connection 2(6 MHz). If Slew-rate controlled extenal clock signal Address Latch Enable The falling dge is used to close the latch of the XTAi, Is connected to XTAL1, ther 10ALE 24v Voltage supply(4.0-5.5v). address/ data bus. Permanently tied low for separate address/ data bus 3 perate the Ic at3su甲py Chip Select(Active Low) A USB D-data line 12 SUSPEND 1, OD4 Device is in Suspend state. 26 AUSB D+ data line 27V 3CLKOUT 02 Programmable Output Clock P3.3V regulated output To opera (slew-rate controlled) the IC at 3. 3v, supply a 3. 3V to both Vcc and VouT33 pins 14 INT_N OD4 Interrupt(Active Low). NOT struction: A0=0 selects the data 28A0 phase. This bit is a don't care in a OD4 Output Open Drain with 4 mA drive OD8 Output Open Drain with 8 mA drive configuration and should be tied high 102 Input and Output with 2 mA drive Output with 4mA drive
Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 7 PINNING Pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 17 18 19 20 21 22 23 24 25 26 27 DATA 28 DATA DATA DATA GND DATA DATA DATA DATA ALE CS_N A0 VOUT3.3 D+ D– VDD XTAL2 XTAL1 RESET_N GL_N EOT_N DMACK_N SUSPEND DMREQ CLKOUT 13 16 WR_N INT_N 14 15 RD_N SV01019 Pin Description PIN SYMBOL TYPE DESCRIPTION 1 DATA IO2 Bit 0 of bi-directional data. Slew-rate controlled. 2 DATA IO2 Bit 1 of bi-directional data. Slew-rate controlled. 3 DATA IO2 Bit 2 of bi-directional data. Slew-rate controlled. 4 DATA IO2 Bit 3 of bi-directional data. Slew-rate controlled. 5 GND P Ground. 6 DATA IO2 Bit 4 of bi-directional data. Slew-rate controlled. 7 DATA IO2 Bit 5 of bi-directional data. Slew-rate controlled. 8 DATA IO2 Bit 6 of bi-directional data. Slew-rate controlled. 9 DATA IO2 Bit 7 of bi-directional data. Slew-rate controlled. 10 ALE I Address Latch Enable. The falling edge is used to close the latch of the address information in a multiplexed address/ data bus. Permanently tied low for separate address/ data bus configuration. 11 CS_N I Chip Select (Active Low). 12 SUSPEND I,OD4 Device is in Suspend state. 13 CLKOUT O2 Programmable Output Clock (slew-rate controlled). 14 INT_N OD4 Interrupt (Active Low). NOTE: 1. O2 : Output with 2 mA drive OD4 : Output Open Drain with 4 mA drive OD8 : Output Open Drain with 8 mA drive IO2 : Input and Output with 2 mA drive O4 : Output with 4mA drive PIN SYMBOL TYPE DESCRIPTION 15 RD_N I Read Strobe (Active Low). 16 WR_N I Write Strobe (Active Low). 17 DMREQ O4 DMA Request. 18 DMACK_N I DMA Acknowledge (Active Low). 19 EOT_N I End of DMA Transfer (Active Low). Double up as Vbus sensing. EOT_N is only valid when asserted together with DMACK_N and either RD_N or WR_N. 20 RESET_N I Reset (Active Low and asynchronous). Built-in Power-On-Reset circuit present on chip, so pin can be tied HIGH to VCC. 21 GL_N OD8 GoodLink LED indicator (Active Low) 22 XTAL1 I Crystal Connection 1 (6 MHz) 23 XTAL2 O Crystal Connection 2 (6 MHz). If external clock signal, instead of crystal, is connected to XTAL1, then XTAL2 should be floated. 24 VCC P Voltage supply (4.0 – 5.5V). To operate the IC at 3.3V, supply 3.3V to both VCC and VOUT3.3 pins. 25 D– A USB D– data line 26 D+ A USB D+ data line 27 VOUT3.3 P 3.3V regulated output. To operate the IC at 3.3V, supply a 3.3V to both VCC and VOUT3.3 pins 28 A0 I Address bit. A0=1 selects command instruction; A0=0 selects the data phase. This bit is a don’t care in a multiplexed address and data bus configuration and should be tied high
Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 COMMAND SUMMARY COMMANDNAME RECIPIENT DATA PHASE Initialization Commands Set Address/Enable Device Write 1 byte Set Endpoint Enable Device Write 1 byte Set DMA FBh Write/Read 1 byte Data Flow Commands Select Endpoint Control out Read 1 byte(optional) Control IN 01h Read 1 byte(optional) Endpoint 1 OUT Read 1 byte(optional) Endpoint 1 IN Read 1 byte(optional Endpoint 2 OUT Read 1 byte(optional) Endpoint 2 IN 05h Read 1 byte(optional) Transaction Status Control oUt Read 1 byte Endpoint 1 OUT 42h Endpoint 1 IN Read 1 byte ndpoint 2 OU Read1byte Read 1 byte ead Buffer Selected Endpoint FO Write Buffer Selected Endpoint F tes Set Endpoint Status Control oUT Write 1 byte Control IN 41h Write 1 byte Endpoint 1 OUT 42h Write 1 byte Write 1 byte dpoint 2 OUT 44h Write 1 byte Endpoint 2 IN 45h Write 1 byte Acknowledge Setup Selected Endpoint Validate Buffer Selected Endpoint FAh General Commands Send resum F6h Read Current Frame Number Read 1 or 2 byte
Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 8 COMMAND SUMMARY COMMAND NAME RECIPIENT CODING DATA PHASE Initialization Commands Set Address/Enable Device D0h Write 1 byte Set Endpoint Enable Device D8h Write 1 byte Set Mode Device F3h Write 2 bytes Set DMA Device FBh Write/Read 1 byte Data Flow Commands Read Interrupt Register Device F4h Read 2 bytes Select Endpoint Control OUT 00h Read 1 byte (optional) Control IN 01h Read 1 byte (optional) Endpoint 1 OUT 02h Read 1 byte (optional) Endpoint 1 IN 03h Read 1 byte (optional) Endpoint 2 OUT 04h Read 1 byte (optional) Endpoint 2 IN 05h Read 1 byte (optional) Read Last Transaction Status Control OUT 40h Read 1 byte Control IN 41h Read 1 byte Endpoint 1 OUT 42h Read 1 byte Endpoint 1 IN 43h Read 1 byte Endpoint 2 OUT 44h Read 1 byte Endpoint 2 IN 45h Read 1 byte Read Buffer Selected Endpoint F0h Read n bytes Write Buffer Selected Endpoint F0h Write n bytes Set Endpoint Status Control OUT 40h Write 1 byte Control IN 41h Write 1 byte Endpoint 1 OUT 42h Write 1 byte Endpoint 1 IN 43h Write 1 byte Endpoint 2 OUT 44h Write 1 byte Endpoint 2 IN 45h Write 1 byte Acknowledge Setup Selected Endpoint F1h None Clear Buffer Selected Endpoint F2h None Validate Buffer Selected Endpoint FAh None General Commands Send Resume F6h None Read Current Frame Number F5h Read 1 or 2 bytes
Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 COMMAND DESCRIPTION Configuration Byte Command Procedure There are three basic types of commands: Initialization, Data and General commands. Respectively, these are used to initia the function for data flow between the function and the host: o。 POWER ON VALUE RESERVED Initialization Commands NO LAZYCLOCK endpoints. They are also used to set the USB assigned address o Initialization commands are used during the enumeration process of CLOCK RUNNING the usB network. These commands are used to enable the function RESERVED: WRITE O Set Address/ Enable ENDPOINT CONFIGURATION Write 1 byte his command is used to set the USB assigned address and enable A'1' indicates that CLKoUT will not the function switch to Lazy clock A0 indicates that he CLKOUT switches to Lazy Clock 1ms pend pin goes high. The programmed value will not be 0000000 POWER ON VALUE hanged by a bus reset. Clock Running A1 indicates that the internal clocks and ENABLE PLL are always running even during te. A 0 indicates that the ternal clock, crystal oscillator and PLL are stopped whenever not needed To Address he value written becomes the address meet the strict Suspend curren requirement, this bit needs to be set to Enable A 1 enables this function 0. The programmed value will not be changed by a bus reset. Set Endpoint Enable nterrupt mode A1 indicates that all errors and Command D8h NAKing are reported and will generate Write 1 byte an interrupt AO indicates that only OK is reported. The programmed value will he generic/isochronous endpoints can only be enabled when the not be changed by a bus reset. function is enabled via the set Address/Enable command SoftConnectTM A1 indicates that the upstream pull-up sistor will be connected if ybus is available. A '0 means that the upstream 國如 POWER ON VALUE resistor will not be connected. the programmed value will not be changed ENERIC/ISOCHRONOUS ENDPOINTS These two bits set th igurations as follows Mode 0(Non-ISO Mode) Mode 1(ISO-OUT Mode) Generic/isochronous Endpoint A value of 1 indicates the Mode 3 (ISo-I0 Mode) See Endpoint Description for Set Mode F3h The Set Mode command is followed by two data writes The first byte contains the configuration byte values. The second byte is the clock division factor byte
Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 9 COMMAND DESCRIPTION Command Procedure There are three basic types of commands: Initialization, Data Flow and General commands. Respectively, these are used to initialize the function; for data flow between the function and the host; and some general commands. Initialization Commands Initialization commands are used during the enumeration process of the USB network. These commands are used to enable the function endpoints. They are also used to set the USB assigned address. Set Address / Enable Command : D0h Data : Write 1 byte This command is used to set the USB assigned address and enable the function. 76 54 32 0 1 0 0 POWER ON VALUE ADDRESS ENABLE SV00825 0 0 0 0 0 0 Address The value written becomes the address. Enable A ‘1’ enables this function. Set Endpoint Enable Command : D8h Data : Write 1 byte The generic/Isochronous endpoints can only be enabled when the function is enabled via the Set Address/Enable command. 76 54 32 X 1 0 0 POWER ON VALUE GENERIC/ISOCHRONOUS ENDPOINTS RESERVED; WRITE 0 X X X X X X SV00860 Generic/Isochronous Endpoint A value of ‘1’ indicates the generic/isochronous endpoints are enabled. Set Mode Command : F3h Data : Write 2 bytes The Set Mode command is followed by two data writes. The first byte contains the configuration byte values. The second byte is the clock division factor byte. Configuration Byte POWER ON VALUE RESERVED NO LAZYCLOCK CLOCK RUNNING INTERRUPT MODE SoftConnect RESERVED; WRITE 0 ENDPOINT CONFIGURATION 76 54 32 1 1 1 0 0 1 0 0 0 SV00861 0 No LazyClock A ‘1’ indicates that CLKOUT will not switch to LazyClock. A ‘0’ indicates that the CLKOUT switches to LazyClock 1ms after the Suspend pin goes high. LazyClock frequency is 30 kHz ± 40%. The programmed value will not be changed by a bus reset. Clock Running A ‘1’ indicates that the internal clocks and PLL are always running even during Suspend state. A ‘0’ indicates that the internal clock, crystal oscillator and PLL are stopped whenever not needed. To meet the strict Suspend current requirement, this bit needs to be set to ‘0’. The programmed value will not be changed by a bus reset. Interrupt Mode A ‘1’ indicates that all errors and “NAKing” are reported and will generate an interrupt. A ‘0’ indicates that only OK is reported. The programmed value will not be changed by a bus reset. SoftConnect A ‘1’ indicates that the upstream pull-up resistor will be connected if VBUS is available. A ‘0’ means that the upstream resistor will not be connected. The programmed value will not be changed by a bus reset. Endpoint configuration These two bits set the endpoint configurations as follows: Mode 0 (Non-ISO Mode) Mode 1 (ISO-OUT Mode) Mode 2 (ISO-IN Mode) Mode 3 (ISO-IO Mode) See Endpoint Description for more details
Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 Clock Division Factor Byte 321 00000000 POWER ON VALUE [0 X1010POWER ONVALUE DMA BURST K DIVISION F DMA ENABLE RESERVED AUTO RELOAD SOF-ONLY interrupt mode INTERRUPT PIN MODE ENDPOINT INDEX 4 INTERRUPT ENABLE Clock Division Factor The value indicates clock division ENDPOINT INDEX 5 INTERRUPT ENABLE factor for CLKOUT. The output sv863 frequency is 48 MHZ/(N+1) where N is the Clock Division Factor. The reset DMA Burst Selects the burst length for DMA operation value is 11. This will produce the output frequency of 4 MHz which can then be programmed up(or down) by 01 Burst (4 cycle)DMA the user. The minimum value is one giving the range of frequency from 4 11 Burst(16 cycle) DMA to 24 MHz. the minimum value of n DMA Enable is zERo giving a maximum frequency Writing a"1 to this bit will start DMA operation through the assertion of DMREQ of 48 MHz. The maximum value of n The main endpoint buffer needs to be full is ELEVEN givi (for DMA Read) or empty(for DMA Write) equency of 4 MHz. The PDIUSBD12 before DMREQ will be asserted. In a single lesign ensures no glitching during cle DMA mode, the dmreq is y change The prog grammed deactivated upon receiving DMACK N In value will not be changed by a bus burst mode DMA, the dMREQ is deactivated after the number of burst is SET TO ONE This bit needs to be set to 1 prior to exhausted. It is then asserted again for the any DMA read or DMA write lext burst. This process continues until peration. This bit should always be OT_ N is asserted together with DMACK_ N set to 1 after power. It is zero afte and either rd n or wr n which will reset his bit to o and terminate the dma operation. The DMA operation can also be SOF-ONLY interrupt mode Setting this bit to 1 will cause the terminated by writing a 0 to this bit terrupt line to be interrupted due to Start of Frame clock (SOF)ONLY, DMA Direction This bit determines the direction of data flow regardless of the setting of luring a DMA transfer. A1 means external pin-interrupt mode, bit 5 of setDMA. mared memory to PDIUSBD12 (DM Write); a 0 means PDIUSBD12 to the Command FBh Auto reload When this bit is set to 1, the DMA operation will automatically restart. Data Read/write 1 byte The set DMA command is followed by one data write/read to/from Interrupt Pin Mode A0 signifies a normal interrupt pin mode the DMA configuration register. where interrupt is generated as a logical OR of all the bits in the interrupt registers. A" DMA Configuration register ignifies that the interrupt will occur when During DMA operation, the two-byte buffer header(status and byte Start of Frame clock(SoF) is seen on the length information) is not transferred to/from the local CPU. This upstream USB bus. The other normal allows dma data to be continuous and not interleaved by chunks of interrupts are still active these headers For DMA read operation, the header will be skipped by the PDIUSBD12. See Read Buffer command For DMA write Endpoint Index 4 operation, the header will be automatically added by the Interrupt Enable A 1 allows for interrupt to be generated PDIUSBD12. This provides for a clean and simple DMA data whenever the int buffer contains a valid packet. ly turned off for DMA Endpoint Index 5 Interrupt Enable A 1 allows for interrupt to be generated whenever the endpoint buffer is validated (see the Validate Buffer command) orally turned off for DMA operatic reduce unnecessary CPU servicing
Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 10 Clock Division Factor Byte 76 5 4 3 2 1 1 1 0 0 0 X X 1 0 POWER ON VALUE CLOCK DIVISION FACTOR RESERVED SV00862 SET_TO_ONE SOF-ONLY interrupt mode Clock Division Factor The value indicates clock division factor for CLKOUT. The output frequency is 48 MHz/(N+1) where N is the Clock Division Factor. The reset value is 11. This will produce the output frequency of 4 MHz which can then be programmed up (or down) by the user. The minimum value is one giving the range of frequency from 4 to 24 MHz. The minimum value of N is ZERO giving a maximum frequency of 48 MHz. The maximum value of N is ELEVEN giving a minimum frequency of 4 MHz. The PDIUSBD12 design ensures no glitching during frequency change. The programmed value will not be changed by a bus reset. SET_TO_ONE This bit needs to be set to 1 prior to any DMA read or DMA write operation. This bit should always be set to 1 after power. It is zero after power–on reset. SOF-ONLY interrupt mode Setting this bit to 1 will cause the interrupt line to be interrupted due to Start of Frame clock (SOF) ONLY, regardless of the setting of pin-interrupt mode, bit 5 of setDMA. Set DMA Command : FBh Data : Read/Write 1 byte The set DMA command is followed by one data write/read to/from the DMA configuration register. DMA Configuration register During DMA operation, the two-byte buffer header (status and byte length information) is not transferred to/from the local CPU. This allows DMA data to be continuous and not interleaved by chunks of these headers. For DMA read operation, the header will be skipped by the PDIUSBD12. See Read Buffer command. For DMA write operation, the header will be automatically added by the PDIUSBD12. This provides for a clean and simple DMA data transfer. POWER ON VALUE INTERRUPT PIN MODE ENDPOINT INDEX 4 INTERRUPT ENABLE ENDPOINT INDEX 5 INTERRUPT ENABLE 76 54 32 0 1 0 0 0 0 0 0 0 0 DMA ENABLE DMA DIRECTION AUTO RELOAD DMA BURST SV00863 DMA Burst Selects the burst length for DMA operation: 00 Single cycle DMA 01 Burst (4 cycle) DMA 10 Burst (8 cycle) DMA 11 Burst (16 cycle) DMA DMA Enable Writing a ‘1’ to this bit will start DMA operation through the assertion of DMREQ. The main endpoint buffer needs to be full (for DMA Read) or empty (for DMA Write) before DMREQ will be asserted. In a single cycle DMA mode, the DMREQ is deactivated upon receiving DMACK_N. In burst mode DMA, the DMREQ is deactivated after the number of burst is exhausted. It is then asserted again for the next burst. This process continues until EOT_N is asserted together with DMACK_N and either RD_N or WR_N which will reset this bit to ‘0’ and terminate the DMA operation. The DMA operation can also be terminated by writing a ‘0’ to this bit. DMA Direction This bit determines the direction of data flow during a DMA transfer. A ‘1’ means external shared memory to PDIUSBD12 (DMA Write); a ‘0’ means PDIUSBD12 to the external shared memory (DMA Read). Auto Reload When this bit is set to ‘1’, the DMA operation will automatically restart. Interrupt Pin Mode A ‘0’ signifies a normal interrupt pin mode where interrupt is generated as a logical OR of all the bits in the interrupt registers. A ‘1’ signifies that the interrupt will occur when Start of Frame clock (SOF) is seen on the upstream USB bus. The other normal interrupts are still active. Endpoint Index 4 Interrupt Enable A ‘1’ allows for interrupt to be generated whenever the endpoint buffer contains a valid packet. Normally turned off for DMA operation to reduce unnecessary CPU servicing. Endpoint Index 5 Interrupt Enable A ‘1’ allows for interrupt to be generated whenever the endpoint buffer is validated (see the Validate Buffer command). Normally turned off for DMA operation to reduce unnecessary CPU servicing
