或 libraryieee, use 1eee.st td _logic_1164.all; use ieee std_logic_unsigned. all; entity half addis port(a, b:in std_ logic, S,c: out std logic) end half add architecture one ofhalf add is signal temp: std _logic_vector(1 downto 0 egin temp<=(0′&a)+b; s<=temp(o) c<=temp(1) end one或 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity half_add is port(a,b:in std_logic; s,c: out std_logic); end half_add; architecture one of half_add is signal temp: std_logic_vector(1 downto 0); begin temp<=(‘0’&a )+b; s<=temp(0); c<=temp(1); end one;