●半加器的原理图编辑 半加器的原理图编辑 ●文本编辑法 library ieee; useieee.std_logic_1164. all; entity half add is port(a, b:in std _ logic, S,c: out std_ logic) end half add: architecture one ofhalf add is b gin s<=axorb c<=a and b do⚫半加器的原理图编辑 XOR inst AND2 inst1 VCC A INPUT VCC B INPUT OUTPUT S OUTPUT C 半加器的原理图编辑 ⚫文本编辑法 library ieee; use ieee.std_logic_1164.all; entity half_add is port(a,b:in std_logic; s,c: out std_logic); end half_add; architecture one of half_add is begin s<=a xor b; c<=a and b; end one;