布局布线前的准备 进行自动布局布线,需准备下列文件 v Verilog Netlist(v) Timing Library File(lib) Library Exchange Format(lef) Timing Constraint File(sdc) v IO Assigment File (io) Institute of Microelectronics, Peking University 集成电路设计实习一单元实验四 Copyright O 2011-2012 数字系统设计Institute of Microelectronics, Peking University Copyright © 2011-2012 集成电路设计实习－单元实验四 数字系统设计 Page 5 布局布线前的准备  进行自动布局布线，需准备下列文件：  Verilog Netlist (.v)  Timing Library File (.lib)  Library Exchange Format (.lef)  Timing Constraint File (.sdc)  IO Assigment File (.io)